CN113990758B - Fin morphology improvement method - Google Patents
Fin morphology improvement method Download PDFInfo
- Publication number
- CN113990758B CN113990758B CN202111425170.0A CN202111425170A CN113990758B CN 113990758 B CN113990758 B CN 113990758B CN 202111425170 A CN202111425170 A CN 202111425170A CN 113990758 B CN113990758 B CN 113990758B
- Authority
- CN
- China
- Prior art keywords
- fin
- silicon oxide
- fin structure
- silicon nitride
- hard mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 68
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 68
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 67
- 238000000137 annealing Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims description 10
- 238000000231 atomic layer deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000012530 fluid Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000000126 substance Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a fin morphology improvement method, which comprises filling silicon nitride in a concave part of a fin structure, growing silicon oxide on the exposed surface of the fin structure, wherein the silicon nitride can protect the silicon in the concave part of the fin structure so as to prevent the silicon in the concave part of the fin structure from being oxidized, oxidizing the silicon outside the concave part of the fin structure, filling the silicon oxide to completely wrap the fin structure and fill a groove between the fin structures, and then annealing.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fin morphology improvement method.
Background
As the feature size of the semiconductor device is reduced in the molar law geometric proportion, the chip integration level is continuously improved, a plurality of negative effects appear to cause the traditional planar MOS transistor to develop to 22nm to encounter the bottleneck, especially the Short Channel Effect (SCE) is obviously increased, and the off-state current of the device is sharply increased; the introduction of the FIN-shaped (FIN) structure increases the surface of the gate surrounding the channel from 16/14nm, and enhances the control of the gate on the channel, thereby effectively relieving the short channel effect in the planar device.
During FIN dry etching, the high-energy plasma may damage FIN surface, and the FIN surface roughness is too large and FIN side surfaces are not bent flat, as shown in fig. 1 and 2. In fin field-Effect Transistor (FinFET), the drive current flows along the vertical sidewalls of the fin structure, and thus the surface quality of the sidewalls has a large impact on reliability and electrical performance of the device. Rough sidewalls can lead to reduced carrier mobility and lifetime, reduced current drive, degraded subthreshold swing, increased leakage current and low frequency noise.
Accordingly, there is a need to provide a new fin morphology improvement method to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a fin morphology improvement method which improves the flatness of the vertical side wall of a fin structure.
In order to achieve the above object, the fin morphology improvement method of the present invention includes the steps of:
s1: filling silicon nitride in the concave part of the fin structure;
s2: growing silicon oxide on the exposed surface of the fin structure;
s3: filling silicon oxide to completely wrap the fin structures and fill the grooves between the fin structures, and then performing annealing treatment;
S4: the silicon oxide is etched to expose a portion of the fin structure.
The fin morphology improvement method has the beneficial effects that: filling silicon nitride in the concave part of the fin structure, growing silicon oxide on the exposed surface of the fin structure, wherein the silicon nitride can protect the silicon in the concave part of the fin structure, further, the silicon in the concave part of the fin structure is prevented from being oxidized, the silicon outside the concave part of the fin structure is prevented from being oxidized, the silicon filled with the silicon oxide to completely wrap the fin structure and fill the groove between the fin structures, and then annealing treatment is carried out, at the moment, the silicon nitride in the concave part of the fin structure can protect the silicon in the concave part of the fin structure, the silicon in the concave part of the fin structure is prevented from being oxidized, and part of the protruding part of the side wall of the fin structure is removed, so that the flatness of the vertical side wall of the fin structure is improved.
Optionally, filling the recess of the fin structure with silicon nitride includes:
forming silicon nitride on a surface of the fin structure;
And removing the silicon nitride outside the concave part of the fin structure by adopting an anisotropic dry etching process. The beneficial effects are that: by adopting the anisotropic dry etching process, only the silicon nitride outside the concave part of the fin structure can be removed, and the silicon nitride in the concave part of the fin structure is reserved.
Optionally, the forming silicon nitride on the surface of the fin structure includes: and forming silicon nitride on the surface of the fin structure by adopting an atomic layer deposition process.
Optionally, the growing silicon oxide on the exposed surface of the fin structure includes: silicon oxide is grown on the exposed surfaces of the fin structures using a water vapor oxidation or atomic layer deposition process.
Optionally, the filling silicon oxide to completely encapsulate the fin structures and fill the trenches between the fin structures, and then performing an annealing process, including:
Filling silicon oxide by adopting a fluid chemical vapor deposition process to completely wrap the fin structures and fill the grooves between the fin structures;
and carrying out steam annealing treatment on the silicon oxide.
Optionally, the etching the silicon oxide to expose a portion of the fin structure includes: and etching the silicon oxide by adopting an isotropic etching process so as to expose part of the fin structure.
Optionally, when the top of the fin structure has a hard mask formed of silicon nitride and silicon oxide, the step S3 further includes: the filled silicon oxide completely encapsulates the hard mask.
Optionally, between executing the step S3 and the step S4, further includes: and flattening the silicon oxide on the upper side of the silicon nitride in the hard mask to expose the silicon nitride in the hard mask.
Optionally, after the planarization of the silicon oxide on the upper side of the silicon nitride in the hard mask, the method further includes: and (5) annealing treatment is carried out. The beneficial effects are that: after the annealing treatment, the film quality of the silicon oxide can be improved.
Optionally, between executing the step S3 and the step S4, further includes: and removing the silicon nitride in the hard mask by adopting a wet method.
Drawings
FIG. 1 is a schematic diagram of a fin structure according to the prior art;
fig. 2 is a schematic diagram of yet another fin structure in the prior art;
FIG. 3 is a flow chart of a method of fin morphology improvement in some embodiments of the invention;
FIG. 4 is a schematic diagram of a structure after forming silicon nitride on the surface of the structure shown in FIG. 1 according to some embodiments of the present invention;
Fig. 5 is a schematic diagram of a structure with silicon nitride removed outside the fin structure recess shown in fig. 4 according to some embodiments of the present invention;
Fig. 6 is a schematic diagram of a structure after growing silicon oxide on the exposed surface of the fin structure shown in fig. 5 in accordance with some embodiments of the invention;
FIG. 7 is a schematic diagram of the structure of FIG. 6 after filling the structure with silicon oxide, in accordance with some embodiments of the present invention;
FIG. 8 is a schematic diagram of a structure of the present invention after a steam annealing process is performed on the structure of FIG. 7 in accordance with some embodiments of the present invention;
FIG. 9 is a schematic diagram of a structure after chemical mechanical planarization of the structure shown in FIG. 8, in accordance with some embodiments of the present invention;
FIG. 10 is a schematic diagram of a structure after removing silicon nitride from the hard mask in the structure of FIG. 9 in accordance with some embodiments of the present invention;
FIG. 11 is a schematic diagram of the structure of the etched silicon nitride of FIG. 10 according to some embodiments of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
Aiming at the problems existing in the prior art, the embodiment of the invention provides a fin shape improvement method.
Referring to fig. 3, the fin morphology improvement method includes the steps of:
s1: filling silicon nitride in the concave part of the fin structure;
s2: growing silicon oxide on the exposed surface of the fin structure;
s3: filling silicon oxide to completely wrap the fin structures and fill the grooves between the fin structures, and then performing annealing treatment;
S4: the silicon oxide is etched to expose a portion of the fin structure.
In some embodiments, filling the recess of the fin structure with silicon nitride includes: forming silicon nitride on a surface of the fin structure; and removing the silicon nitride outside the concave part of the fin structure by adopting an anisotropic dry etching process. And forming silicon nitride on the surface of the fin structure through an atomic layer deposition process.
In some embodiments, the forming silicon nitride on the surface of the fin structure includes: and forming silicon nitride on the surface of the fin structure by adopting an atomic layer deposition process.
In some embodiments, the growing silicon oxide on the exposed surface of the fin structure includes: silicon oxide is grown on the exposed surfaces of the fin structures using a water vapor oxidation or atomic layer deposition process.
In some embodiments, the filling silicon oxide to completely encapsulate the fin structures and fill the trenches between the fin structures, and then performing an annealing process, including: filling silicon oxide by adopting a fluid chemical vapor deposition process to completely wrap the fin structures and fill the grooves between the fin structures; and carrying out steam annealing treatment on the silicon oxide.
In some embodiments, the etching the silicon oxide to expose a portion of the fin structure includes: and etching the silicon oxide by adopting an isotropic etching process so as to expose part of the fin structure.
In some embodiments, when the top of the fin structure has a hard mask formed of silicon nitride and silicon oxide, the step S1 further includes: and forming silicon nitride on the surface of the fin structure and the hard mask.
In a fin structure formation precursor process, a hard mask is used to block and etch the substrate to form the fin structure.
Fig. 1 is a schematic diagram of a fin structure in the prior art. Referring to fig. 1, a substrate 101 has two fin structures 102 thereon, two sides of each fin structure 102 have a recess 1021, and an upper side of each fin structure 102 has a hard mask, wherein materials of the hard mask from top to bottom are respectively silicon oxide 103, silicon nitride 104 and silicon oxide 103.
Fig. 2 is a schematic diagram of yet another fin structure in the prior art. Referring to fig. 2, a substrate 101 has two fin structures 102 with curved sidewalls, and each fin structure 102 has a hard mask 103 on its upper side, and the materials of the hard mask from top to bottom are silicon oxide 103, silicon nitride 104, and silicon oxide 103, respectively. Wherein the inward curvature of the fin structure 102 sidewall corresponds to the recess in fig. 1.
Fig. 4 is a schematic diagram of a structure after silicon nitride is formed on the surface of the structure shown in fig. 1 according to some embodiments of the present invention. A layer of silicon nitride 104 is deposited on the fin structure 102 and the surface of the hard mask by an atomic layer deposition process to obtain the structure shown in fig. 4.
Fig. 5 is a schematic diagram of a structure after removing silicon nitride outside the fin structure recess shown in fig. 4 according to some embodiments of the present invention. And removing the silicon nitride 104 except the position of the recess 1021 of the fin structure 102 by dry etching, and reserving the silicon nitride 104 in the position of the recess 1021 of the fin structure 102 to fill the silicon nitride 104 in the position of the recess 1021 of the fin structure 102, so as to obtain the structure shown in fig. 5.
Fig. 6 is a schematic diagram of a structure after growing silicon oxide on the exposed surface of the fin structure shown in fig. 5, in accordance with some embodiments of the invention. The exposed silicon surface of the fin structure 102 is oxidized by a steam oxidation method or an atomic layer deposition process, and then silicon oxide 103 is grown on the exposed surface of the fin structure 102, resulting in the structure shown in fig. 6. Wherein, since the silicon nitride at the fin structure 102 is generated by an atomic deposition process, the generated silicon nitride is not stable, and a portion of the silicon nitride at the recess of the fin structure 102 may be oxidized during the process of generating the silicon oxide 103.
In some embodiments, when the top of the fin structure has a hard mask formed of silicon nitride and silicon oxide, the step S3 further includes: the filled silicon oxide completely encapsulates the hard mask.
FIG. 7 is a schematic diagram of the structure of FIG. 6 after filling the structure with silicon oxide, in accordance with some embodiments of the present invention. Silicon oxide 103 is filled using a fluid chemical vapor deposition process to completely encapsulate fin structures 102, the hard mask, and fill the trenches between fin structures 102, resulting in the structure shown in fig. 7.
Fig. 8 is a schematic diagram of a structure of the present invention after a steam annealing treatment is performed on the structure shown in fig. 7 according to some embodiments of the present invention. After the silicon oxide 103 is subjected to the steam annealing treatment, the silicon nitride 104 in the recess of the fin structure 102 is fully or partially oxidized to silicon oxide, so as to obtain the structure shown in fig. 8, and the silicon nitride 104 in the recess of the fin structure 102 is fully oxidized to silicon oxide.
In some embodiments, when the top of the fin structure has a hard mask formed of silicon nitride and silicon oxide, performing between the step S3 and the step S4 further includes: and carrying out chemical mechanical planarization on the silicon oxide on the upper side of the silicon nitride in the hard mask so as to expose the silicon nitride in the hard mask.
FIG. 9 is a schematic diagram of a structure after chemical mechanical planarization of the structure shown in FIG. 8, in accordance with some embodiments of the present invention. The silicon oxide 103 is subjected to chemical mechanical planarization exposing the silicon nitride 104 in the hard mask to result in the structure shown in fig. 9.
In some embodiments, after performing chemical mechanical planarization on the silicon oxide on the upper side of the silicon nitride in the hard mask, the method further includes: and (5) carrying out annealing treatment to improve the film quality of the silicon oxide.
In some embodiments, between the step S3 and the step S4, further includes: and removing the silicon nitride in the hard mask by adopting a wet method.
FIG. 10 is a schematic diagram of a structure after removing silicon nitride from the hard mask in the structure of FIG. 9, in accordance with some embodiments of the present invention. The silicon nitride 104 in the hard mask is removed by a wet process to obtain the structure shown in fig. 10.
FIG. 11 is a schematic diagram of the structure of the etched silicon nitride of FIG. 10 according to some embodiments of the invention. The silicon oxide 103 is etched using an isotropic etch process to expose a portion of the fin structure 102, resulting in the structure shown in fig. 11. If the silicon nitride in the recess of the fin structure 102 is only partially oxidized to silicon oxide, the silicon nitride in the recess of the fin structure 102 is etched together with the silicon nitride 103 by using an isotropic etching process.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A method for fin morphology improvement, comprising the steps of:
S1: filling silicon nitride in the concave part of the fin structure, and exposing the surface outside the concave part of the fin structure;
s2: growing silicon oxide on the exposed surface of the fin structure;
s3: filling silicon oxide to completely wrap the fin structures and fill the grooves between the fin structures, and then performing annealing treatment;
S4: the silicon oxide is etched to expose a portion of the fin structure.
2. The method of claim 1, wherein filling the recess of the fin structure with silicon nitride comprises:
forming silicon nitride on a surface of the fin structure;
And removing the silicon nitride outside the concave part of the fin structure by adopting an anisotropic dry etching process.
3. The fin morphology improvement method of claim 2, wherein the forming silicon nitride on the surface of the fin structure comprises: and forming silicon nitride on the surface of the fin structure by adopting an atomic layer deposition process.
4. The fin morphology improvement method of claim 1, wherein the growing silicon oxide on the exposed surface of the fin structure comprises: silicon oxide is grown on the exposed surfaces of the fin structures using a water vapor oxidation or atomic layer deposition process.
5. The method of claim 1, wherein the filling silicon oxide to completely encapsulate the fin structures and fill the trenches between the fin structures, and then performing an annealing process comprises:
Filling silicon oxide by adopting a fluid chemical vapor deposition process to completely wrap the fin structures and fill the grooves between the fin structures;
and carrying out steam annealing treatment on the silicon oxide.
6. The fin morphology improvement method of claim 1, wherein the etching the silicon oxide to expose a portion of the fin structure comprises: and etching the silicon oxide by adopting an isotropic etching process so as to expose part of the fin structure.
7. The fin morphology improvement method of claim 1, wherein when the top of the fin structure has a hard mask formed of silicon nitride and silicon oxide, the step S3 further comprises: the filled silicon oxide completely encapsulates the hard mask.
8. The fin morphology improvement method according to claim 7, wherein between performing the step S3 and the step S4, further comprising: and flattening the silicon oxide on the upper side of the silicon nitride in the hard mask to expose the silicon nitride in the hard mask.
9. The fin profile improvement method according to claim 8, wherein after said planarizing the silicon oxide on the upper side of the silicon nitride in the hard mask, further comprising: and (5) annealing treatment is carried out.
10. The fin morphology improvement method according to claim 8 or 9, wherein between performing the step S3 and the step S4, further comprising: and removing the silicon nitride in the hard mask by adopting a wet method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111425170.0A CN113990758B (en) | 2021-11-26 | 2021-11-26 | Fin morphology improvement method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111425170.0A CN113990758B (en) | 2021-11-26 | 2021-11-26 | Fin morphology improvement method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113990758A CN113990758A (en) | 2022-01-28 |
CN113990758B true CN113990758B (en) | 2024-04-16 |
Family
ID=79732191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111425170.0A Active CN113990758B (en) | 2021-11-26 | 2021-11-26 | Fin morphology improvement method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113990758B (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106298545A (en) * | 2016-11-09 | 2017-01-04 | 上海华力微电子有限公司 | The manufacture method of fin field effect pipe |
CN107591399A (en) * | 2016-07-06 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US9935102B1 (en) * | 2016-10-05 | 2018-04-03 | International Business Machines Corporation | Method and structure for improving vertical transistor |
CN111312591A (en) * | 2020-02-25 | 2020-06-19 | 上海华力集成电路制造有限公司 | Method for preventing residue from forming on overlay alignment mark |
CN111316422A (en) * | 2017-10-30 | 2020-06-19 | 国际商业机器公司 | Method for high-K dielectric feature uniformity |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7622354B2 (en) * | 2007-08-31 | 2009-11-24 | Qimonda Ag | Integrated circuit and method of manufacturing an integrated circuit |
CN105428238B (en) * | 2014-09-17 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET and preparation method thereof and electronic device |
US9548249B2 (en) * | 2015-02-27 | 2017-01-17 | Globalfoundries Inc. | Methods of performing fin cut etch processes for FinFET semiconductor devices and the resulting devices |
US9680017B2 (en) * | 2015-09-16 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including Fin FET and manufacturing method thereof |
US10516037B2 (en) * | 2017-06-30 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming shaped source/drain epitaxial layers of a semiconductor device |
US10777658B2 (en) * | 2018-04-17 | 2020-09-15 | International Business Machines Corporation | Method and structure of fabricating I-shaped silicon vertical field-effect transistors |
US10991537B2 (en) * | 2019-05-03 | 2021-04-27 | International Business Machines Corporation | Vertical vacuum channel transistor |
-
2021
- 2021-11-26 CN CN202111425170.0A patent/CN113990758B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107591399A (en) * | 2016-07-06 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US9935102B1 (en) * | 2016-10-05 | 2018-04-03 | International Business Machines Corporation | Method and structure for improving vertical transistor |
CN106298545A (en) * | 2016-11-09 | 2017-01-04 | 上海华力微电子有限公司 | The manufacture method of fin field effect pipe |
CN111316422A (en) * | 2017-10-30 | 2020-06-19 | 国际商业机器公司 | Method for high-K dielectric feature uniformity |
CN111312591A (en) * | 2020-02-25 | 2020-06-19 | 上海华力集成电路制造有限公司 | Method for preventing residue from forming on overlay alignment mark |
Also Published As
Publication number | Publication date |
---|---|
CN113990758A (en) | 2022-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104008994B (en) | Method for manufacturing semiconductor device | |
US20180315857A1 (en) | Device and method to improve fin top corner rounding for finfet | |
CN106571336B (en) | Method for forming fin field effect transistor | |
CN104733315A (en) | Semiconductor structure forming method | |
US20090140374A1 (en) | Semiconductor device with improved control ability of a gate and method for manufacturing the same | |
CN110783193B (en) | Semiconductor structure and forming method thereof | |
CN108305850B (en) | Semiconductor structure and forming method thereof | |
CN111370488A (en) | Semiconductor structure and forming method thereof | |
KR100683490B1 (en) | Method for manufacturing field effect transistor having vertical channel | |
CN104425264A (en) | Method for forming semiconductor structure | |
CN113990758B (en) | Fin morphology improvement method | |
CN106856189B (en) | Shallow trench isolation structure and forming method thereof | |
CN111627977B (en) | Semiconductor structure, forming method thereof and semiconductor device | |
CN108573862B (en) | Semiconductor structure and forming method thereof | |
WO2021228269A1 (en) | Method for preparing embedded word line structure | |
CN107591327B (en) | Method for forming fin field effect transistor | |
CN110867377B (en) | Planarization method of virtual gate | |
CN112397450B (en) | Method for forming semiconductor structure | |
CN112864092B (en) | Method for forming semiconductor structure and transistor | |
CN112670179B (en) | Semiconductor structure and forming method thereof | |
CN108630606B (en) | Semiconductor structure and forming method thereof | |
CN107068764B (en) | Semiconductor device manufacturing method | |
CN112309977A (en) | Semiconductor structure and forming method thereof | |
KR101060713B1 (en) | Manufacturing Method of Semiconductor Device | |
CN112786452B (en) | Semiconductor structure and forming method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: 201800 room jt2216, building 6, 1288 Yecheng Road, Jiading District, Shanghai Applicant after: Shanghai IC equipment Material Industry Innovation Center Co.,Ltd. Applicant after: SHANGHAI IC R & D CENTER Co.,Ltd. Address before: No. 497 Gauss Road, Zhangjiang hi tech park, Pudong New Area, Shanghai, 201210 Applicant before: Shanghai IC equipment Material Industry Innovation Center Co.,Ltd. Applicant before: SHANGHAI IC R & D CENTER Co.,Ltd. |
|
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |