CN107978514A - Transistor and forming method thereof - Google Patents

Transistor and forming method thereof Download PDF

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Publication number
CN107978514A
CN107978514A CN201610919492.3A CN201610919492A CN107978514A CN 107978514 A CN107978514 A CN 107978514A CN 201610919492 A CN201610919492 A CN 201610919492A CN 107978514 A CN107978514 A CN 107978514A
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layer
transistor
pseudo
opening
barrier layer
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CN107978514B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity

Abstract

A kind of transistor and forming method thereof, forming method includes：Being formed includes the substrate of core space and external zones；Form the first pseudo- grid structure and the second pseudo- grid structure respectively on core space and external zones substrate, the first pseudo- grid structure includes the first gate oxide and the first pseudo- gate electrode layer, and the second pseudo- grid structure includes the second gate oxide and the second pseudo- gate electrode layer；The first pseudo- gate electrode layer and the second pseudo- gate electrode layer are removed, the first opening and the second opening are formed in the dielectric layer between pseudo- grid structure on substrate；Form the first barrier layer of the first opening sidewalls of covering, bottom and core space dielectric layer, and the second barrier layer of the second opening sidewalls of covering, bottom and external zones dielectric layer；Form the photoresist figure of full second opening of filling and covering external zones；Remove the first gate oxide and the first barrier layer；Remove photoresist figure；Remove the second barrier layer；Gate structure is formed in the first opening and in the second opening.The forming method can improve the electric property of transistor.

Description

Transistor and forming method thereof
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of transistor and forming method thereof.
Background technology
In semiconductor fabrication, as the development of super large-scale integration, integrated circuit feature size persistently reduce.For The reduction of meeting market's demand size, the channel length of MOSFET element is also corresponding constantly to be shortened.However, with device channel length Shortening, the distance between device source electrode and drain electrode also shortens therewith, therefore grid is deteriorated the control ability of raceway groove therewith, grid The difficulty of voltage pinch off (pinch off) raceway groove is also increasing so that sub-threshold leakage (subthreshold leakage) Phenomenon, i.e., so-called short-channel effect (SCE：Short-channel effects) it is easier to occur.
Therefore, in order to better conform to the reduction of characteristic size, semiconductor technology gradually starts from planar MOSFET transistor To the three-dimensional transistor transient with more high effect, such as fin formula field effect transistor (FinFET).The grid of FinFET are extremely Ultra-thin body (fin) can be controlled from both sides less.It is more stronger to the control ability of raceway groove than grid with planar MOSFET devices, So as to suppress short-channel effect well.
Fin field effect pipe is broadly divided into core (Core) device and input and output (Input and according to function distinguishing Output, I/O) device.Core devices include core MOS device, and input and output device includes input and output MOS device.Usually In the case of, much bigger than core devices operating voltage of input and output device operating voltage.The problems such as to prevent electrical breakdown, work as device When operating voltage is bigger, it is desirable to which device gate dielectric layer thickness is thicker, and therefore, the thickness of input and output device gate dielectric layer is usually big In the thickness of the gate dielectric layer of core devices.
But the electric property of the transistor of prior art formation still has much room for improvement.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of transistor and forming method thereof, improve the electric property of transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：Form substrate, the substrate Including for forming the core space of core devices and external zones for forming input and output device；Formed over the substrate more A puppet grid structure, on core space substrate for the first pseudo- grid structure, on external zones substrate for the second pseudo- grid structure, Wherein, the described first pseudo- grid structure includes the first gate oxide and the first pseudo- gate electrode layer, and the described second pseudo- grid structure includes the Two gate oxides and the second pseudo- gate electrode layer；Formed and be situated between on substrate between the described first pseudo- grid structure and the second pseudo- grid structure Matter layer；The described first pseudo- gate electrode layer and the second pseudo- gate electrode layer are removed, is formed in the dielectric layer and exposes the first gate oxidation First opening of layer and the second opening for exposing the second gate oxide；Form the first opening sidewalls of covering and bottom, the second opening Side wall and bottom and the barrier layer of dielectric layer, are the first barrier layer positioned at core space, are stopped positioned at external zones for second Layer；Form the photoresist figure of full second opening of filling and covering external zones；Using the photoresist figure as mask, described first is removed Gate oxide and the first barrier layer；Remove the photoresist figure；After removing the photoresist figure, the second barrier layer is removed, is exposed Second gate oxide of the second open bottom；Metal layer is formed in the described first opening and the second opening, positioned at the first opening In the metal layer be used for form first grid structure；Second gate oxide and the metal in the second opening Layer is used to form second grid structure.
Optionally, the barrier layer is oxide layer.
Optionally, the barrier layer is silicon oxide layer.
Optionally, the preparation method of the silicon oxide layer is atomic layer deposition.
Optionally, the technological parameter of the atomic layer deposition is：Growth temperature is 80-300 DEG C, and chamber pressure is 5mTorr-20Torr, growth time are 5-100 circulation.
Optionally, the thickness on the barrier layer is
Optionally, described the step of removing the first gate oxide and the first barrier layer, includes：Using SiCoNi etching technics Or diluted hydrofluoric acid solution is removed step.
Optionally, the technological parameter of the SiCoNi etching technics includes：The gas flow of helium for 600sccm extremely 2000sccm, the gas flow of Nitrogen trifluoride are 20sccm to 200sccm, the gas flow of ammonia for 200sccm extremely 500sccm, chamber pressure are 2Torr to 10Torr, and the process time is 20s to 400s.
Optionally, the volumetric concentration percentage of hydrofluoric acid is 0.05%-0.2% in the hydrofluoric acid solution.
Optionally, the step of removal photoresist figure includes：The photoresist figure is removed using cineration technics.
Optionally, the forming method further includes：Before the second barrier layer is removed, formed in first open bottom Sacrifice layer；In the step of removing the second barrier layer, the sacrifice layer of first open bottom is also removed.
Optionally, the sacrifice layer is silicon oxide layer.
Optionally, the thickness of the sacrifice layer is
Optionally, described the step of removing sacrifice layer and the second barrier layer, includes：Carried out using diluted hydrofluoric acid solution Removal step.
Optionally, after first opening and the second opening is formed, be open the first gate oxide exposed to first The second gate oxide exposed with the second opening carries out nitrating processing.
Correspondingly, the present invention, which provides a kind of use, is previously formed the transistor that method is formed.
Correspondingly, the present invention also provides a kind of transistor, including：Substrate, including the core space with core devices and External zones with input and output device；Dielectric layer on the substrate, has in the dielectric layer and runs through the core First opening of area's dielectric layer and the second opening through the external zones dielectric layer；First gate oxide, positioned at described One open bottom；Second gate oxide, positioned at second open bottom；Positioned at first opening sidewalls, the first gate oxidation Barrier layer on layer, on the second opening sidewalls, the second gate oxide and at the top of the dielectric layer, positioned at the core space Barrier layer is the first barrier layer, is the second barrier layer positioned at the barrier layer of external zones.
Optionally, the barrier layer is oxide layer.
Optionally, the barrier layer is silicon oxide layer.
Optionally, the thickness on the barrier layer is
Compared with prior art, technical scheme has the following advantages：
The forming method of transistor provided by the invention, by the first opening sidewalls and bottom and the second open side Barrier layer is formed on wall and bottom, re-forms the photoresist figure of full second opening of filling and covering external zones, is removing photoresist figure Barrier layer is removed again afterwards, photoresist is together removed during remaining in removal barrier layer, so that photoresist figure removes More thoroughly, it is not easy to remain, and then improves the electric property of transistor.
Further, since the second gate oxide can be as a part for second grid structure, the stop in subsequent technique The formation of layer can reduce by the second gate oxide and react with photoresist figure, photoresist residual be reduced, so as to improve second grid The quality of structure, and then the electric property of transistor is improved, improve the yield of device.
The present invention provides a kind of transistor formed using above-mentioned forming method, on second gate oxide of transistor Photoresist residual it is less, therefore the electric property of the transistor can be improved.
The present invention also provides a kind of transistor, the transistor is included positioned at first opening sidewalls, the first gate oxidation Barrier layer on layer, on the second opening sidewalls, the second gate oxide and at the top of the dielectric layer, in semiconductor fabrication process During, if forming photoresist figure on the barrier layer, the photoresist on the barrier layer remains in described except barrier layer During be together removed, so as to which photoresist residual is reduced or avoided, and then improve the electric property of transistor.
Brief description of the drawings
Fig. 1 to Fig. 6 is a kind of corresponding structure diagram of each step of the forming method of transistor；
Fig. 7 to Figure 17 be transistor of the present invention one embodiment of forming method in each step counter structure schematic diagram.
Embodiment
From background technology, the transistor electricity performance that the prior art is formed still has much room for improvement.With reference to the prior art Forming method, it is bad to transistor electricity performance the reason for analyze.Referring to figs. 1 to Fig. 6, a kind of shape of transistor is shown Into the corresponding structure diagram of each step of method.The forming method of the transistor comprises the following steps：
With reference to figure 1, substrate 100 is formed, the substrate 100 includes core space I and external zones II.I substrate of core space There is the first fin 110 on 100, there is the second fin 120 on II substrate 100 of external zones.
With reference to figure 2, Fig. 2 is along the cross-sectional view of 120 extending direction of the first fin 110 and the second fin, in institute State the first pseudo- grid knot that the first fin 110 is developed across on substrate 100 and covers 110 atop part of the first fin and sidewall surfaces Structure (not indicating), the second pseudo- grid structure across the second fin 120 and covering 120 atop part of the second fin and sidewall surfaces (not indicating).Wherein, the described first pseudo- grid structure includes 111 He of the first gate oxide positioned at 110 surface of the first fin The first pseudo- gate electrode layer 112 on first gate oxide 111, the described second pseudo- grid structure include being located at described second Second gate oxide 121 on 120 surface of fin and the second pseudo- gate electrode layer 122 on second gate oxide 121.
With continued reference to Fig. 2, the first source and drain doping area is formed in the first fin 110 of the described first pseudo- grid structure both sides 113, form the second source and drain doping area 123 in the second fin 120 of the described second pseudo- grid structure both sides.On the substrate 100 Also form the pseudo- grid structure of covering described first, the second pseudo- grid structure, the first source and drain doping area 113 and the second source and drain doping area 123 Dielectric layer 130.
With reference to figure 3, etching removes the described first pseudo- gate electrode layer 112 (as shown in Figure 2) and the second pseudo- gate electrode layer 122 (as shown in Figure 2), forms the first opening 200 for exposing the first gate oxide 111 in the dielectric layer 130 and exposes second gate Second opening 210 of oxide layer 121；The first gate oxide 111 exposed to the described first opening 200 and second opening 210 the second gate oxides 121 exposed carry out plasma nitridation process.
With reference to figure 4, the photoresist figure 300 for covering the external zones II is formed, is mask with the photoresist figure 300, carved Etching off is except the first gate oxide 111 (as shown in Figure 3) of the described first 200 bottoms of opening；Remove the photoresist figure 300.
With reference to figure 5, boundary layer 115 is formed in the described first 200 bottoms of opening；On the boundary of the described first 200 bottoms of opening On surface layer 115, first opening 200 side walls and second opening 210 bottoms the second gate oxide 121 on, second opening 210 side walls Upper formation gate dielectric layer 140.
With reference to figure 6, filling is full in the described first 200 (as shown in Figure 5) of opening and the second 210 (as shown in Figure 5) of opening Metal forms metal layer 150, and boundary layer 115, gate dielectric layer 140 and the metal layer 150 of the core space I form first grid knot Structure 116, the second gate oxide 121, gate dielectric layer 140 and the metal layer 150 of the external zones II form second grid structure 126。
In the forming method of prior art transistor, plasma nitridation process is carried out to the second gate oxide 121, is improved The reliability performance of transistor and time correlation dielectric breakdown, still, when the nitrogen content of the second gate oxide 121 is higher When (such as more than 15%), the amino in the second gate oxide 121 easily reacts with photoresist figure 300, therefore, is removing During photoresist figure 300, the photoresist figure 300 to react with amino is difficult to be removed, so that cause photoresist to remain, into And influence the electric property of transistor.
In addition, the amino in the second gate oxide 121 reacts with photoresist figure 300, photoresist residual is readily retained in the The surface of two gate oxides 121,140 performance of gate dielectric layer being formed on the second gate oxide 121 will be affected, so that shadow Ring the electric property of transistor.
In order to solve the above technical problem, the present invention provides a kind of forming method of transistor, including：Form substrate, institute Stating substrate includes core space and external zones；Multiple pseudo- grid structures are formed on substrate, it is pseudo- for first on core space substrate Grid structure, on external zones substrate for the second pseudo- grid structure, wherein, the described first pseudo- grid structure includes the first gate oxide With the first pseudo- gate electrode layer, the described second pseudo- grid structure includes the second gate oxide and the second pseudo- gate electrode layer；Described first Dielectric layer is formed on substrate between pseudo- grid structure and the second pseudo- grid structure；Remove the described first pseudo- gate electrode layer and the second pseudo- grid Electrode layer, forms the first opening for exposing the first gate oxide in the dielectric layer and exposes the second of the second gate oxide and open Mouthful；The first opening sidewalls of covering and bottom, the second opening sidewalls and bottom and the barrier layer of dielectric layer are formed, positioned at core space For the first barrier layer, be the second barrier layer positioned at external zones；Form the photoresist of full second opening of filling and covering external zones Figure；Using the photoresist figure as mask, first gate oxide and the first barrier layer are removed；Remove the photoresist figure； After removing the photoresist figure, the second barrier layer is removed, exposes the second gate oxide of the second open bottom；Opened described first Metal layer is formed in mouth and the second opening, the metal layer in the first opening is used to form first grid structure；It is located at Second gate oxide and the metal layer in second opening are used to form second grid structure.
In the present invention, by forming barrier layer on the second opening sidewalls and bottom and dielectric layer, it is full to re-form filling The photoresist figure of second opening and covering external zones, again removes barrier layer after photoresist figure is removed, photoresist remains in Together it is removed during except barrier layer, so that the removal of photoresist figure is more thorough, is not easy to remain, and then improves crystal The electric property of pipe.
Further, since the second gate oxide can be as a part for second grid structure, the stop in subsequent technique The formation of layer can reduce by the second gate oxide and react with photoresist figure, so that the quality of second grid structure is improved, into And improve the electric property of transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
Fig. 7 to Figure 17 be transistor of the present invention one embodiment of forming method in each step counter structure schematic diagram.This reality Example is applied by taking fin formula field effect transistor as an example.But it should be recognized that the forming method of the present invention can be also used for other partly leading Body device.
With reference to reference to figure 7 and Fig. 8, the stereogram of transistor and cuing open along AA1 (as shown in Figure 7) directions are respectively illustrated Face structure diagram, formed substrate 400, the substrate 400 include be used for formed core devices core space I (with reference to figure 8) and For forming the external zones II of input and output device (with reference to figure 8).
In the present embodiment, there is the first fin 410 on I substrate 400 of core space, on II substrate 400 of external zones With the second fin 420.
The material of the substrate 400 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate 400 can also It is enough the germanium substrate on the silicon substrate or insulator on insulator；The material of first fin, 410 and second fin 420 is Silicon, germanium, SiGe, carborundum, GaAs or gallium indium.In the present embodiment, the substrate 400 is silicon substrate, first fin The material of 410 and second fin 420 of portion is silicon.
Specifically, the step of forming substrate 400 includes：Initial substrate is provided, is formed on the initial substrate hard Mask layer (not shown)；Using the hard mask layer as mask, the initial substrate is etched, forms some discrete protrusions；Institute It is fin to state protrusion, and for the initial substrate after etching as substrate 400, the fin positioned at the core space I is the first fin 410, Fin positioned at the external zones II is the second fin 420.
It should be noted that in the present embodiment, after 410 and second fin 420 of the first fin is formed, also described 400 surface of substrate forms isolation structure 401.
The isolation structure 401 is used between adjacent fin and the electric isolution between core space I and external zones II, described The material of isolation structure 401 can be silica, silicon nitride or silicon oxynitride.In the present embodiment, the material of the isolation structure 401 Expect for silica.
In the present embodiment, the isolation structure 401 is fleet plough groove isolation structure.In other embodiments, the isolation junction Structure can also be local silicon oxidation isolation structure.
With reference to figure 9, Fig. 9 is along the cross-sectional view in BB1 (as shown in Figure 7) direction, is formed on substrate 400 multiple Pseudo- grid structure, on I substrate 400 of core space for the first pseudo- grid structure, it is pseudo- for second on II substrate 400 of external zones Grid structure.
Described first pseudo- grid structure and the second pseudo- grid structure are the first grid structure and second grid structure being subsequently formed Take up space position.
In the present embodiment, the described first pseudo- grid structure is across first fin 410 and covering first fin 410 Point top and sidewall surfaces, including the first gate oxide 411 and the first pseudo- gate electrode layer 412, the described second pseudo- grid structure across Second fin 420 and covering 420 atop part of the second fin and sidewall surfaces, including 421 He of the second gate oxide Second pseudo- gate electrode layer 422.
Specifically, the step of forming described first pseudo- grid structure and the second pseudo- grid structure includes：Form covering described first The pseudo- gate oxidation films of 410 and second fin 420 of fin；Pseudo- gate electrode film is formed on the pseudo- gate oxidation films；To the pseudo- grid Electrode film carries out planarization process；The first graph layer (not shown) is formed in the pseudo- gate electrode film；With first figure Layer is mask, and the graphical pseudo- gate electrode film and pseudo- gate oxidation films, the first gate oxide is formed on first fin 410 411, the first pseudo- gate electrode layer 412 is formed on first gate oxide 411, the described first pseudo- gate electrode layer 412 is across institute State the first fin 410.The second gate oxide 421 is formed on second fin 420, on second gate oxide 421 The second pseudo- gate electrode layer 422 is formed, the described second pseudo- gate electrode layer 422 is across second fin 420, first gate oxidation 411 and first pseudo- gate electrode layer 412 of layer forms the first pseudo- grid structure, the pseudo- gate electrode layer of the second gate oxide 421 and second 422 form the second pseudo- grid structure；Etching removes first graph layer.
The material of the described first pseudo- pseudo- gate electrode layer 422 of gate electrode layer 412 and second can be polysilicon, silica, nitrogen SiClx, silicon oxynitride, carborundum, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In the present embodiment, the described first pseudo- gate electrode The material of 412 and second pseudo- gate electrode layer 422 of layer is polysilicon, 411 and second gate oxide 421 of the first gate oxide Material is silica.
In the present embodiment, the formation process of 411 and second gate oxide 421 of the first gate oxide is that steam in situ is given birth to Into oxidation (ISSG, In-situ Stream Generation) technique.
It should be noted that formed after the described first pseudo- grid structure and the second pseudo- grid structure, the formation of the transistor Method further includes：The first side wall layer 413 is formed in the described first pseudo- grid structure side wall, is formed in the described second pseudo- grid structure side wall Second sidewall layer 423.
The material of the first side wall layer 413 and second sidewall layer 423 can be silica, silicon nitride, carborundum, carbon nitrogen SiClx, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides.In the present embodiment, the first side wall layer 413 and second The material of side wall layer 423 is silicon nitride.
It should be noted that after the first pseudo- grid structure and the second pseudo- grid structure is formed, the forming method further includes： The first source and drain doping area (not indicating) is formed in first fin 410 of the described first pseudo- grid structure both sides, in the described second pseudo- grid The second source and drain doping area (not indicating) is formed in second fin 420 of structure both sides.
Specifically, the step of the first source and drain doping area of the formation includes：First in the described first pseudo- grid structure both sides The first stressor layers 414 are formed in fin 410, forming the first source and drain in the first stressor layers 414 by the way of original position is adulterated mixes Miscellaneous area；The step of the second source and drain doping area of the formation, includes：The shape in the second fin 420 of the described second pseudo- grid structure both sides Into the second stressor layers 424, the second source and drain doping area is formed in the second stressor layers 424 by the way of original position is adulterated.
With reference to figure 10, dielectric layer is formed on the substrate 400 between the first dummy gate structure and the second dummy gate structure 460。
In the present embodiment, the dielectric layer 460 is located on the isolation structure 401 and the first fin of part 410 and portion Divide on the second fin 420, the dielectric layer 460 also covers the first source and drain doping area and the second source and drain doping area, and the medium Layer 460 exposes the first pseudo- pseudo- gate electrode layer 422 of gate electrode layer 412 and second.
In the present embodiment, the dielectric layer 460 is laminated construction, including the first medium layer on the substrate 400 440, and the second dielectric layer 450 on the first medium layer 440.
The first medium layer 440 and the material of the second dielectric layer 450 are insulating materials, are, for example, silica, nitrogen SiClx, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.In the present embodiment, the first medium layer 440 and institute The material for stating second dielectric layer 450 is silica.
With reference to figure 11, the described first pseudo- gate electrode layer 412 (with reference to figure 10) and the second pseudo- (reference of gate electrode layer 422 are removed Figure 10), the first opening 600 for exposing the first gate oxide 411 is formed in the dielectric layer 460 and exposes the second gate oxide 421 the second opening 610.
In the present embodiment, in the processing step with along with, etching removes the described first pseudo- pseudo- grid of gate electrode layer 412 and second Electrode layer 422.Specifically, the described first pseudo- pseudo- grid electricity of gate electrode layer 412 and second is removed using no mask etching technique etching Pole layer 422.
In the present embodiment, the described first pseudo- pseudo- grid electricity of gate electrode layer 412 and second is removed using dry etch process etching Pole layer 422, since the etching technics has higher quarter to the described first pseudo- pseudo- gate electrode layer 422 of gate electrode layer 412 and second Erosion selection ratio, so that while etching removes the first puppet 412 and second pseudo- gate electrode layer 422 of gate electrode layer, ensures institute Dielectric layer 460 is stated from loss.
It should be noted that in the present embodiment, the forming method of the transistor further includes：Forming first opening 600 and second are open after 610, and nitrating processing is carried out to 411 and second gate oxide 421 of the first gate oxide.
The nitrating processing is used to nitrogenize 411 and second gate oxide 421 of the first gate oxide, so as to reduce first The heterointerface state charge of 411 and second gate oxide 421 of gate oxide, improves the first gate oxide 411 and the second gate oxide 421 Surface uniformity, and then improve semiconductor devices with time correlation dielectric breakdown reliability performance.
Specifically, the nitrating treatment process used in the present embodiment is plasma nitridation process.
With reference to figure 12,600 side walls of opening of covering first and bottom, the second 610 side walls of opening and bottom and medium are formed The barrier layer (not indicating) of layer 460.
Wherein, it is the first barrier layer 416 positioned at core space I, is the second barrier layer 426 positioned at external zones II.
Second barrier layer 426 is used for the photoresist residual for reducing external zones II, and second barrier layer 426 can also subtract Few second gate oxide 421 reacts with photoresist figure, photoresist residual is reduced, so as to improve the second grid knot being subsequently formed The quality of structure, and then the electric property of transistor is improved, improve the yield of device.
Correspondingly, the barrier layer use can be formed on the first gate oxide 411 and the second gate oxide 421 and can Formed with the material being removed.The barrier layer can be oxide layer, and in the present embodiment, the barrier layer is silicon oxide layer.Oxygen SiClx layer is easier to be formed and removes, and conventional dry or wet etch can remove silicon oxide layer, thus with existing work Skill has preferably processing compatibility, reduces technology difficulty.
In the present embodiment, silicon oxide layer is prepared using atom layer deposition process.Specifically technological parameter is：Growth temperature For 80-300 DEG C, chamber pressure 5mTorr-20Torr, growth time is 5-100 circulation.Grown and aoxidized using lower temperature Silicon layer, reduce technique realizes difficulty and cost, while influence of the relatively low growth temperature to transistor miscellaneous part is smaller, Thus the electric property of transistor is influenced also smaller.
It should be noted that if barrier layer is excessively thin, barrier layer, which is difficult to play, preferably stops the second gate oxide 421 and light The effect that resistance figure reacts, during photoresist figure is removed, it is difficult to reduce photoresist residual, and then be difficult to improve crystal The electric property of pipe.If barrier layer is blocked up, the follow-up cost and difficulty for removing technique and removing barrier layer can be increased.Therefore, originally In embodiment, the thickness on the barrier layer is
With reference to figure 13, form full second 610 (with reference to the figures 12) of opening of filling and cover the photoresist figure 520 of external zones II.
520 one side of photoresist figure is made during the first gate oxide 411 and the first barrier layer 416 is subsequently removed For mask, on the other hand, the photoresist figure 520 is also used as the protective layer of 610 bottom of the second opening and side wall, after preventing During the first gate oxide 411 of continuous removal and the first barrier layer 416, the bottom and side of the opening of processing damage second 610 are removed Wall, so as to destroy the second grid structure being subsequently formed, and then reduces the electric property of transistor.
Specifically, the step of formation photoresist figure 520 include：Photoresist rotary coating is filled into full second opening 610, And II dielectric layer 460 of external zones is covered, soft drying then is carried out to it, makes solid film.Then, to being coated with photoresist Chip be exposed and develop, form photoresist figure 520.In addition, in order to obtain more preferable lithographic results, reduce photoetching process In reflection, the photoresist figure 520 can also include bottom anti-reflection layer (Bottom Anti-Reflect Coating, BARC)。
Sent out it should be noted that second barrier layer 426 can reduce by the second gate oxide 421 with photoresist figure 520 Raw reaction, reduces photoresist residual, so as to improve the quality for the second grid structure being subsequently formed, and then improves the electricity of transistor Performance, improves the yield of device.
It is mask with the photoresist figure 520 with reference to figure 14, removes the first gate oxide 411 (with reference to figure 13) and first Barrier layer 416 (with reference to figure 13).
Since the core space I is used to form core devices, the external zones II is used to form input and output device, core The operating voltage of device is smaller than the operating voltage of input and output device, the problems such as to prevent electrical breakdown, when the operating voltage of device When bigger, it is desirable to which the thickness of the gate dielectric layer of device is thicker, that is to say, that the thickness of the gate dielectric layer for the core devices being subsequently formed Degree is less than the thickness of input and output device gate dielectric layer.For this reason, in the present embodiment, before gate dielectric layer is formed, institute is removed The first gate oxide 411 (as shown in figure 13) of 600 bottom of the first opening is stated, retains the second of 610 bottoms of the second opening Gate oxide 421, second gate oxide 421 is as the part for being subsequently formed second grid structure.
Specifically, the step of removing the first gate oxide 411 and the first barrier layer 416 includes：Work is etched using SiCoNi Skill or diluted hydrofluoric acid solution are removed step.
In the present embodiment, step is removed using SiCoNi etching technics.The step of SiCoNi etching technics, wraps Include：Using helium as diluent gas, Nitrogen trifluoride and ammonia are as reacting gas to generate etching gas；Gone by etching gas Except the first barrier layer 416 and the first gate oxide 411, accessory substance is formed；Annealing process is carried out, the accessory substance is distilled and is decomposed For gaseous products；The gaseous products are removed by air suction mode.
Specifically, the technological parameter of the SiCoNi etching technics includes：The gas flow of helium for 600sccm extremely 2000sccm, the gas flow of Nitrogen trifluoride are 20sccm to 200sccm, the gas flow of ammonia for 200sccm extremely 500sccm, chamber pressure are 2Torr to 10Torr, and the process time is 20s to 400s.
In other embodiments, the first barrier layer and the first gate oxide can also be removed using hydrofluoric acid solution, Damaged to reach good removal effect, and reduce to remove in technique caused by transistor, the hydrogen of the hydrofluoric acid solution Fluoric acid volumetric concentration percentage is 0.05%-0.2%.
With reference to figure 15, remove the photoresist figure 520 (with reference to figure 14).
In this implementation, the photoresist figure 520 is removed using cineration technics.Specifically, use includes oxygen in cineration technics The plasma gas of base or oxonium ion removes photoresist figure 520.
In other embodiments, the method for wet-cleaning can also be used to remove the photoresist figure.
With reference to figure 16, after removing the photoresist figure 520, the second barrier layer 426 (with reference to figure 15) is removed, exposes second and opens Second gate oxide 421 of 610 bottoms of mouth.
During the second barrier layer 426 of the removal, the photoresist on 426 surface of the second barrier layer can be remained and second Barrier layer 426 together removes, so as to reduce photoresist residual, and then improves the performance of transistor.
In the present embodiment, the forming method of the transistor further includes：Before the second barrier layer 426 is removed, described Sacrifice layer (not shown) is formed on the first 600 bottoms of opening；In the step of removing the second barrier layer 426, also remove described first and open The sacrifice layer of 600 bottoms of mouth.
During the second barrier layer 426 is removed, the sacrifice layer can reduce 600 base substrate 400 of the first opening Damage, so as to improve the quality for the first grid structure being subsequently formed, and then improve the electric property of transistor, and removing , can be by the sacrifice layer of the first 600 bottoms of opening and the second resistance positioned at the second open bottom during second barrier layer 426 Barrier 426 together removes, and can't increase the complexity for removing technique, and existing removal technique has compatibility well.
Further, since can be in the first opening 600 during the first gate oxide 411 and the first barrier layer 416 is removed Defect is produced in base substrate 400, therefore, defect can also be aoxidized by forming sacrifice layer in the described first 600 bottoms of opening, after During continuous removal sacrifice layer, defect and sacrifice layer can together be removed, so as to improve 600 base substrate of the first opening 400 uniformity and integrality, improves the quality for being subsequently formed first grid structure, and then improves the electrical property of transistor Energy.
In the present embodiment, the sacrifice layer formed in the first 600 bottoms of opening is silicon oxide layer.Specifically, the shape Include into the step of sacrifice layer：Using including H2O2Solution first opening 600 bottoms formed silicon oxide layer.
If sacrificial layer thickness is blocked up, the substrate 400 of 600 bottom of the first opening can be consumed excessively, and increase and subsequently go Except the cost and difficulty of sacrifice layer.If sacrifice layer is excessively thin, it is difficult to complete oxidation the defects of the first 600 bottom of opening, so that It is difficult to remove defect completely by subsequently removing the technique of sacrifice layer, and then it is good to be difficult to acquisition raising uniformity, integrality First opening 600 bottoms.Therefore, in the present embodiment, the thickness of the sacrifice layer is
It should be noted that in the present embodiment, the step of removing sacrifice layer and the second barrier layer 426, includes：Using dilution Hydrofluoric acid solution be removed step.
Damaged to reach good removal effect, and reduce to remove in technique caused by transistor, in the present embodiment, The hydrofluoric acid volume percentage of the hydrofluoric acid solution is 0.05%-0.2%.
With reference to figure 17, metal is formed in the described first 600 (with reference to figures 16) of opening and the second 610 (with reference to figures 16) of opening Layer 404.
The material of the metal layer 404 can be copper, tungsten, aluminium or silver, and in the present embodiment, the metal layer 404 is tungsten.
It should be noted that described before 610 interior formation metal layer 404 of the first opening 600 and the second opening, the crystalline substance The forming method of body pipe further includes：Boundary layer 418 (Interlayer, IL) is formed in the first 600 bottoms of opening；In the first opening Gate dielectric layer 403 is formed on second gate oxide 421 of 610 bottoms of the opening of boundary layer 418 and second of 600 bottoms.
The boundary layer 418 being located in the first opening 600, gate dielectric layer 403 and metal layer 404 form first grid knot Structure 700, second gate oxide 421 being located in the second opening, gate dielectric layer 403 and metal layer 404 form second grid Structure 701.
In the present embodiment, the material of the boundary layer 418 is silica, is formed by thermal oxidation technology.Due to the boundary Surface layer 418 is subsequently used for forming first grid structure 700, and therefore, the thickness of the boundary layer 418 is less than the second grid knot The thickness of second gate oxide 421 of structure.
The gate dielectric layer 403 includes the high-K dielectric layer formed by high K dielectric material (dielectric coefficient is more than 3.9).It is described High K dielectric material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide Titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.In the present embodiment, the material of the gate dielectric layer 403 is titanium oxide.
In the present embodiment, by being open 610 (such as in the first 600 (as shown in figure 12) side walls of opening and bottom and second Shown in Figure 12) barrier layer (not indicating) is formed on side wall and bottom, re-form full second opening 610 of filling and covering external zones II Photoresist figure 520 (as shown in figure 13), again removes barrier layer after photoresist figure 520 is removed, and photoresist remains in removal resistance Together be removed during barrier so that photoresist figure 520 remove more thoroughly, be not easy to remain, and then improve crystal The electric property of pipe；Further, since the second gate oxide 421 can be used as 701 (such as Figure 17 of second grid structure in subsequent technique It is shown) a part, the formation on the barrier layer can reduce by the second gate oxide 421 and react with photoresist figure 520, subtract Few photoresist residual, so as to improve the quality of second grid structure 701, and then improves the electric property of transistor, improves device Yield.
With continued reference to Figure 17, the structure diagram of one embodiment of transistor of the present invention is shown.Correspondingly, the present invention provides A kind of transistor formed using forming method described in previous embodiment.
Since the photoresist on second gate oxide of transistor 421 remains less, the electrical property of the transistor It is able to can be improved.
With reference to the structure diagram for reference to figure 12, showing one embodiment of transistor of the present invention.Correspondingly, the present invention also carries For a kind of transistor, including：
Substrate 400, including the core space I with core devices and the external zones II with input and output device；
Dielectric layer 460 on the substrate 400, has in the dielectric layer 460 and runs through I dielectric layer of core space 460 the first opening 600 and the second opening 610 through II dielectric layer 460 of external zones；
First gate oxide 411, positioned at the described first 600 bottoms of opening；
Second gate oxide 421, positioned at the described second 610 bottoms of opening；
Positioned at the described first 600 side walls of opening, on the first gate oxide 411, the second 610 side walls of opening, the second gate oxidation The barrier layer (not indicating) on the layer 421 and top of the dielectric layer 460, is the first resistance positioned at the barrier layer of the core space I Barrier 416, is the second barrier layer 426 positioned at the barrier layer of external zones II.
In the present embodiment, the transistor is fin field effect pipe, therefore has fin on the substrate 400.Specifically, There is the first fin 410 on I substrate 400 of core space, there is the second fin 420 on II substrate 400 of external zones.
The material of the substrate 400 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate 400 can also It is enough the germanium substrate on the silicon substrate or insulator on insulator；The material of first fin, 410 and second fin 420 is Silicon, germanium, SiGe, carborundum, GaAs or gallium indium.In the present embodiment, the substrate 400 is silicon substrate, first fin The material of 410 and second fin 420 of portion is silicon.
It should be noted that in the present embodiment, the transistor further includes：The substrate 400 between the adjacent fin On isolation structure 401.
The isolation structure 401 is used for playing electric isolution between adjacent fin and between core space I and external zones II Effect, the material of the isolation structure 401 can be silica, silicon nitride or silicon oxynitride.In the present embodiment, the isolation junction The material of structure 401 is silica.
In the present embodiment, the isolation structure 401 is fleet plough groove isolation structure.In other embodiments, the isolation junction Structure can also be local silicon oxidation isolation structure.
In the present embodiment, the dielectric layer 460 is located on the isolation structure 401 and the first fin of part 410 and portion Divide on the second fin 420.
In the present embodiment, the dielectric layer 460 is laminated construction, including the first medium layer on the substrate 400 440, and the second dielectric layer 450 on the first medium layer 440.
The first medium layer 440 and the material of the second dielectric layer 450 are insulating materials, are, for example, silica, nitrogen SiClx, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.In the present embodiment, the first medium layer 440 and institute The material for stating second dielectric layer 450 is silica.
In the present embodiment, the material of 411 and second gate oxide 42 of the first gate oxide is silica.Wherein, institute State a part for the gate structure that the second gate oxide 421 is used for as II transistor of external zones.
In semiconductor fabrication, if forming photoresist figure in the external zones II, the external zones II easily has light Photoresist residual can also be removed while hindering residual, and remove the barrier layer, therefore second barrier layer 426 is used to reduce The photoresist residual of external zones II；Second barrier layer 426 can also reduce second gate oxide 421 and be sent out with photoresist figure Raw reaction, reduces photoresist residual, so as to improve the quality of II gate structure of external zones, and then improves the electrical property of transistor Energy, improves the yield of device.
The material on the barrier layer is arranged to：It is easily formed in 411 and second gate oxide 421 of the first gate oxide Go up and be easy to the material being removed.The barrier layer can be oxide layer, and in the present embodiment, the barrier layer is silicon oxide layer. Silicon oxide layer is relatively easy to form and removes, and conventional dry or wet etch can remove silicon oxide layer, thus with existing work Skill has preferably processing compatibility, reduces technology difficulty.
It should be noted that the thickness on the barrier layer is unsuitable too small, also should not be too large.If the thickness mistake on barrier layer Small, the barrier layer is difficult to preferably play the role of stopping that the second gate oxide 421 reacts with photoresist figure, is removing During photoresist figure, it is difficult to reduce photoresist residual, and then cause to be difficult to the electric property for improving transistor；If barrier layer Thickness it is excessive, then easily increase removes the cost and technology difficulty on the barrier layer.Therefore, in the present embodiment, the stop Layer thickness be
A kind of transistor is present embodiments provided, the transistor is included positioned at the described first 600 side walls of opening, the first grid Barrier layer in oxide layer 411, on the second 610 side walls of opening, the second gate oxide 421 and at the top of the dielectric layer 460 (not indicating), during semiconductor fabrication process, if forming photoresist figure on the barrier layer, the light on the barrier layer Hinder and be together removed during barrier layer is removed described in remaining in, so as to which photoresist residual is reduced or avoided, and then improved The electric property of transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the scope of restriction.

Claims (20)

  1. A kind of 1. forming method of transistor, it is characterised in that including：
    Substrate is formed, the substrate includes being used for the core space for forming core devices and the periphery for forming input and output device Area；
    Form multiple pseudo- grid structures over the substrate, on core space substrate for the first pseudo- grid structure, positioned at external zones On substrate for the second pseudo- grid structure, wherein, the described first pseudo- grid structure includes the first gate oxide and the first pseudo- gate electrode layer, Described second pseudo- grid structure includes the second gate oxide and the second pseudo- gate electrode layer；
    Dielectric layer is formed on substrate between the described first pseudo- grid structure and the second pseudo- grid structure；
    The described first pseudo- gate electrode layer and the second pseudo- gate electrode layer are removed, is formed in the dielectric layer and exposes the first gate oxide First opening and expose the second gate oxide second opening；
    The first opening sidewalls of covering and bottom, the second opening sidewalls and bottom and the barrier layer of dielectric layer are formed, positioned at core Area for the first barrier layer, be the second barrier layer positioned at external zones；
    Form the photoresist figure of full second opening of filling and covering external zones；
    Using the photoresist figure as mask, first gate oxide and the first barrier layer are removed；
    Remove the photoresist figure；
    After removing the photoresist figure, the second barrier layer is removed, exposes the second gate oxide of the second open bottom；
    Metal layer is formed in the described first opening and the second opening, the metal layer in the first opening is used to form the One gate structure；Second gate oxide and the metal layer in the second opening are used to form second grid structure.
  2. 2. the forming method of transistor as claimed in claim 1, it is characterised in that the barrier layer is oxide layer.
  3. 3. the forming method of transistor as claimed in claim 1, it is characterised in that the barrier layer is silicon oxide layer.
  4. 4. the forming method of transistor as claimed in claim 3, it is characterised in that the preparation method of the silicon oxide layer is original Sublayer deposits.
  5. 5. the forming method of transistor as claimed in claim 4, it is characterised in that the technological parameter of the atomic layer deposition For：Growth temperature is 80-300 DEG C, chamber pressure 5mTorr-20Torr, and growth time is 5-100 circulation.
  6. 6. the forming method of transistor as claimed in claim 1, it is characterised in that the thickness on the barrier layer is
  7. 7. the forming method of transistor as claimed in claim 1, it is characterised in that removal first gate oxide and first The step of barrier layer, includes：Step is removed using SiCoNi etching technics or diluted hydrofluoric acid solution.
  8. 8. the forming method of transistor as claimed in claim 7, it is characterised in that the technique ginseng of the SiCoNi etching technics Number includes：The gas flow of helium is 600sccm to 2000sccm, and the gas flow of Nitrogen trifluoride is 20sccm to 200sccm, The gas flow of ammonia is 200sccm to 500sccm, and chamber pressure is 2Torr to 10Torr, and the process time is 20s to 400s.
  9. 9. the forming method of transistor as claimed in claim 7, it is characterised in that the body of hydrofluoric acid in the hydrofluoric acid solution Product percentage is 0.05%-0.2%.
  10. 10. the forming method of transistor as claimed in claim 1, it is characterised in that described the step of removing photoresist figure wraps Include：The photoresist figure is removed using cineration technics.
  11. 11. the forming method of transistor as claimed in claim 1, it is characterised in that the forming method further includes：Removing Before second barrier layer, sacrifice layer is formed in first open bottom；
    In the step of removing the second barrier layer, the sacrifice layer of first open bottom is also removed.
  12. 12. the forming method of transistor as claimed in claim 11, it is characterised in that the sacrifice layer is silicon oxide layer.
  13. 13. the forming method of transistor as claimed in claim 11, it is characterised in that the thickness of the sacrifice layer is
  14. 14. the forming method of transistor as claimed in claim 11, it is characterised in that the removal sacrifice layer and second stops The step of layer, includes：Step is removed using diluted hydrofluoric acid solution.
  15. 15. the forming method of transistor as claimed in claim 1, it is characterised in that forming first opening and second After opening, the first gate oxide and second that expose to the first opening are open at the second gate oxide progress nitrating exposed Reason.
  16. A kind of 16. transistor formed such as any one of claim 1 to 15 forming method.
  17. A kind of 17. transistor, it is characterised in that including：
    Substrate, including the core space with core devices and the external zones with input and output device；
    Dielectric layer on the substrate, have in the dielectric layer the first opening through the core space dielectric layer, with And the second opening through the external zones dielectric layer；
    First gate oxide, positioned at first open bottom；
    Second gate oxide, positioned at second open bottom；
    Positioned at first opening sidewalls, on the first gate oxide, it is on the second opening sidewalls, the second gate oxide and described Barrier layer at the top of dielectric layer, is the first barrier layer positioned at the barrier layer of the core space, is the positioned at the barrier layer of external zones Two barrier layers.
  18. 18. transistor as claimed in claim 17, it is characterised in that the barrier layer is oxide layer.
  19. 19. transistor as claimed in claim 17, it is characterised in that the barrier layer is silicon oxide layer.
  20. 20. transistor as claimed in claim 17, it is characterised in that the thickness on the barrier layer is
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