CN107887273A - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN107887273A CN107887273A CN201610877710.1A CN201610877710A CN107887273A CN 107887273 A CN107887273 A CN 107887273A CN 201610877710 A CN201610877710 A CN 201610877710A CN 107887273 A CN107887273 A CN 107887273A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of forming method of fin formula field effect transistor, including：Semiconductor substrate is provided, threshold voltage ion implanting is carried out into the Semiconductor substrate, to form threshold voltage injection region；The Semiconductor substrate is performed etching to form the fin of protrusion, the fin includes at least a portion threshold voltage injection region in the depth direction；Amorphous silicon layer is formed in the sidewall surfaces of the fin；Separation layer is formed using fluid chemistry gas-phase deposition and the first annealing process on the semiconductor substrate, the separation layer covers the fin.The present invention program in subsequent annealing process processing, can protect the silicon of the sidewall surfaces of the fin, threshold voltage Doped ions effectively be prevented from fin divergence loss, so as to lift the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of fin formula field effect transistor.
Background technology
In order to preferably adapt to the scaled requirement of device size, semiconductor technology gradually starts from planar MOSFET
Transistor transient from transistor to the three-dimensional with more high effect, such as fin formula field effect transistor (Fin Field
Effect Transistor, FinFET).
FinFET generally includes to protrude from the fin of semiconductor substrate surface, the top of fin described in covering part and side wall
Grid structure, the source region in the fin of the grid structure both sides and drain region.Threshold value is carried out in the fin to FinFET
When voltage ion injects, because fin has the characteristics of spacing is narrow, size is small, adjacent fin can play barrier effect, close
In the fin lower zone of Semiconductor substrate, the region for being difficult to be arrived by ion beam irradiation, referred to as threshold voltage ion implanting are formed
Shadow effect (shadow effect).Shadow effect can cause fin threshold voltage ion doping consistent degree bad, lack fin
Longitudinal diffusion uniformity inside portion.
To solve the problems, such as above-mentioned shadow effect, the scheme that threshold voltage ion implanting is carried out before fin is formed is carried
Go out.Specifically, the program carries out threshold voltage ion implantation doping after the completion of well region doping, so that when forming fin,
The doping fin for having completed threshold voltage ion implanting is directly obtained, effectively prevent the threshold value because caused by stopping adjacent fin
The shadow effect of voltage ion injection.
But subsequently using fluid chemistry gas-phase deposition (Flowable Chemical Vapor
Deposition, FCVD) formed separation layer after, exist fin Doped ions loss be lost in the problem of.
The content of the invention
Present invention solves the technical problem that being to provide a kind of forming method of fin formula field effect transistor, can subsequently move back
In ignition technique processing, the silicon of the sidewall surfaces of the fin is protected, effectively prevents threshold voltage Doped ions from being spread from fin
Loss, so as to lift the performance of fin formula field effect transistor.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of forming method of fin formula field effect transistor, bag
Include：Semiconductor substrate is provided, threshold voltage ion implanting is carried out into the Semiconductor substrate, to form threshold voltage injection
Area；The Semiconductor substrate is performed etching to form the fin of protrusion, the fin exists including the threshold voltage injection region
At least a portion on depth direction；Amorphous silicon layer is formed in the sidewall surfaces of the fin；It is vapor-deposited using fluid chemistry
Technique and the first annealing process form separation layer on the semiconductor substrate, and the separation layer covers the fin.
Optionally, the Semiconductor substrate is performed etching is included with forming the fin of protrusion：In the Semiconductor substrate
Surface forms patterned hard mask layer；Using the hard mask layer as Semiconductor substrate described in mask etching to form the fin of protrusion
Portion, and retain the hard mask layer positioned at the fin top surface.
Optionally, include in the sidewall surfaces formation amorphous silicon layer of the fin：The sidewall surfaces of the fin are carried out
Ion implanting, to form amorphous silicon layer.
Optionally, the Doped ions of the sidewall surfaces progress ion implanting processing to the fin are：Carbon ion or germanium from
Son.
Optionally, the sidewall surfaces to the fin carry out the implantation temperature of ion implanting for -140 degrees Celsius to -
20 degrees Celsius.
Optionally, it is to the technological parameter of the sidewall surfaces progress ion implanting of the fin：Implantation Energy be 5KeV extremely
15KeV；Implantation dosage is 1E13 atom/cm2To 1E15 atom/cm2；Implant angle is 7 degree to 20 degree.
Optionally, the thickness of the amorphous silicon layer is 1 nanometer to 3 nanometers.
Optionally, the technological parameter of the fluid chemistry gas-phase deposition is：Depositing temperature is 30 DEG C to 90 DEG C；Reaction
Pressure is 0.01Torr to 10Torr；Sedimentation time is 10 minutes to 300 minutes.
Optionally, first annealing process includes：Furnace anneal.
Optionally, the technological parameter of first annealing process is：Annealing temperature is 350 DEG C to 800 DEG C；Annealing time is
20 minutes to 200 minutes.
Optionally, it is described to use fluid chemistry gas-phase deposition and the first annealing process shape on the semiconductor substrate
Into after separation layer, in addition to：Second annealing process processing is carried out to the separation layer.
Optionally, second annealing process includes：Furnace anneal, rapid thermal annealing, spike annealing or laser annealing.
Optionally, it is to the technological parameter of the separation layer the second annealing process processing of progress：Annealing temperature is 900 Celsius
Degree is to 1100 degrees Celsius；The gas that annealing uses includes N2；Annealing time is 20 minutes to 120 minutes.
Optionally, the Semiconductor substrate includes first area arranged side by side and second area, and the first area is partly led
It is interior formed with the second well region formed with the first well region, the Semiconductor substrate of the second area in body substrate.
Optionally, first well region is different from the type of second well region, wherein, the first area is nmos area
Domain, when carrying out threshold voltage ion implanting, the Doped ions for injecting the first area are N-type ion；The second area
For PMOS area, when carrying out threshold voltage ion implanting, the Doped ions for injecting the second area are p-type ion.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
In the forming method of the fin formula field effect transistor of the embodiment of the present invention, by providing Semiconductor substrate, to institute
State and threshold voltage ion implanting is carried out in Semiconductor substrate, to form threshold voltage injection region；The Semiconductor substrate is carried out
For etching to form the fin of protrusion, the fin includes at least a portion threshold voltage injection region in the depth direction；
Amorphous silicon layer is formed in the sidewall surfaces of the fin；Using fluid chemistry gas-phase deposition and the first annealing process described
Separation layer is formed in Semiconductor substrate, the separation layer covers the fin., can be in the isolation using the embodiment of the present invention
Amorphous silicon layer is formed in advance between layer and the sidewall surfaces of the fin, so as in the processing of follow-up first annealing process, protect
The silicon of the sidewall surfaces of the fin effectively prevents threshold voltage Doped ions from fin divergence loss, so as to lift fin field
The performance of effect transistor.
Further, relative in the prior art, threshold voltage ion implantation technology is arranged on separation layer is annealed
After processing, in embodiments of the present invention, first carry out threshold voltage ion implanting the step of.The separation layer is carried out behind
During the processing of second annealing process, because annealing process temperature is high, anneal duration length, threshold voltage can be adulterated
Ion more uniformly diffuses into the fin, strengthens the longitudinal diffusion uniformity inside fin, and then improves fin resistance member
The performance of part and semiconductor devices.
Further, in embodiments of the present invention, during the second annealing process processing is carried out to the separation layer, institute
State amorphous silicon layer the technique that amorphous silicon layer is removed without extra increase, can be contributed to cost-effective with self-regeneration.
Brief description of the drawings
Fig. 1 is a kind of fin formula field effect transistor forming process flow chart in the embodiment of the present invention.
Fig. 2 to Fig. 8 is the cross-sectional view of fin formula field effect transistor forming process provided in an embodiment of the present invention.
Embodiment
In the prior art, to avoid the shadow effect problem of threshold voltage ion implanting, it is necessary to before fin is formed
Threshold voltage ion implanting is carried out, so as to directly obtain the doping fin for having completed threshold voltage ion implanting.
But the first annealing process processing is carried out to the separation layer after subsequent fluid chemical vapor deposition method
When, easily cause Doped ions to be diffused out from fin, and then be lost and be lost in.
It is pointed out that for the separation layer formation process of fin formula field effect transistor, in the existing stage, fluid chemistry
Gas-phase deposition is widely applied.Because when forming separation layer on a semiconductor substrate, between adjacent fin,
Because fin has the characteristics of spacing is narrow, size is small, the separation layer is difficult uniformly to fill, and the separation layer pattern resulted in is not
It is smooth, and be easy to produce space in the isolation layer.And the space in separation layer easily causes the generation of leakage current, so that
Transistor performance reduces.Relative to high density plasma CVD and high-aspect-ratio depositing operation (HARP), fluid
The filler formed in chemical vapor deposition method is to contain silicon precursor in fluid state, due to being easier to obtain in fluid state
Uniform space filling effect, therefore the separation layer being correspondingly formed will more even compact, so as to better meet fin field
The performance requirement of effect transistor.
Further, after being deposited using fluid chemistry gas-phase deposition to separation layer, it is also necessary to use and move back
Ignition technique solidifies separation layer.In deposition process, fluid state is filled into Semiconductor substrate containing silicon precursor and
Between adjacent fin.In the curing process, it is gentle by being passed through oxygen, ozone in reaction chamber using the first annealing process
State water, oxidation processes are carried out to the separation layer of original state, to discharge moisture, solid-state material containing silica is converted into, is formed
Separation layer.
Wherein, during solidifying separation layer using the first annealing process, the separation layer of original state is entered
During row oxidation processes, because the silicon in the doping fin can be also oxidized, easily Doped ions are caused to be diffused out from fin,
The problem of loss of fin Doped ions is lost in be present.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, partly led by providing
Body substrate, threshold voltage ion implanting is carried out into the Semiconductor substrate, to form threshold voltage injection region；Partly led to described
Body substrate is performed etching to form the fin of protrusion, and the fin includes the threshold voltage injection region in the depth direction extremely
A few part；Amorphous silicon layer is formed in the sidewall surfaces of the fin；Annealed using fluid chemistry gas-phase deposition and first
Technique forms separation layer on the semiconductor substrate, and the separation layer covers the fin., can be with using the embodiment of the present invention
Amorphous silicon layer is formed in advance between the sidewall surfaces of the separation layer and the fin, so as at follow-up first annealing process
In reason, protect the silicon of the sidewall surfaces of the fin to avoid being oxidized, effectively prevent threshold voltage Doped ions from expanding from fin
Loss is dissipated, lifts the performance of fin formula field effect transistor.
It is understandable to enable above-mentioned purpose, feature and the beneficial effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Fig. 1 is a kind of fin formula field effect transistor forming process flow chart in the embodiment of the present invention, is comprised the following steps：
Step S101：Semiconductor substrate is provided, threshold voltage ion implanting is carried out into the Semiconductor substrate, to be formed
Threshold voltage injection region.
Step S102：The Semiconductor substrate is performed etching to form the fin of protrusion, the fin includes the threshold
At least a portion of threshold voltage injection region in the depth direction.
Step S103：Amorphous silicon layer is formed in the sidewall surfaces of the fin.
Step S104：Formed on the semiconductor substrate using fluid chemistry gas-phase deposition and the first annealing process
Separation layer, the separation layer cover the fin.
Above-mentioned each step is illustrated with reference to Fig. 2 to Fig. 8.
Reference picture 2, there is provided Semiconductor substrate 100, threshold voltage ion implanting is carried out into the Semiconductor substrate 100,
To form threshold voltage injection region.
In the present embodiment, the Semiconductor substrate 100 is silicon substrate.In other embodiments, the Semiconductor substrate
100 material can also be silicon, germanium, SiGe, carborundum, GaAs or gallium indium, and the Semiconductor substrate 100 can also be
The germanium substrate on silicon substrate or insulator on insulator.
It can be N-type that the Semiconductor substrate 100, which can include first area I and second area II, the first area I,
Metal-oxide semiconductor (MOS) (N-Metal Oxide Semiconductor, NMOS) region or P-type mos
(P-Metal Oxide Semiconductor, PMOS) region, the second area II can be NMOS area or PMOS areas
Domain.
In the present embodiment, using the FinFET of formation as complementary metal oxide semiconductor (Complementary Metal
Oxide Semiconductor, CMOS) exemplified by device, the first area I can be set and be used to be subsequently formed nmos device,
The second area II is used to be subsequently formed PMOS device, and the first area I and second area II are adjacent region.
In other embodiments, the first area I can also be PMOS area, and the corresponding second area II is
NMOS area.Or the first area I and second area II are NMOS area, the FinFET being correspondingly formed is NMOS devices
Part.Or the first area I and second area II are PMOS area, the FinFET being correspondingly formed is PMOS device.
In the present embodiment, carried out respectively in the first area I and the second area II the first ion doping and
Second ion doping, the well region formed in the Semiconductor substrate 100 and threshold voltage injection region.Wherein, the threshold value
Voltage injection region can be located at the surface of the well region.
Further, if the first area I is NMOS area, the well region Doped ions and the threshold voltage are mixed
Heteroion is N-type ion, such as including P, As or Sb.
Specifically, so that the Doped ions of the well region are P as an example, the Implantation Energy of the ion implantation technology is 100KeV
To 200KeV, implantation dosage 5E12atom/cm2To 6E13atom/cm2, implant angle is 0 to 10 degree.
So that the threshold voltage Doped ions are P as an example, the Implantation Energy of the ion implantation technology for 8KeV extremely
20KeV, implantation dosage 1E13atom/cm2To 1E14atom/cm2, implant angle is 0 to 10 degree.
So that the threshold voltage Doped ions are As an example, the Implantation Energy of the ion implantation technology for 15KeV extremely
50KeV, implantation dosage 1E13atom/cm2To 1E14atom/cm2, implant angle is 0 to 10 degree.
If the second area II is PMOS area, the well region Doped ions and the threshold voltage Doped ions are
P-type ion, such as including B, Ga or In.
Specifically, so that the Doped ions of the well region are B as an example, the Implantation Energy of the ion implantation technology is 30KeV
To 80KeV, implantation dosage 5E12atom/cm2To 6E13atom/cm2, implant angle is 0 to 10 degree.
So that the threshold voltage Doped ions are B as an example, the Implantation Energy of the ion implantation technology for 3KeV extremely
10KeV, implantation dosage 1E13atom/cm2To 1E14atom/cm2, implant angle is 0 to 10 degree.
So that the threshold voltage Doped ions are BF2 as an example, the Implantation Energy of the ion implantation technology for 10KeV extremely
30KeV, implantation dosage 1E13atom/cm2To 1E14atom/cm2, implant angle is 0 to 10 degree.
It is pointed out that the present invention is not limited above-mentioned well region and threshold voltage ion implantation technology.Follow-up
In explanation, explanation no longer will be made a distinction to the first area I and second area II.
In another embodiment, can also be in the table of Semiconductor substrate 100 before threshold voltage ion implanting is carried out
Face forms oxygen pad layer (pad oxide, not shown), for reducing the stress of Semiconductor substrate 100 and hard mask layer 111, and
Reduce in threshold voltage ion implantation process to the implant damage of Semiconductor substrate 100.
Wherein, the oxygen pad layer can be obtained by heating the Semiconductor substrate 100, and the present invention is to forming the pad oxygen
The mode of layer is not intended to be limited in any.
Further, after threshold voltage ion implanting, the threshold value electricity of doping can also be made by annealing treating process
Pressure ion diffuses to the Semiconductor substrate 100.
Wherein, the technique made annealing treatment to threshold voltage injection region can use rapid thermal annealing, described to move back
The parameter of fire processing includes：The gas of use includes N2, annealing temperature is 950 degrees Celsius to 1050 degrees Celsius, annealing time 5
Second was to 30 seconds.It is pointed out that the present invention is not limited above-mentioned annealing treating process.
In embodiments of the present invention, after the completion of well region doping, threshold voltage ion implantation doping is carried out, so as to follow-up
When fin 102 is formed in technique, the fin for having completed threshold voltage ion implanting is directly obtained, effectively prevent and forming fin
In the case of carrying out threshold voltage ion implanting afterwards, the shade of threshold voltage ion implanting because caused by stopping adjacent fin
Effect.
Reference picture 3, the Semiconductor substrate 100 is performed etching to form the fin 102 of protrusion, the fin 102 wraps
Include at least a portion of the threshold voltage injection region in the depth direction.
In the present embodiment, the Semiconductor substrate 100 is performed etching to form the processing step of the fin 102 of protrusion
Including：Initial hard mask is formed on the surface of Semiconductor substrate 100；Formed on the surface of the initial hard mask patterned
Photoresist layer, using the patterned photoresist layer as initial hard mask described in mask etching to obtain patterned hard mask layer
111, the photoresist layer is removed, and then with the hard mask layer 111 for Semiconductor substrate 100 described in mask etching, to be formed
The fin 102 of protrusion, the fin 102 include the threshold voltage injection region in the depth direction, or including the threshold value
At least a portion of voltage injection region.
Further, after the fin 102 is formed, reservation is covered firmly positioned at the described of the top surface of fin 102
Film layer 111.When subsequently carrying out flatening process, the top surface of the hard mask layer 111 can be as flatening process
Stop position, also, the hard mask layer 111 can also be protected to the top surface of the fin 102.In the present embodiment
In, the material of the hard mask layer 111 can be silicon nitride.
In the present embodiment, the top dimension of the fin 102 is less than bottom size.In other embodiments, the fin
The side wall in portion 102 can also be perpendicular with substrate surface, i.e., the top dimension of fin 102 is equal to bottom size.
In the present embodiment, there are four fins 102 with the Semiconductor substrate 100 as an example, not limiting actual
The number of fin in technique.In actual process, multiple fins can also be formed as needed.
Reference picture 4, amorphous silicon layer 120 is formed in the sidewall surfaces of the fin 102.
In the present embodiment, by carrying out ion implanting processing to the sidewall surfaces of the fin 102, to form non-crystalline silicon
Layer 120.
The silicon of the sidewall surfaces for acting as protecting the fin 102 of the amorphous silicon layer 120, it is avoided to be oxidized.Can
With understanding, if the thickness of the amorphous silicon layer 120 is very thick, it is described non-subsequently to will have to increase additional technique removal
Crystal silicon layer 120, cause process complexity and cost increase.In the present embodiment, the thickness of the amorphous silicon layer 120 is 1 nanometer
To 3 nanometers.
Compared to deposition spin coating proceeding, ion implantation technology can preferably control the thickness of the amorphous silicon layer 120, and
And obtain more preferable uniformity.
Preferably, by the way of low-temperature-doped, the uniformity more preferably amorphous silicon layer 120 can be obtained.It is described to described
The implantation temperature that the sidewall surfaces of fin 102 carry out ion implanting is -140 degrees Celsius to -20 degrees Celsius.
The sidewall surfaces to the fin 102 carry out ion implanting processing Doped ions can include carbon ion or
Germanium ion.
If the Implantation Energy of the ion implanting is excessive, cause the depth of injection larger, will be not only in the fin
102 sidewall surfaces form amorphous silicon layer 120, can cause the follow-up process complexity for removing amorphous silicon layer 120.If it is described from
Son injection Implantation Energy it is too small, cause injection depth it is too small, amorphous silicon layer 120 can not be formed by also resulting in.In this implementation
In example, Implantation Energy can be set as 5KeV to 15KeV.
If the implantation dosage of the ion implanting is excessive, easily cause the increase of process costs and the size of fin 102
Deviation, specifically, implantation dosage, which crosses conference, makes the sidewall surfaces of fin 102 form blocked up amorphous silicon layer 120, after both causing
It is continuous to remove the process complexity of amorphous silicon layer 120, and doping cost is added due to excessive dopant dose, it can also remove
The thickness of fin 102 in the horizontal direction is thinned after amorphous silicon layer 120, and then increases the technique management and control complexity of fin 102.If
The implantation dosage of the ion implanting is too small, causes in the amorphous silicon layer 120 of formation, the mass percent concentration of Doped ions
Too small, the protective effect for also resulting in the amorphous silicon layer 120 reduces.In the present embodiment, implantation dosage can be set as
1E13atom/cm2To 1E15atom/cm2。
In the case where injection depth is certain, the implant angle is relevant with Implantation Energy.The implant angle refers to
The angle formed between Semiconductor substrate normal direction.Implantation Energy it is bigger, it is necessary to implant angle it is bigger；Otherwise, it is necessary to
Implant angle it is smaller.In the present embodiment, implant angle can be set as 7 degree to 20 degree.
To sum up, the parameter of the ion implantation technology needs to select suitable scope.And corresponding to different gap ions
Atomic mass is different.In the case where identical injects depth, the larger gap ion of atomic mass need the energy that loses compared with
Greatly, therefore larger Implantation Energy is needed.
It is pointed out that when the sidewall surfaces to the fin 102 carry out ion implanting, because fin has spacing
Narrow, the characteristics of size is small, adjacent fin 102 can play barrier effect, the area of Semiconductor substrate 100 between adjacent fin 102
Domain, and in the lower zone of the fin 102 of the Semiconductor substrate 100, form the shadow effect of ion implanting, cause
The amorphous silicon layer 120 is mainly formed at the sidewall surfaces of the fin 102.
Reference picture 5, cushion oxide layer (liner oxide) 112 is formed on the surface of the amorphous silicon layer 120.
Because the fin 102 is by being formed after being etched to Semiconductor substrate 100, generally having the corner angle protruded and table
Mask is defective, and device performance can be influenceed after fin formula field effect transistor is subsequently formed.Therefore, the cushion oxide layer 112
Wedge angle sphering can be played a part of to a certain extent, and the cushion oxide layer 112 can be follow-up progress FCVD processing
Good interfacial state is provided, helps to form the silicon precursor that contains of better quality, and then improve the filling quality of separation layer 114.
Also, the cushion oxide layer 112 can also avoid the material of the separation layer 114 and fin 102 formed in subsequent technique
Material lattice mismatches and causes larger stress.
In the present embodiment, the material of cushion oxide layer 112 can be silica, using chemical vapor deposition or atomic layer
Depositing operation is formed.In other embodiments, the cushion oxide layer 112 can also be formed using thermal oxidation technology.The lining
The material of pad oxide 112 can also be silicon nitride or silicon oxynitride.
Reference picture 6, using fluid chemistry gas-phase deposition and the first annealing process in the Semiconductor substrate 100 shape
Into separation layer 114, the separation layer 114 covers the fin 102.
After being deposited using fluid chemistry gas-phase deposition to separation layer 114, it is also necessary to using annealing process
Solidify separation layer 114.
In deposition process, what deposition formed fluid state contains silicon precursor, is filled into Semiconductor substrate 100, phase
Between adjacent fin 102, and cover fin 102.
Specifically, reactant include oxygen gas plasma, silicon source gas (such as SiH4), carrier gas (such as nitrogen, hydrogen or
Inert gas), reaction temperature is 30 DEG C to 90 DEG C, and reaction pressure be 0.01Torr to 10Torr, sedimentation time for 10 minutes extremely
300 minutes, on a semiconductor substrate 100, between adjacent fin 102 deposition form fluid state contain silicon precursor.The stream
The defects of moving enough preferably being filled between fin 102 containing silicon precursor for property, and not allowing to be also easy to produce space.
After completion of the reaction, the hardness containing silicon precursor also needs to further improve, to form the isolation material of solid-state
Material.
In the curing process, using the first annealing process, by being passed through oxygen, ozone and vaporous water in reaction chamber,
Oxidation processes are carried out to the isolated material of original state, to discharge moisture, solid-state material containing silica is converted into, forms separation layer
114。
Specifically, first annealing process can be steam annealing (steam anneal) or wet method annealing (wet
Anneal), such as furnace anneal (furnace anneal) can be used, annealing temperature is 350 DEG C to 800 DEG C, annealing time
For 20 minutes to 200 minutes.
The first annealing process is being used, during the further oxidation of material containing silica to the solid-state, if described
There is no the amorphous silicon layer 120 between the sidewall surfaces of separation layer 114 and the fin 102, be then doped with threshold voltage ion
Fin 102 in silicon can also be oxidized, easily cause Doped ions to be diffused out from fin 102, so be lost be lost in.
In the present embodiment, the fin sidewall surfaces formed amorphous silicon layer 120 can effectively will described in every
Absciss layer 114 is isolated with the side wall of the fin 102, so as to protect the silicon of the sidewall surfaces of the fin 102, avoids it by oxygen
Change, help to prevent threshold voltage Doped ions from lifting the performance of fin formula field effect transistor from the divergence loss of fin 102.
It is pointed out that the hard mask layer 111 positioned at the top surface of fin 102 can be to fin
The silicon of 102 top surface is protected, and avoids it from being oxidized.
Reference picture 7, it is described to use fluid chemistry gas-phase deposition and the first annealing process in the Semiconductor substrate 100
After upper formation separation layer 114, the second annealing process processing is carried out to the separation layer 114.
Wherein, it is described that being moved back using furnace anneal, fast speed heat for the second annealing process processing is carried out to separation layer 114
Fire, spike annealing or laser annealing.Preferably, in the present embodiment, furnace anneal or rapid thermal annealing can be used, to reach
Technological temperature is high, the purpose of anneal duration length.
Specifically, compared with first annealing process, the annealing process temperature that second annealing process uses is high, moves back
Fiery duration length, can make threshold voltage Doped ions more uniformly diffuse into the fin 102, strengthen in fin 102
The longitudinal diffusion uniformity in portion, fin doped region 121 is formed, and then improve the performance of fin resistive element and semiconductor devices.
In specific implementation, if the annealing temperature is too high, easily make the diffusion rate of Doped ions too fast, increase work
Skill management and control complexity.If annealing time is long, easily makes thickness of the threshold voltage doped region to be formed in depth excessive, enter
And influence the electrical property of fin FET.In the present embodiment, annealing temperature is 900 degrees Celsius to 1100 degrees Celsius,
The annealing time is 20 minutes to 120 minutes, and the gas that the annealing uses includes N2。
Further, in embodiments of the present invention, the process of the second annealing process processing is being carried out to the separation layer 114
In, the amorphous silicon layer 120 can be with self-regeneration, technique that amorphous silicon layer 120 is removed without extra increase, help to save into
This.
Reference picture 8, the separation layer 114 is planarized；Remove the hard mask layer of the top surface of fin 102
111 (reference pictures 7), and the part of the separation layer 114 is removed to expose the top of the fin 102.More specifically,
The top of fin 102 has top surface and sidewall surfaces, after a part for the separation layer 114 is removed, fin 102
Top surface and partial sidewall surface are exposed.
In the present embodiment, the separation layer 114 is planarized using chemical mechanical milling tech, and planarizes the isolation
The stop position of layer 114 is the top surface of the hard mask layer 111.
In the present embodiment, the processing step of the part for removing the separation layer 114 includes：It is etched back to remove institute
State the part of separation layer 114 in a thickness direction；Etching removes the (reference of hard mask layer 111 positioned at the top of fin 102
Fig. 7)；Etching removes the cushion oxide layer 112 for being isolated the side wall of fin 102 that layer 114 exposes.
Wherein, it is described to be etched back to remove a part, the etching of the separation layer 114 in a thickness direction and remove positioned at described
The hard mask layer 111 and etching at the top of fin 102 remove the liner oxidation for being isolated the side wall of fin 102 that layer 114 exposes
The technique that layer 112 uses is selected from：The work that dry etch process, wet-etching technology or dry etching and wet etching are combined
Skill.In the present embodiment, the etch liquids that the wet-etching technology can use is hydrofluoric acid solutions.
Afterwards, the processing step to form fin formula field effect transistor can be continued to complete based on the fin 102.Specifically
Processing step can be well known to a person skilled in the art any appropriate processing step, repeat no more here.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (15)
- A kind of 1. forming method of fin formula field effect transistor, it is characterised in that including：Semiconductor substrate is provided, threshold voltage ion implanting is carried out into the Semiconductor substrate, to form threshold voltage injection Area；The Semiconductor substrate is performed etching to form the fin of protrusion, the fin exists including the threshold voltage injection region At least a portion on depth direction；Amorphous silicon layer is formed in the sidewall surfaces of the fin；Separation layer is formed using fluid chemistry gas-phase deposition and the first annealing process on the semiconductor substrate, it is described every Absciss layer covers the fin.
- 2. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that served as a contrast to the semiconductor Bottom performs etching to be included with forming the fin of protrusion：Patterned hard mask layer is formed in the semiconductor substrate surface；Using the hard mask layer as Semiconductor substrate described in mask etching to form the fin of protrusion, and retain and be located at the fin The hard mask layer of top surface.
- 3. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that in the side of the fin Wall surface, which forms amorphous silicon layer, to be included：Ion implanting is carried out to the sidewall surfaces of the fin, to form amorphous silicon layer.
- 4. the forming method of fin formula field effect transistor according to claim 3, it is characterised in that to the side of the fin Wall surface carry out ion implanting processing Doped ions be：Carbon ion or germanium ion.
- 5. the forming method of fin formula field effect transistor according to claim 3, it is characterised in that described to the fin Sidewall surfaces carry out ion implanting implantation temperature be -140 degrees Celsius to -20 degrees Celsius.
- 6. the forming method of the fin formula field effect transistor according to claim 4 or 5, it is characterised in that to the fin Sidewall surfaces carry out ion implanting technological parameter be：Implantation Energy is 5KeV to 15KeV；Implantation dosage is 1E13atom/cm2To 1E15atom/cm2；Implant angle is 7 degree to 20 degree.
- 7. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that the amorphous silicon layer Thickness is 1 nanometer to 3 nanometers.
- 8. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that the fluid chemistry gas The technological parameter of phase depositing operation is：Depositing temperature is 30 DEG C to 90 DEG C；Reaction pressure is 0.01Torr to 10Torr；Sedimentation time is 10 minutes to 300 minutes.
- 9. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that first lehr attendant Skill includes：Furnace anneal.
- 10. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that first annealing The technological parameter of technique is：Annealing temperature is 350 DEG C to 800 DEG C；Annealing time is 20 minutes to 200 minutes.
- 11. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that described to use fluid Chemical vapor deposition method and the first annealing process are formed after separation layer on the semiconductor substrate, in addition to：Second annealing process processing is carried out to the separation layer.
- 12. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that second annealing Technique includes：Furnace anneal, rapid thermal annealing, spike annealing or laser annealing.
- 13. the forming method of fin formula field effect transistor according to claim 11, it is characterised in that to the separation layer The technological parameter for carrying out the second annealing process processing is：Annealing temperature is 900 degrees Celsius to 1100 degrees Celsius；The gas that annealing uses includes N2；Annealing time is 20 minutes to 120 minutes.
- 14. the forming method of fin formula field effect transistor according to claim 1, it is characterised in that the semiconductor lining Bottom includes first area arranged side by side and second area, and the Semiconductor substrate of the first area is interior formed with the first well region, described Formed with the second well region in the Semiconductor substrate of second area.
- 15. the forming method of fin formula field effect transistor according to claim 14, it is characterised in that first well region It is different from the type of second well region, wherein,The first area is NMOS area, when carrying out threshold voltage ion implanting, inject the doping of the first area from Son is N-type ion；The second area is PMOS area, when carrying out threshold voltage ion implanting, inject the doping of the second area from Son is p-type ion.
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| CN111415907A (en) * | 2020-03-31 | 2020-07-14 | 上海华力集成电路制造有限公司 | Method for manufacturing amorphous silicon structure |
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