CN208433413U - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN208433413U CN208433413U CN201820948488.4U CN201820948488U CN208433413U CN 208433413 U CN208433413 U CN 208433413U CN 201820948488 U CN201820948488 U CN 201820948488U CN 208433413 U CN208433413 U CN 208433413U
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Abstract
The utility model relates to a kind of semiconductor structure, the semiconductor structure includes: substrate；Positioned at the gate structure of the substrate surface, the gate structure includes the grid positioned at the gate dielectric layer of substrate surface and positioned at the gate dielectric layer surface；The grid includes the first doped region and the second doped region, doped with the first Doped ions in first doped region, second doped region is doped with the second Doped ions, second Doped ions are p-type Doped ions, and first Doped ions can be improved segregation coefficient of the p-type Doped ions in the grid.Above-mentioned semiconductor structure can be avoided gate depletion, improve the performance of semiconductor structure.
Description
Technical field
The utility model relates to technical field of semiconductors more particularly to a kind of semiconductor structures.
Background technique
The prior art in the pmos devices, usually carries out P-type ion doping to grid to adjust the grid and lining of transistor
Work function between bottom, to achieve the purpose that adjust PMOS threshold voltage.In order to realize the electrical contact of grid, PMOS device
Top portions of gates will form metal contact layer.The metal contact layer is usually metal silicide.
In the technical process of 3D NAND, due to big heat budget, need using relatively stable WSi2It is connect as grid
Contact layer.The P-type ion of the grid of PMOS device is adulterated, and B ion doping is generallyd use, however, B is in WSi2Middle segregation coefficient is high,
Diffusion rate is fast, and B is caused to pass through WSi2The interface of layer and grid, enters WSi2In layer and in WSi2It is built up in layer, causes grid
It exhausts, to cause the threshold voltage shift of PMOS device, influences the performance of PMOS transistor, to be unable to satisfy high speed great Rong
Measure the demand of circuit.
Gate depletion problem how is avoided, the performance of semiconductor structure is improved, is current urgent problem to be solved.
Utility model content
Technical problem to be solved by the utility model is to provide a kind of semiconductor structures, to improve the semiconductor junction
The performance of structure.
The technical solution of the utility model provides a kind of semiconductor structure, comprising: substrate；Positioned at the grid of the substrate surface
Pole structure, the gate structure include the grid positioned at the gate dielectric layer of substrate surface and positioned at the gate dielectric layer surface；Institute
Stating grid includes the first doped region and the second doped region, and first doped region is interior doped with the first Doped ions, institute
The second doped region is stated doped with the second Doped ions, second Doped ions are p-type Doped ions, described first adulterate from
Son can be improved segregation coefficient of the p-type Doped ions in the grid.
Optionally, first Doped ions include at least one of C and Ge.
Optionally, first Doped ions are distributed at each position of the grid.
Optionally, second Doped ions include B or BF2At least one of.
Optionally, further includes: the source electrode and drain electrode in the substrate of the gate structure two sides.
Optionally, further includes: positioned at the gate contact layer of the gate top surface.
Optionally, the material of the gate contact layer includes at least one of tungsten silicide and nickel silicide.
The semiconductor structure of the utility model, adulterates the first Doped ions in gate material layers, described first adulterate from
Son can be improved segregation coefficient of the p-type Doped ions in gate material layers, so that the gate material layers are carrying out p-type
After Doped ions doping, higher p-type Doped ions concentration is kept, gate depletion problem is avoided, to improve semiconductor structure
Performance.
Detailed description of the invention
Fig. 1 to Fig. 5 is the structural schematic diagram of the forming process of the semiconductor structure of the utility model.
Specific embodiment
The specific embodiment of semiconductor structure provided by the utility model and forming method thereof is done with reference to the accompanying drawing
It is described in detail.
Referring to FIG. 1, providing substrate 100；Gate dielectric material layer 101 is formed on 100 surface of substrate and is located at described
The gate material layers 120 on 110 surface of gate dielectric material layer.
The substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to the reality of device
Demand can choose suitable semiconductor material as substrate 100, be not limited thereto.In the specific embodiment, the lining
Bottom 100 is monocrystalline silicon wafer crystal.It is also formed with dopant well 101 in the substrate 100, in the specific embodiment, the substrate 100
Dopant well 101 be n-type doping trap, it is subsequent to form PMOS transistor on the dopant well 101.
Successively gate dielectric material layer 110 and gate material layers 120, the gate medium material are formed on 100 surface of substrate
The material of the bed of material 110 can be the dielectric materials such as silica, hafnium oxide, zirconium oxide, can use thermal oxide, chemical vapor deposition
Technique or atom layer deposition process form the gate dielectric material layer.The material of the gate material layers 120 can for polysilicon,
The semiconductor materials such as silicon carbide, germanium silicon can form the gate material layers 120 using chemical vapor deposition process.In the tool
In body embodiment, the material of the gate dielectric material layer 110 is silica, is formed using thermal oxidation technology；The grid material
The material of the bed of material 120 is polysilicon, is formed using chemical vapor deposition process.
Referring to FIG. 2, to the gate material layers 120 the first ion doping of progress, the first of first ion doping
Doped ions can be improved segregation coefficient of the p-type Doped ions in the gate material layers 120.
First Doped ions include at least one of C and Ge, for example, first ion doping can be to described
Gate material layers 120 carry out C ion doping or Ge ion doping；First ion doping can also be simultaneously to the grid
Material layer 120 adulterates C ion and Ge ion, or successively doping C ion and Ge ion.
First ion doping can be realized using ion implanting or diffusion technique.
In present embodiment, the C ion implanting that first ion doping is single is adopted.Specifically, use C from
Sub- energy is 5keV~25keV, doping concentration 5E18cm-3~1E20cm-3。
In another specific embodiment, first ion doping injects C ion to the gate material layers 120 simultaneously
With Ge ion, wherein C ion energy is 5keV~25keV, doping concentration 5E18cm-3~1E20cm-3；Ge ion energy is
10keV~20keV, doping concentration 1E18cm-3~1E19cm-3。
First Doped ions can be improved segregation coefficient of the p-type Doped ions in the gate material layers 120, be
The p-type Doped ions are enabled to all have higher segregation coefficient at each position in the gate material layers 120,
So that p-type Doped ions can be uniformly distributed in the gate material layers 120, can be mixed by controlling first ion
Miscellaneous technological parameter, so that doped with first Doped ions at each position of the gate material layers 120, preferably
, the first Doped ions distributed density of 120 position of gate material layers is uniform.It is wanted to meet specific electrical property
It asks, the concentration of first Doped ions can also be distributed along the thickness step of the gate material layers 120, from the grid material
The top surface of the bed of material 120 becomes larger from 100 surface of substrate, the concentration of first Doped ions, or from the grid
The top surface of material layer 120 gradually becomes smaller from 100 surface of substrate, the concentration of first Doped ions.
In other specific embodiments, in order to ensure that the first Doped ions can be distributed in the gate material layers
At 120 each position, first ion doping includes repeatedly doping step, for example including multiple injection step.It can be by
The doping parameters of the secondary each doping step of adjustment, so that the injection depth of difference doping step is not in the multiple doping step
Together, the first Doped ions of doping is finally enabled to be distributed at each position of the gate material layers 120.By multiple
It adulterates step and realizes first ion doping, additionally it is possible to adjust the at each depth location of the gate material layers 120
The concentration distribution of one Doped ions.During realizing the first ion doping using ion implantation technology, by repeatedly injecting
Step realizes the first ion doping, the Implantation Energy of bolus injection step can be reduced, to reduce first ion doping
To implant damage caused by the gate material layers 120.Preferably, first ion doping includes 1~5 injection step,
It is excessive to avoid injection step, cause the process time too long.
Referring to FIG. 3, the second ion doping is carried out to the gate material layers 120, what second ion doping used
Second Doped ions are p-type Doped ions.
The p-type Doped ions include B or BF2At least one of.The p-type Doped ions are for adjusting the grid
Work function between material layer 120 and substrate 100.Second ion doping can be real using ion implanting or diffusion technique
It is existing.
In present embodiment, second ion doping carries out after the first ion doping, second ion
The second Doped ions used are adulterated as B, using ion implantation technology, B energy is 2keV~6keV, and doping concentration is
1E19cm-3~1E20cm-3.With BF2It compares, B ion is not easy to spread into gate dielectric material layer 110, is conducive to improve semiconductor
The performance of structure.
In other specific embodiments, second ion doping can also be in the advance of first ion doping
Row.
After completing first ion doping and second ion doping, further includes: to the gate material layers
120 are made annealing treatment, to activate the first Doped ions and the second Doped ions in the gate material layers 120, simultaneously also
The damage generated in injection process in the gate material layers 120 can be repaired.The annealing temperature cannot be excessively high, keeps away
Exempt from first Doped ions and the second Doped ions to spread into the gate dielectric layer 110 and substrate 100.It is specific real at one
It applies in mode, the temperature range of the annealing is 950 DEG C~1100 DEG C.
Referring to FIG. 4, the gate material layers 120 (please referring to Fig. 3) and gate dielectric material layer (please referring to Fig. 3) are etched,
Gate structure is formed, the gate structure includes: to be situated between positioned at the gate dielectric layer 111 on 100 surface of substrate and positioned at the grid
The grid 121 on 111 surface of matter layer；Source electrode 421 and drain electrode 422 are formed in the substrate 100 of the gate structure two sides.
The Patterned masking layer of definition gate structure position and figure can be formed on 120 surface of gate material layers,
Using the Patterned masking layer as exposure mask, etches the gate material layers 120 and form grid 121, and the etching gate medium
Material layer 110 forms gate dielectric layer 111.
It further include the sidewall surfaces formation side wall 410 in the gate structure, to protect after forming the gate structure
Protect the side wall of the gate structure.Ion doping is carried out to the substrate 100 of the gate structure two sides again, forms the source of transistor
Pole 421 and drain electrode 422.In the specific embodiment, the semiconductor structure of formation is PMOS transistor, the source electrode 421 and leakage
Pole 422 is p-type doping, and is formed in the dopant well 101.The source electrode 421 and 422 outside of drain electrode have usually also formed
Fleet plough groove isolation structure (not shown).
Referring to FIG. 5, forming gate contact layer 510 in 121 top surface of grid.
In present embodiment, while 121 top surface of grid forms gate contact layer 510, also in institute
It states 421 surface of source electrode and forms Source contact layer 521, form drain contact layer 522 on 422 surfaces of the drain electrode.
The forming method of the gate contact layer 510, Source contact layer 521 and the gate contact layer 510 includes: in institute
After stating source electrode 421, drain electrode 422 and 121 forming metal layer on surface of grid, anneal, so that the metal layer and source electrode
421, the surfacing of drain electrode 422 and grid 121 carries out reaction and forms contact layer；Then unreacted metal layer is removed.
The material of the gate contact layer 510, Source contact layer 521 and drain contact layer 522 generallys use metal and partly leads
Body compound material, such as metal silicide materials, comprising: at least one of tungsten silicide and nickel silicide.
In the higher semiconductor technology of heat budget, more stable tungsten silicide is generallyd use as the gate contact
The material of layer 510, Source contact layer 521 and drain contact layer 522.In the specific embodiment, the gate contact layer 510,
The material of Source contact layer 521 and drain contact layer 522 is WSi2。
In other specific embodiments, proceeding to step shown in Fig. 3, second is carried out to the gate material layers 120
After ion doping, metal contact layer is formed on 120 surface of gate material layers；Then again to the metal contact layer, grid
Pole material layer 120 and gate dielectric material layer 110 perform etching, and form gate structure and the grid at the top of gate structure
Contact layer.It is forming the gate structure and then is continuously forming the source electrode in the substrate 100 of the gate structure two sides
And drain electrode, and it is subsequent without in source electrode and drain electrode surface formation contact layer.
In above-mentioned specific embodiment, due to can be improved p-type Doped ions and existing in the first Doped ions of grid doping
Therefore segregation coefficient in the grid can effectively avoid the second Doped ions in grid into the gate contact layer
Diffusion avoids grid that tcam-exhaustion occurs so that the second Doped ions in the grid are able to maintain that higher doping concentration,
To improve the performance of the semiconductor structure of formation.
Specific embodiment of the present utility model also provides a kind of semiconductor structure.
Referring to FIG. 5, the structural schematic diagram of the semiconductor structure for one specific embodiment of the utility model.
The semiconductor structure includes: substrate 100；Gate structure positioned at 100 surface of substrate, the gate structure
Grid 121 including being located at the gate dielectric layer 111 on 100 surface of substrate and positioned at 111 surface of gate dielectric layer；The grid
121 include the first doped region and the second doped region, doped with the first Doped ions in first doped region, described the
For two doped regions doped with the second Doped ions, second Doped ions are p-type Doped ions, the first Doped ions energy
Enough improve segregation coefficient of the p-type Doped ions in the grid 121.
The substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to the reality of device
Demand can choose suitable semiconductor material as substrate 100, be not limited thereto.In the specific embodiment, the lining
Bottom 100 is monocrystalline silicon wafer crystal.It is also formed with dopant well 101 in the substrate 100, in the specific embodiment, the substrate 100
Dopant well 101 be n-type doping trap, it is subsequent to form PMOS transistor on the dopant well 101.
The material of the gate dielectric layer 111 can be the dielectric materials such as silica, hafnium oxide, zirconium oxide, the grid 121
Material can be the semiconductor materials such as polysilicon, silicon carbide, germanium silicon.In this specific embodiment, the gate dielectric layer 111
Material be silica；The material of the grid 121 is polysilicon.
First Doped ions include at least one of C and Ge.In the specific embodiment, described first adulterate from
Son is C, and the doping concentration in the grid 121 is 5E18cm-3~1E20cm-3.It is described in another specific embodiment
First Doped ions include C and Ge, and wherein C ion doping concentration is 5E18cm-3~1E20cm-3；Ge ion doping concentration is
1E18cm-3~1E19cm-3。
In the specific embodiment, first doped region and the overlapping of the second doped region are distributed in entire grid
121.First Doped ions can be improved segregation coefficient of the p-type Doped ions in the grid 121, in order to make
The p-type Doped ions all have higher segregation coefficient at each position in the grid 121 so that p-type adulterate from
Son can be uniformly distributed in the grid 121, at each position of the grid 121 doped with described first adulterate from
Son, preferably, the first Doped ions distributed density of 121 position of the grid is uniform.In order to meet specific electrical property
It is required that the concentration of first Doped ions can also be distributed along the thickness step of the grid 121, from the grid 121
Top surface becomes larger from 100 surface of substrate, the concentration of first Doped ions, or from the top of the grid 121
Surface gradually becomes smaller from 100 surface of substrate, the concentration of first Doped ions.
Second Doped ions are p-type Doped ions, including B or BF2At least one of.The p-type Doped ions
For adjusting the work function between the grid 121 and substrate 100.It is a in the specific embodiment, second Doped ions
For B, doping concentration 1E19cm-3~1E20cm-3。
The sidewall surfaces of the gate structure are also formed with side wall 410, to protect the side wall of the gate structure.
In the specific embodiment, the semiconductor structure is PMOS transistor, and the source electrode 421 and drain electrode 422 are P
Type doping, and be located in the dopant well 101.The source electrode 421 and 422 outside of drain electrode have usually also formed shallow trench isolation knot
Structure (not shown).
121 top surface of grid is also formed with gate contact layer 510 and 421 surface of the source electrode formed it is active
Pole contact layer 521,422 surfaces of the drain electrode are formed with drain contact layer 522.The gate contact layer 510, Source contact layer
521 and the material of drain contact layer 522 generally use metal semiconductor compound material, such as metal silicide materials, comprising: tungsten
Silicide, nickel silicide etc..
In the higher semiconductor technology of heat budget, more stable tungsten silicide is generallyd use as the gate contact
The material of layer 510, Source contact layer 521 and drain contact layer 522.In the specific embodiment, the gate contact layer 510,
The material of Source contact layer 521 and drain contact layer 522 is WSi2。
In the semiconductor structure of above-mentioned specific embodiment, due to being mixed in the grid of the semiconductor structure doped with first
Heteroion can be improved segregation coefficient of the p-type Doped ions in the grid, therefore, can effectively avoid in grid
Two Doped ions are spread into the gate contact layer, so that the second Doped ions in the grid are able to maintain that higher mix
Miscellaneous concentration avoids grid that tcam-exhaustion occurs, to improve the performance of the semiconductor structure of formation.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
Art personnel can also make several improvements and modifications without departing from the principle of this utility model, these improvements and modifications
Also it should be regarded as the protection scope of the utility model.
Claims (7)
1. a kind of semiconductor structure characterized by comprising
Substrate；
Positioned at the gate structure of the substrate surface, the gate structure includes positioned at the gate dielectric layer of substrate surface and positioned at institute
State the grid on gate dielectric layer surface；
The grid includes the first doped region and the second doped region, in first doped region doped with first adulterate from
Son, for second doped region doped with the second Doped ions, second Doped ions are p-type Doped ions, described first
Doped ions can be improved segregation coefficient of the p-type Doped ions in the grid.
2. semiconductor structure according to claim 1, which is characterized in that first Doped ions include in C and Ge
It is at least one.
3. semiconductor structure according to claim 1, which is characterized in that first Doped ions are distributed in the grid
Each position at.
4. semiconductor structure according to claim 1, which is characterized in that second Doped ions include B or BF2In
It is at least one.
5. semiconductor structure according to claim 1, which is characterized in that further include: positioned at the gate structure two sides
Source electrode and drain electrode in substrate.
6. semiconductor structure according to claim 1, which is characterized in that further include: positioned at the gate top surface
Gate contact layer.
7. semiconductor structure according to claim 6, which is characterized in that the material of the gate contact layer includes tungsten silication
At least one of object and nickel silicide.
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| CN201820948488.4U CN208433413U (en) | 2018-06-20 | 2018-06-20 | Semiconductor structure |
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| CN201820948488.4U CN208433413U (en) | 2018-06-20 | 2018-06-20 | Semiconductor structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630535A (en) * | 2018-06-20 | 2018-10-09 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630535A (en) * | 2018-06-20 | 2018-10-09 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN108630535B (en) * | 2018-06-20 | 2024-04-02 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
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