CN105448916B

CN105448916B - Transistor and forming method thereof

Info

Publication number: CN105448916B
Application number: CN201410437401.3A
Authority: CN
Inventors: 邱慈云; 施雪捷; 辜良智; 吕瑞霖; 魏琰; 刘欣; 蔡建祥
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-08-29
Filing date: 2014-08-29
Publication date: 2018-10-16
Anticipated expiration: 2034-08-29
Also published as: CN105448916A

Abstract

A kind of transistor and forming method thereof, wherein the forming method of transistor, including：There is provided include adjacent first area, second area and third region semiconductor substrate；Well region ion implanting is carried out, well region is formed in the semiconductor substrate；Channel region ion implanting is carried out, the first doped region is formed in well region surface in the first region；Gate structure, the first doped region in gate structure covering first area are formed in the semiconductor substrate of the first area；Shallow Doped ions injection is carried out, forms shallow doping source region in the semiconductor substrate of the second area of gate structure side, shallow doped drain is formed in the semiconductor substrate in the third region of the gate structure other side；It is formed on shallow doping source region and raises source region, formed on shallow doped drain and raise drain region.The method of the present invention reduces the parasitic capacitance between source region and drain region and channel region and substrate.

Description

Transistor and forming method thereof

Technical field

The present invention relates to field of semiconductor fabrication, more particularly to a kind of forming method of transistor.

Background technology

Metal-oxide-semicondutor (MOS) transistor is the most basic device in semiconductor manufacturing, is widely used in In various integrated circuits, doping type when according to principal carrier and manufacture is different, is divided into NMOS and PMOS transistor.

The prior art provides a kind of production method of MOS transistor.It please refers to Fig.1 to the prior art shown in Fig. 3 The cross-sectional view of the forming process of MOS transistor.

Referring to FIG. 1, providing semiconductor base 100, isolation structure 101 is formed in the semiconductor base 100, it is described Semiconductor base 100 between isolation structure 101 is active area, and well region (not shown) is formed in the active area；Pass through One ion implanting is in well region surface doping foreign ion, to adjust the threshold voltage for the transistor being subsequently formed.

Then, gate dielectric layer 102 and grid electricity are sequentially formed on the semiconductor base 100 between the isolation structure 101 Pole 103, the gate dielectric layer 102 and gate electrode 103 constitute gate structure.

It continues to refer to figure 1, carries out oxidation technology, form the oxide layer 104 for covering the gate structure.

With reference to figure 2, shallow Doped ions injection (LDD) is carried out, the shape successively in the semiconductor base 100 of gate structure both sides At source drain extension area 105.

With reference to figure 3, the side wall 111 of gate structure is formed on the side wall of gate structure both sides；It is with the gate structure Mask, the well region for carrying out gate structure both sides carry out deep Doped ions injection, and the energy and dosage of deep Doped ions injection are more than The energy and dosage of shallow Doped ions injection, form source region 112 and drain region 113, the source in the well region of gate structure both sides The depth in area 112 and drain region 113 is more than the depth in source drain extension area 105.

However, the performance for the transistor that the prior art is formed is still to be improved.

Invention content

Problems solved by the invention how is reduced between transistor source region and drain region and channel region and semiconductor substrate Or the parasitic capacitance between drain region and channel region and semiconductor substrate.

To solve the above problems, the present invention provides a kind of forming method of transistor, including：Semiconductor substrate, institute are provided The first area, second area and third region that semiconductor substrate includes adjacent are stated, position is distinguished in second area and third region Both sides in first area；Well region ion implanting is carried out, the semiconductor in the first area, second area and third region serves as a contrast Well region is formed in bottom；Channel region ion implanting is carried out, the first doped region of formation in well region surface in the first region, described the The doping type of one doped region is identical as the doping type of well region；Grid knot is formed in the semiconductor substrate of the first area Structure, the gate structure cover the first doped region in first area；Shallow Doped ions injection is carried out, in gate structure side Shallow doping source region is formed in the semiconductor substrate of second area, in the semiconductor substrate in the third region of the gate structure other side It forms shallow doped drain, the shallow doping source region and the doping type of shallow doped drain and the doping type of well region is opposite；Shallow It is formed on doping source region and raises source region, raised doped with foreign ion in source region, the top surface for raising source region is higher than semiconductor The surface of substrate, it is described to raise source region and shallow doping source region composition source region, it is formed on shallow doped drain and raises drain region, raise leakage Doped with foreign ion in area, the top surface for raising drain region is higher than the surface of semiconductor substrate, described to raise drain region and shallow mix Miscellaneous drain region constitutes drain region.

Optionally, before carrying out channel region ion implanting, mask layer, the mask are formed in the semiconductor substrate surface There is the first opening of the semiconductor substrate surface for exposing first area in layer；After forming mask layer, with the mask layer For mask, channel region ion implanting, the well region table in first area are carried out to the semiconductor substrate of first area along the first opening The first doped region is formed in face.

Optionally, the gate structure covers first doped region, and the both sides side wall of the gate structure is beyond the The edges at two ends of one doped region.

Optionally, gate structure side side wall beyond the first doped region corresponding end margin distance be 1~ 100nm。

Optionally, when the transistor of formation is NMOS transistor, the doping type of the well region and the first doped region is P Type, the shallow doping source region, shallow doped drain, raise source region and raise drain region doping type be N-type, the channel region ion The p type impurity ion of injection injection is boron ion or indium ion, and the dosage range of implanting impurity ion is 1E12~4E13atom/ cm², implant angle is 0~20 degree, and energy range when injecting boron ion is 4~30Kev, injects energy range when indium ion For 30~300Kev；The N-type impurity ion of the shallow Doped ions injection is one or both of phosphonium ion or arsenic ion, note Energy when entering arsenic ion is 3~60Kev, and dosage is 3E13~2E15atom/cm², implant angle is 0~45 degree, injects phosphorus Energy when ion is 3~80Kev, and dosage is 2E13~5E14atom/cm², implant angle is 0~45 degree.

Optionally, when the transistor of formation is PMOS transistor, the doping type of the well region and the first doped region is N Type, the shallow doping source region, shallow doped drain, raise source region and raise drain region doping type be p-type, the channel region ion The N-type impurity ion of injection injection is phosphonium ion or arsenic ion, and the dosage range of implanting impurity ion is 1E12~4E13atom/ cm², implant angle is 0~20 degree, and energy range when injecting boron ion is 10~70Kev, injects energy model when arsenic ion It encloses for 20~140Kev；The p type impurity ion of the shallow Doped ions injection is one or both of boron ion or indium ion, Energy when injecting boron ion is 3~30Kev, and dosage is 3E13~2E15atom/cm², implant angle is 0~45 degree, injection Energy when indium ion is 20~80Kev, and dosage is 1E13~5E13atom/cm², implant angle is 0~45 degree.

Optionally, the shallow doping source region and the opposite lift of the doping type of shallow doped drain and the doping type of well region High source region and the thickness for raising drain region are 30~100nm, raise source region and raise concentration impurity ion in drain region be 1E20~ 5E20atom/cm³。

Optionally, described to raise source region and raise drain region formation process as doping selective epitaxial process in situ.

Optionally, the formation process raised source region and raise drain region is：First is formed on the shallow doping source region Epitaxial layer；The second epitaxial layer is formed on the shallow doped drain；The first ion implanting is carried out, in the first epitaxial layer impurity Source region is raised in ion, formation, and drain region is raised in the impurity ion in the second epitaxial layer, formation, wherein the first ion implanting is noted When entering N-type impurity ion, N-type impurity ion includes phosphonium ion, and the energy of injection is 4~12Kev, implantation dosage be 2E15~ 2E16atom/cm², the first ion implanting implanting p-type foreign ion, p type impurity ion includes boron ion, and the energy of injection is 2 ~8Kev, implantation dosage are 2E15~2E16atom/cm²。

The embodiment of the present invention additionally provides a kind of forming method of transistor, including：Semiconductor substrate is provided, it is described partly to lead Body substrate includes adjacent first area, second area and third region, and second area and third region are located at first The both sides in region；Carry out well region ion implanting, the shape in the semiconductor substrate of the first area, second area and third region At well region；Channel region ion implanting is carried out, the first doped region, institute are formed in the well region surface in first area and second area The doping type for stating the first doped region is identical as the doping type of well region；Grid are formed in the semiconductor substrate of the first area Pole structure, the gate structure cover the first doped region in first area；Shallow Doped ions injection is carried out, in gate structure one Shallow doping source region is formed in the semiconductor substrate of the second area of side, the semiconductor lining in the third region of the gate structure other side Shallow doped drain, the shallow doping source region and the doping type of shallow doped drain are formed in bottom and the doping type of well region is opposite； It is formed on shallow doping source region and raises source region, raised in source region doped with foreign ion, raise the top surface of source region higher than half The surface of conductor substrate, it is described to raise source region and shallow doping source region composition source region, it is formed on shallow doped drain and raises drain region, lifted Doped with foreign ion in high drain region, the top surface for raising drain region is higher than the surface of semiconductor substrate, it is described raise drain region and Shallow doped drain constitutes drain region.

Optionally, before carrying out channel region ion implanting, mask layer, the mask are formed in the semiconductor substrate surface There is the second opening of the semiconductor substrate for exposing first area and second area in layer；After forming mask layer, with described Mask layer is mask, and channel region ion implanting is carried out to the semiconductor substrate of first area and second area along the second opening, The first doped region is formed in first area and the well region surface of second area.

Optionally, the first doped region of gate structure covering first area, and the close third region of the gate structure Side side wall beyond the first doped region close third region an end margin.

Optionally, the side side wall in the close third region of the gate structure exceeds the close third area of the first doped region The distance of one end margin in domain is 1~100nm.

The present invention also provides a kind of transistors, including：Semiconductor substrate, the semiconductor substrate include adjacent One region, second area and third region, second area and third region are located at the both sides of first area；Positioned at the firstth area Well region in the semiconductor substrate in domain, second area and third region；First in well region surface in first area is mixed The doping type in miscellaneous area, first doped region is identical as the doping type of well region；Semiconductor positioned at the first area serves as a contrast Gate structure on bottom, the gate structure cover the first doped region in first area；Second positioned at gate structure side Shallow doping source region in the semiconductor substrate in region is located at shallow in the semiconductor substrate in the third region of the gate structure other side Doped drain, the shallow doping source region and the doping type of shallow doped drain and the doping type of well region are opposite；Positioned at shallow doping Source region is raised in source region, raises in source region doped with foreign ion, raises the top surface of source region higher than semiconductor substrate Surface, it is described to raise source region and shallow doping source region composition source region；Drain region is raised on shallow doped drain, raises in drain region and mixes Miscellaneous to have foreign ion, the top surface for raising drain region is higher than the surface of semiconductor substrate, described to raise drain region and shallow doped drain Constitute drain region.

Optionally, the depth of first doped region is 30~200nm, and foreign ion is a concentration of in the first doped region 1E17~5E18atom/cm³。

Optionally, the doping type of the doping type and well region of the shallow doping source region and shallow doped drain is on the contrary, described The depth of shallow doping source region and shallow doped drain is 15~50nm, and concentration impurity ion is in shallow doping source region and shallow doped drain 3E18~3E20atom/cm³。

Optionally, it raises source region and raises the doping type of the doping type and shallow doping source region and shallow doped drain in drain region Identical, the thickness raised source region and raise drain region is 30~100nm, and the foreign ion raised source region and raised in drain region is dense Degree is 1E20~5E20atom/cm³。

Optionally, when the transistor is NMOS transistor, the doping type of the well region and the first doped region is P Type, the shallow doping source region, shallow doped drain raise source region and raise the doping type in drain region as N-type.

Optionally, when the transistor is PMOS transistor, the doping type of the well region and the first doped region is N Type, the shallow doping source region, shallow doped drain raise source region and raise the doping type in drain region as p-type.

The present invention also provides a kind of transistors, including：Semiconductor substrate, the semiconductor substrate include adjacent One region, second area and third region, second area and third region are located at the both sides of first area；Positioned at the firstth area Well region in the semiconductor substrate in domain, second area and third region；Well region surface in first area and second area The doping type of the first interior doped region, first doped region is identical as the doping type of well region；Positioned at the first area Semiconductor substrate on gate structure, the first doped region in gate structure covering first area；Positioned at gate structure Shallow doping source region in the semiconductor substrate of the second area of side is located at the semiconductor in the third region of the gate structure other side Shallow doped drain in substrate, the shallow doping source region and the doping type of shallow doped drain and the doping type of well region are opposite； Source region is raised on shallow doping source region, raises in source region doped with foreign ion, raises the top surface of source region higher than half The surface of conductor substrate, it is described to raise source region and shallow doping source region composition source region；Drain region, lift are raised on shallow doped drain Doped with foreign ion in high drain region, the top surface for raising drain region is higher than the surface of semiconductor substrate, it is described raise drain region and Shallow doped drain constitutes drain region.

Compared with prior art, technical scheme of the present invention has the following advantages：

The forming method of the transistor of the present invention, the semiconductor in the first area, second area and third region serve as a contrast Well region is formed in bottom；Carry out channel region ion implanting, the well region table in first area (or first area and second area) The first doped region is formed in face, the doping type of first doped region is identical as the doping type of well region；In firstth area Gate structure, the first doped region in gate structure covering first area are formed in the semiconductor substrate in domain；Carry out shallow mix Heteroion injects, and shallow doping source region is formed in the semiconductor substrate of the second area of gate structure side, another in gate structure Shallow doped drain is formed in the semiconductor substrate in the third region of side；It is formed on shallow doping source region and raises source region, raise source Doped with foreign ion in area, the top surface for raising source region is higher than the surface of semiconductor substrate；It is formed on shallow doped drain Drain region is raised, is raised doped with foreign ion in drain region, the top surface for raising drain region is higher than the surface of semiconductor substrate.This hair The method of bright transistor, after forming well region in the semiconductor substrate of the first area, second area and third region, then Channel region ion implanting is carried out, forms the first doping in the well region surface in first area or first area and second area Area, to adjust the threshold voltage of the transistor formed, when carrying out channel region ion implanting, the object of channel region ion implanting injection The only well region of first area (or first area and second area), the well region of second area and third region (or third region) Surface will not by implanting impurity ion, therefore the concentration impurity ion in the drain region in the source region of second area and third region relative to The concentration impurity ion in the source region of prior art transistor and drain region reduces (or the concentration impurity ion in the drain region in third region The concentration impurity ion in the drain region of transistor reduces compared with the existing technology), to reduce drain region and source region and channel region with And the parasitic capacitance between the parasitic capacitance (or between drain region and channel region and semiconductor substrate) between semiconductor substrate, Improve the switching rate of transistor.In addition, the drain region that the present invention is formed includes raising drain region and shallow doped drain, source region includes It is described to raise source region and shallow doping source region, it raises source region and raises the semiconductor substrate that drain region is located at second area and third region On surface, shallow doping source region and shallow doped drain are located in well region, are formed by shallow Doped ions injection technology, shallow doping source region Can be shallower with shallow doped drain depth, thus reduce the contact area between drain region and source region and channel region and drain region and Contact area between source region and semiconductor substrate, to reduce parasitic capacitance between drain region and source region and channel region and The size of parasitic capacitance between drain region and source region and semiconductor substrate, it is described raise source region and raise drain region be located at semiconductor serve as a contrast On bottom surface so that foreign ion control source region and is raised in drain region raising, and prevents from adulterating when the source region to be formed and drain region Foreign ion is spread relatively deep in semiconductor substrate, and increases the contact area of source region and drain region and channel region.

Further, the gate structure of formation covers first doped region, and the both sides side wall of the gate structure exceeds The edges at two ends of first doped region so that the first doped region of formation and the subsequently shape in the semiconductor substrate of gate structure both sides At shallow doping source region and shallow doped drain do not contact so that the first doped region will not be with shallow doping source region and shallow doped drain The PN junction formed between area and semiconductor substrate contacts, and reduces the Doped ions concentration of PN junction, is conducive to reduce drain region and source Parasitic capacitance between area and channel region and semiconductor substrate improves the switching rate of transistor.

Further, the first doped region of the gate structure covering first area of formation, and the gate structure close to the One end margin in close third region of the side side wall in three regions beyond the first doped region so that the first doped region of formation leans on The edge in nearly third region and the shallow doped drain subsequently formed in the semiconductor substrate in the third region of gate structure side It does not contact, so that the PN junction that the first doped region will not be formed between shallow doped drain and semiconductor substrate contacts, reduces The Doped ions concentration of PN junction between shallow doped drain and semiconductor substrate is conducive to reduce drain region and be led with channel region and partly Parasitic capacitance between body substrate improves the switching rate of transistor.

Further, the second opening formed in mask layer, the second opening expose partly leading for first area and second area Body substrate surface, therefore process window when the second opening of formation increases, the second opening of formation has higher position and ruler Very little precision subsequently carries out the positions and dimensions precision of the first doped region of channel region ion implanting formation along the second opening accordingly Also higher, and due to the semiconductor substrate surface in mask layer covering third region, when carrying out channel region ion implanting, It will not be by implanting impurity ion, to reduce the parasitism between the drain region being subsequently formed and channel region in the well region in third region Capacitance, though carry out channel region ion implanting when first area semiconductor substrate in if can inject part foreign ion so that Parasitic capacitance between the source region being subsequently formed and channel region can become larger, but due to the parasitic capacitance between source region and channel region Smaller, the switching rate and switch of the increase of the parasitic capacitance to transistor is influenced on the switching rate of transistor and switching loss Loss influences can be ignored.

The transistor of the present invention, first doped region are only located in the well region of first area (or first area and second Region) well region in, the concentration impurity ion for reducing second area and third region (or reduces the impurity in third region Ion concentration), to reduce between the parasitic capacitance between channel region and drain region and source region (or channel region and drain region) Parasitic capacitance improves the switching rate of transistor.In addition, drain region includes raising drain region and shallow doped drain, source region includes institute It states and raises source region and shallow doping source region, shallow doping source region and shallow doped drain are located in well region, shallow doping source region and shallow doped drain Area's depth can be shallower, raises source region and is located in the semiconductor substrate of second area, raises drain region and is located at partly leading for third region In body substrate, thus the contact area of drain region and channel region is reduced, to reduce the parasitism electricity between drain region and channel region The size of appearance, it is described to raise source region and raise drain region and be located on semiconductor substrate surface, it is described to raise source region and raise drain region and be Transistor passes through enough carriers when working.

Description of the drawings

Fig. 1 to the forming process of the MOS transistor of the prior art shown in Fig. 3 cross-sectional view；

Fig. 4~Fig. 9 is the cross-sectional view of one embodiment of the invention transistor forming process；

Figure 10~Figure 14 is the cross-sectional view of the forming process of another embodiment of the present invention transistor.

Specific implementation mode

As described in the background art, the performance of the transistor of the formation of the prior art is still to be improved, for example, transistor conduct Switching device in application, the switching rate and switching loss of transistor be evaluate transistor performance two important indicators, it is existing Transistor as switching device when, the problems such as it is slow that there is also switching rates, and switching loss is big.

The study found that the parasitism electricity between the drain electrode and channel region of the switching rate and switching loss and transistor of transistor Hold closely related, the parasitic capacitance between parasitic capacitance or drain electrode and channel region between source region and channel region is bigger, crystal The switching rate of pipe is slower, and switching loss is bigger.The formation process of the transistor of the prior art is further ground Study carefully discovery, the parasitic capacitance between parasitic capacitance or drain electrode and channel region between source region and channel region is larger mainly there are two sides The reason of face：On the one hand, after forming well region in the semiconductor substrate, the surface of well region is doped to adjust by ion implanting The threshold voltage of transistor being subsequently formed is saved, on well region surface is that will not form mask before carrying out the first ion implanting Layer, the first ion implanting is directed to the surface to entire well region, formed subsequently in the well region of gate structure both sides source region and When drain region, the foreign ion of the first ion implanting injection can also be located at drain region and source region, thus the injection of the first ion implanting is miscellaneous Matter ion will increase the concentration impurity ion in drain region so that the parasitic capacitance of source region and drain region between channel region can increase Greatly；On the other hand, the depth in the drain region of the formation of the prior art is deeper, thus the contact area of drain region and channel region is also larger, So that the parasitic capacitance between drain region and channel region is also larger.The transistor formed to existing technology is further studied It was found that the parasitic capacitance between source region and channel region, the parasitic capacitance between drain region and channel region opens transistor The influence bigger of rate and switching loss is closed, it is high voltage that reason, which needs to apply in drain electrode when transistor works, is completed Reversion from no-voltage (or low-voltage) to high voltage when, the parasitic capacitance charge and discharge time between drain region and channel region can be very long, Thus switching rate reduces, switching loss increases.

For this purpose, the present invention provides a kind of transistor and forming method thereof, wherein the forming method of transistor of the present invention, After forming well region in the semiconductor substrate of the first area, second area and third region, channel region ion note is then carried out Enter, forms the first doped region in the well region surface in first area (or first area and second area), to be formed with adjusting Transistor threshold voltage, carry out channel region ion implanting when, channel region ion implanting injection object be first area Well region, the channel region of the well region surface of first area as transistor, therefore, when carrying out channel region ion implanting, second It the well region surface in region and third region (or third region) will not be by implanting impurity ion, subsequently in second area and third When region forms source region and drain region, concentration impurity ion source region and the leakage compared with the existing technology in source region and drain region (or drain region) The concentration impurity ion in area reduces, to reduce the parasitic capacitance between drain region and source region and channel region and semiconductor substrate Parasitic capacitance between (or between drain region and channel region and semiconductor substrate), in addition, heretofore described raise drain region Drain region is constituted with shallow doped drain, it is described to raise source region and shallow doping source region composition source region, shallow doping source region and shallow doped drain In well region, formed by shallow Doped ions injection technology, depth can be shallower, raise source region and raise drain region be located at partly lead On body substrate surface, thus source region and drain region be located at the depth of the part in semiconductor substrate can be very shallow, reduce drain region and Source region and channel region and the contact area of semiconductor substrate, to reduce the parasitism electricity between drain region and source region and channel region The size of appearance, it is described to raise source region and raise drain region and be located on semiconductor substrate surface so that foreign ion control is in the source of raising It area and raises in drain region, prevents the foreign ion adulterated when the source region to be formed and drain region from being spread in semiconductor substrate relatively deep, And increase the contact area of source region and drain region and channel region.

To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality In making should include length, width and depth three-dimensional space.

Fig. 4~Fig. 9 is the cross-sectional view of one embodiment of the invention transistor forming process.

Referring to FIG. 4, provide semiconductor substrate 200, the semiconductor substrate 200 include adjacent first area 11, Second area 12 and third region 13, second area 12 and third region 13 are located at the both sides of first area 11；Carry out trap Area's ion implanting forms well region in the semiconductor substrate 200 of the first area 11, second area 12 and third region 13 203。

The semiconductor substrate 200 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), silicon carbide (SiC)；Can also be silicon-on-insulator (SOI), germanium on insulator (GOI)；Or can also be other materials, such as arsenic III-V compounds of group such as gallium.In the present embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.

The semiconductor substrate 200 includes adjacent first area 11, second area 12 and third region 13, the firstth area The semiconductor substrate 200 in domain 11 is subsequently formed the channel region of transistor, and the semiconductor substrate of the second area 12 is subsequently formed The semiconductor substrate 200 of the shallow doping source region of transistor, third region 13 is subsequently formed the shallow doped drain of transistor.

Well region 203 is formed in semiconductor substrate 200 by well region ion implanting, according to the type of the transistor of formation Difference adulterates different types of foreign ion into semiconductor substrate 200, forms well region 203.In one embodiment, work as formation Transistor when being the transistor of N-type, the foreign ion of well region ion implanting injection is p type impurity ion, and the p-type is miscellaneous Matter ion is one or more of boron ion, gallium ion, indium ion.In another embodiment, when the transistor of formation is p-type Transistor when, the foreign ion of well region ion implanting injection is the foreign ion of N-type, and the foreign ion of the N-type is One or several kinds in phosphonium ion, arsenic ion, gallium ion.

Isolation structure 201 is also formed in the semiconductor substrate 200, the isolation structure 201 is used for electric isolation phase Adjacent active area, in the present embodiment, the isolation structure is fleet plough groove isolation structure, the forming process of the isolation structure 201 For：It etches the semiconductor substrate 200 and forms groove；Form the spacer material layer for covering 200 surface of semiconductor substrate, institute State the full groove of spacer material layer filling；Using the isolation on 200 surface of chemical mechanical milling tech removal semiconductor substrate Material layer forms isolation structure 201 in the trench.

The isolation structure 201 can be formed after or before forming well region 203.

With reference to figure 5, mask layer 204 is formed on 200 surface of the semiconductor substrate, there is exposure in the mask layer 204 Go out first opening 205 on 200 surface of semiconductor substrate of first area 11.

The mask layer 204 prevents second area 12 and third region 13 when subsequently carrying out channel region ion implanting Well region is also injected into foreign ion in surface.

The mask layer 204 can be with single-layer or multi-layer (>=2 layers) stacked structure.In one embodiment, the mask layer 204 It can be double stacked structure, include the first mask layer on 200 surface of semiconductor substrate and on the first mask layer The second mask layer.

In the present embodiment, the material of the mask layer 204 is photoresist, by exposed and developed technique in the mask layer The first opening 205 is formed in 204.In other embodiments of the invention, the material of the mask layer 204 can also be oxidation Silicon, silicon nitride etc..

Before forming mask layer 204, protective layer (not shown), institute are formed on 200 surface of the semiconductor substrate Protective layer is stated when subsequent ion injects, the lattice damage for preventing semiconductor substrate 200 from generating, and control the tunnel of ion implanting Effect.

After forming mask layer 204 it is mask with the mask layer 204 with reference to figure 6, along first 205 pair of first area of opening The semiconductor substrate 200 in domain 11 carries out channel region ion implanting, and the first doping is formed in 203 surface of well region of first area 11 The doping type in area 206, first doped region 206 is identical as the doping type of well region 203.

The purpose for forming the first doped region 206 is to adjust the threshold voltage for the transistor being subsequently formed.

Before the present invention carries out channel region ion implanting, 12 quilt of third region 13 and second area of semiconductor substrate 200 Mask layer 204 covers, therefore when carrying out channel region ion implanting, foreign ion can only be injected into the well region of first area 11 203 surfaces, and will not be by implanting impurity ion in 203 surface of second area 12 and the well region in third region 13, thus subsequently exist When forming source region and drain region in second area 12 and the well region in third region 13, the concentration impurity ion in source region and drain region will not be because Increase for channel region ion implanting, transistor compared with the existing technology, the concentration impurity ion in source region and drain region reduces, and has Conducive to the parasitic capacitance reduced between drain region and channel region.

The study found that when forming the first doped region 206, if channel region ion implanting Implantation Energy is too low, injection it is total Dosage is easy fluctuation, so as to cause the fluctuation of threshold value, and cannot effectively obstruct the break-through between source region and drain region；Channel region If ion implanting Implantation Energy is too high, significant cross direction profiles are had, will increase junction capacity, and need prodigious dosage Rational threshold voltage can be effectively formed.

In the present embodiment, the doping type of first doped region 206 is identical as the doping type of well region 203.It is real one It applies in example, when the transistor being subsequently formed is the transistor of N-type, the doping type of well region 203 is p-type, first doping The doping type in area 206 is also p-type, and 200 implanting p-type of semiconductor substrate by channel region ion implanting to first area 11 is miscellaneous Matter ion forms the first doped region 206 that doping type is p-type, and the p type impurity ion is boron ion or indium ion, and injection is miscellaneous The dosage range of matter ion is 1E12~4E13atom/cm², implant angle is 0~20 degree, injects energy range when boron ion For 4~30Kev, energy range when injecting indium ion is 30~300Kev.

In another embodiment, when the transistor being subsequently formed is the transistor of p-type, the doping type of well region 203 is N Type, the doping type of first doped region 206 are also N-type, by channel region ion implanting to the semiconductor of first area 11 Substrate 200 injects N-type impurity ion and forms the first doped region 206 that doping type is N-type, and the foreign ion of the N-type is phosphorus The dosage range of ion or arsenic ion, implanting impurity ion is 1E12~4E13atom/cm², implant angle is 0~20 degree, note Energy range when entering boron ion is 10~70Kev, and energy range when injecting arsenic ion is 20~140Kev.

In one embodiment, the depth of the first doped region 206 of formation is 30~200nm, impurity in the first doped region 206 A concentration of 1E17~5E18atom/cm of ion³。

In the present embodiment, the width of the width of the first doped region 206 of formation and the semiconductor substrate 200 of first area 11 It is equal.

In other embodiments of the invention, the width of first doped region is less than the semiconductor substrate of first area The edge of width, the i.e. semiconductor substrate of the Edge Distance first area of the first doped region has certain distance.

Subsequently when forming gate structure in the semiconductor substrate of first area, the gate structure covering described first of formation Doped region, and the both sides side wall of the gate structure exceeds the edges at two ends of the first doped region so that the first doped region of formation It is not contacted with the shallow doping source region and shallow doped drain subsequently formed in the semiconductor substrate of gate structure both sides, so that First doped region will not be contacted with the PN junction formed between shallow doping source region and shallow doped drain and semiconductor substrate, reduce PN The Doped ions concentration of knot is conducive to reduce the parasitic capacitance between drain region and source region and channel region and semiconductor substrate, carry The switching rate of high transistor.

With reference to figure 7, gate structure is formed in the semiconductor substrate 200 of the first area 11, the gate structure covers The first doped region 206 in lid first area 11.

The gate structure includes the gate dielectric layer 207 being located in semiconductor substrate 200, the covering of gate dielectric layer 207 first The surface of doped region 206, the gate electrode 208 on gate dielectric layer 207.

Side wall 209 is also formed on the both sides side wall of the gate structure, the side wall is subsequently carrying out shallow Doped ions Gate electrode 208 is protected when injection.

The detailed process that the gate structure is formed is：Form the gate dielectric material layer for covering the semiconductor substrate 200； Layer of gate electrode material is formed on the gate dielectric material layer；Mask layer, the mask are formed in the layer of gate electrode material Layer covers the part layer of gate electrode material on first doped region 206；Using the mask layer as gate electrode described in mask etching Material layer and gate dielectric material layer；Gate dielectric layer 207 is formed on semiconductor substrate 200, grid electricity is formed on gate dielectric layer 207 Pole 208.

In other embodiments of the invention, when the width for the first doped region being previously formed is less than partly leading for first area When the width of body substrate, the gate structure formed in the semiconductor substrate of first area covers first doped region, and institute The both sides side wall for stating gate structure exceeds the edges at two ends of the first doped region.

In a specific embodiment, gate structure side side wall beyond the first doped region corresponding end margin away from From for 1~100nm so that the first doped region effectively has while effective adjusting threshold voltage and reduces drain region and source region Parasitic capacitance between channel region and semiconductor substrate.

In the present embodiment, the material of the gate dielectric layer is silica, and the material of gate electrode is polysilicon.

In other embodiments of the invention, the gate structure is metal gates, and the material of the gate dielectric layer can be with Material for high-k dielectric material, the gate electrode can be metal.The metal gates are formed by rear grid technique, herein not It repeats again.

With reference to figure 8, shallow Doped ions injection is carried out, in the semiconductor substrate 200 of the second area 12 of gate structure side It is interior to form shallow doping source region 211, shallow doped drain is formed in the semiconductor substrate 200 in the third region 13 of the gate structure other side Area 210.

The shallow doping source region 211 is located in the well region 203 of second area 12, and the shallow doped drain 210 is located at third In the well region 203 in region 13, the depth of shallow doping source region 211 and shallow doped drain 210 is less than the depth of well region 203.

The study found that when forming the first doped region 206, if channel region ion implanting Implantation Energy is too low, semiconductor lining The protective layer that bottom surface is formed is easy to influence the accumulated dose variation of injection, and the accumulated dose variation of injection can cause the change of threshold voltage Change, and cannot effectively obstruct the break-through between source region and drain region；If channel region ion implanting Implantation Energy is too high, have Significant cross direction profiles will increase junction capacity, and need prodigious dosage that can just be effectively formed rational threshold voltage.

In the present embodiment, the doping type of shallow doping source region 211 and shallow doped drain 210 and the doping type phase of well region Instead.In one embodiment, when the transistor being subsequently formed is the transistor of N-type, the doping type of well region 203 is p-type, described Shallow doping source region 211 and the doping type of shallow doped drain 210 are N-type, are injected to 12 He of second area by shallow Doped ions The foreign ion that N-type is injected in the semiconductor substrate 200 in third region 13, forms the shallow doping source region 211 of N-type and shallow doped drain The foreign ion in area 210, the shallow Doped ions injection is one or both of phosphonium ion or arsenic ion, when injecting arsenic ion Energy be 3~60Kev, dosage be 3E13~2E15atom/cm², implant angle is 0~45 degree, injects energy when phosphonium ion Amount is 3~80Kev, and dosage is 2E13~5E14atom/cm², implant angle is 0~45 degree.

In another embodiment, when the transistor being subsequently formed is the transistor of p-type, the doping type of well region 203 is N The doping type of type, the shallow doping source region 211 and shallow doped drain 210 is p-type, is injected to the secondth area by shallow Doped ions The foreign ion of implanting p-type in the semiconductor substrate 200 in domain 12 and third region 13 forms the shallow doping source region 211 of p-type and shallow The foreign ion of doped drain 210, the shallow Doped ions injection is one or both of boron ion or indium ion, injects boron Energy when ion is 3~30Kev, and dosage is 3E13~2E15atom/cm², implant angle is 0~45 degree, injects indium ion When energy be 20~80Kev, dosage be 1E13~5E13atom/cm², implant angle is 0~45 degree.

In the present embodiment, shallow doping source region 211 and follow-up formed on a semiconductor substrate raise source region composition source region, shallow to mix The drain region of raising formed on miscellaneous drain region 210 and Subsequent semiconductor substrate constitutes drain region, thus the shallow of formation is mixed in semiconductor substrate Miscellaneous source region 211 and the depth of shallow doped drain 210 can be shallower, shallow doping source region 211 and shallow doped drain 210 and channel region Contact area reduces, to subtract the parasitic capacitance for having descended shallow doping source region 211 and shallow doped drain 210 and channel region.

In one embodiment, the depth of the shallow doping source region 211 and shallow doped drain 210 is 15~50nm, shallow doping Concentration impurity ion is 3E18~3E20atom/cm in source region 211 and shallow doped drain 210³。

It with reference to figure 9, is formed on shallow doping source region 211 and raises source region 213, raised in source region 213 doped with foreign ion, The top surface for raising source region 213 is higher than the surface of semiconductor substrate 200, described to raise 211 structure of source region 213 and shallow doping source region At the source region of transistor；It is formed on shallow doped drain 210 and raises drain region 212, raised in drain region 212 doped with foreign ion, The top surface for raising drain region 212 is higher than the surface of semiconductor substrate 200, described to raise 210 structure of drain region 212 and shallow doped drain At the drain region of transistor.

It raises source region 213 and raises mixing for the doping type in drain region 212 and shallow doping source region 211 and shallow doped drain 210 Miscellany type is identical, in one embodiment, when the transistor being subsequently formed is the transistor of N-type, shallow doping source region 211 and shallow mixes The doping type in miscellaneous drain region 210 is N-type, and the doping type raised source region 213 and raise drain region 212 is also N-type.Another In embodiment, when the transistor being subsequently formed is the transistor of p-type, the doping of shallow doping source region 211 and shallow doped drain 210 Type is p-type, and the doping type raised source region 213 and raise drain region 212 is also p-type.

The thickness raised source region 213 and raise drain region 212 is 30~100nm, raises source region and raises in drain region Concentration impurity ion is 1E20~5E20atom/cm³。

The material raised source region 213 and raise drain region 212 is polysilicon, SiGe or silicon carbide, in the present embodiment, institute It states and raises source region 213 and raise the material in drain region 212 as polysilicon.

In one embodiment, described to raise source region 213 and raise 212 formation process of drain region as doping selective epitaxial in situ Technique, using forming material to raise source region 213 described in polysilicon and raising drain region 212 as an example, the doping choosing in situ The temperature of selecting property epitaxy technique is 650-800 degrees Celsius, and pressure is 5-20torr, silicon source gas SiH₄Or SiCl₂H₄, silicon source The flow of gas is 30-200sccm, and selective gas is HCl, and the flow of selective gas is 50-300sccm, further includes miscellaneous The flow of matter source gas, impurity source gas is 30-200sccm, different according to the type for forming transistor, selects different impurity Source gas, for example when the transistor of formation N-type, the impurity source gas is phosphorus source gas, arsenic source gas, forms the crystal of p-type Guan Shi, the impurity source gas are boron source gas.

In another embodiment, the formation process raised source region 213 and raise drain region 212 is：In the shallow doping The first epitaxial layer is formed in source region；The second epitaxial layer is formed on the shallow doped drain；The first ion implanting is carried out, first Source region 213 is raised in epitaxial layer impurity ion, formation, and drain region is raised in the impurity ion in the second epitaxial layer, formation 212.When being formed simultaneously different types of transistor in semiconductor substrate, what this method can form different doping types raises source Area 213 and raise drain region 212.In one embodiment, in the foreign ion raised source region 213 He raise 212 doped N-type of drain region, N Type foreign ion includes phosphonium ion, and the energy of the first ion implanting is 4~12Kev, and dosage is 2E15~2E16atom/cm². In another embodiment, in the foreign ion raised source region 213 He raise 212 doped p-type of drain region, p type impurity ion include boron from The energy of son, the first ion implanting is 2~8Kev, and dosage is 2E15~2E16atom/cm²。

In another embodiment, described to raise source region 213 and raise 212 forming process of drain region and be：Using chemical vapor deposition Product technique forms the polysilicon material layer for covering the semiconductor substrate 200 and gate structure；In the polysilicon material layer Impurity ion；The polysilicon material layer is etched, is formed on shallow doping source region 211 and raises source region 213, in shallow doped drain It is formed in area 210 and raises drain region 212.

Further include annealing process after carrying out the first ion implanting, with the foreign ion of activation injection, and makes foreign ion Uniformly diffusion.

Compared with the prior art, it is injected by deep Doped ions, forms deep doped region as source region, transistor work is provided When most of carrier, in the embodiment of the present invention, the drain region of formation includes raising drain region 212 and shallow doped drain 210, is formed Source region include it is described raise source region 213 and shallow doping source region 211, shallow doping source region 211 and shallow doped drain 210 are located at well region It is interior, it is formed by shallow Doped ions injection technology, depth can be shallower, raises source region 213 and raises drain region 212 and be located at semiconductor On 200 surface of substrate, thus source region and drain region be located at the depth of the part in semiconductor substrate 200 can be very shallow, reduce leakage Area and source region and channel region and the contact area of semiconductor substrate 200, to reduce drain region and source region and channel region and The size of parasitic capacitance between semiconductor substrate 200, it is described to raise source region 213 and raise drain region 212 and be located at semiconductor substrate On 200 surfaces so that foreign ion control is being raised source region 213 and raised in drain region 212, when preventing the source region to be formed and drain region The foreign ion of doping is spread relatively deep in semiconductor substrate 200, and increases the contact area of source region and drain region and channel region.

The present invention also provides a kind of transistors, referring to FIG. 9, including：

Semiconductor substrate 200, the semiconductor substrate 200 include adjacent first area 11, second area 12 and the Three regions 13, second area 12 and third region 13 are located at the both sides of first area 11；

Well region 203 in the semiconductor substrate 200 of first area 11, second area 12 and third region 12；

The first doped region 206 in 203 surface of well region in first area 11, first doped region 206 are mixed Miscellany type is identical as the doping type of well region 203；

Gate structure in the semiconductor substrate 200 of the first area 11, the gate structure cover the firstth area The first doped region 206 in domain 11；

Shallow doping source region 211 in the semiconductor substrate 200 of the second area 12 of gate structure side is located at grid Shallow doped drain 210 in the semiconductor substrate 200 in the third region 13 of the structure other side；

Source region 213 is raised on shallow doping source region 211, raises in source region 213 doped with foreign ion, raises source region 213 top surface is higher than the surface of semiconductor substrate 200, described to raise source region 213 and the composition transistor of shallow doping source region 211 Source region；

Drain region 212 is raised on shallow doped drain 210, raises in drain region 212 doped with foreign ion, raises drain region 212 top surface is higher than the surface of semiconductor substrate 200, described to raise drain region 212 and the composition transistor of shallow doped drain 210 Drain region.

Specifically, the gate structure includes the gate dielectric layer 207 being located in semiconductor substrate 200, gate dielectric layer 207 covers The surface of the first doped region of lid 206, the gate electrode 208 on gate dielectric layer 207.

Also there is side wall 209 on the both sides side wall of gate structure

The depth of first doped region 206 is 30~200nm, and foreign ion is a concentration of in the first doped region 206 1E17~5E18atom/cm³。

The doping type of the shallow doping source region 211 and the doping type of shallow doped drain 210 and well region 203 is on the contrary, institute The depth of shallow doping source region 211 and shallow doped drain 210 is stated for 15~50nm, in shallow doping source region 211 and shallow doped drain 210 Concentration impurity ion is 3E18~3E20atom/cm³。

It raises source region 213 and raises mixing for the doping type in drain region 212 and shallow doping source region 211 and shallow doped drain 210 Miscellany type is identical, and the thickness raised source region 213 and raise drain region 212 is 30~100nm, raises source region 213 and raises leakage Concentration impurity ion in area 212 is 1E20~5E20atom/cm³。

The material raised source region 213 and raise drain region 212 is polysilicon, SiGe or silicon carbide.

In one embodiment, the doping type of the well region 213 and the first doped region 206 is p-type, the shallow doping source region 211, shallow doped drain 210, the doping type raised source region 213 and raise drain region 212 are N-type.

In another embodiment, the doping type of the well region 213 and the first doped region 206 is N-type, the shallow doped source Area 211, shallow doped drain 210, the doping type raising source region 213 and raise drain region 212 are p-type.

The gate structure covers first doped region 206, and the both sides side wall of the gate structure is mixed beyond first The edges at two ends in miscellaneous area, gate structure side side wall beyond the first doped region corresponding end margin distance be 1~ 100nm。

It should be noted that other about above-mentioned transistor limit and description, the formation of aforementioned transistor is please referred to The definitions relevant of journey part and description, details are not described herein.

Referring to FIG. 10, provide semiconductor substrate 200, the semiconductor substrate 200 include adjacent first area 11, Second area 12 and third region 13, second area 12 and third region 13 are located at the both sides of first area 11；Carry out trap Area's ion implanting forms well region in the semiconductor substrate 200 of the first area 11, second area 12 and third region 13 203；Mask layer 204 is formed on 200 surface of the semiconductor substrate, has in the mask layer 204 and exposes first area 11 With second opening 205 on 200 surface of semiconductor substrate of second area 12.

By the study found that parasitic capacitance between source region and channel region, the parasitism between drain region and channel region Capacitance is to influence to the switching rate of transistor and the influence bigger of switching loss, i.e. parasitic capacitance between drain region and channel region The switching rate of transistor and the most important parasitic capacitance of switching loss.

Carry out having in the mask layer formed the in previous embodiment on a semiconductor substrate before channel region ion implanting One opening, the first opening only expose the semiconductor substrate surface of first area, but due to the continuous reduction of channel region dimensions And the continuous improvement of the integrated level of transistor so that the size of first area also can constantly reduce, and require first to open accordingly The size of mouth also can constantly reduce, but due to the limitation of manufacture craft, it is higher and with a smaller size to be hardly formed precision First opening can have deviation along the position that the first opening carries out channel region ion implanting, affect the performance of transistor.

In the present embodiment, the second opening 205 formed in mask layer 204 exposes first area 11 and second area 12 200 surface of semiconductor substrate, therefore process window when the second opening 205 of formation increases so that 205 tool of the second opening of formation There is higher positions and dimensions precision, even if subsequently carry out channel region ion implanting, the semiconductor substrate 200 of first area 11 In can also inject part foreign ion so that the parasitic capacitance between the source region being subsequently formed and channel region can become larger, but by Parasitic capacitance between source region and channel region is smaller on the switching rate of transistor and switching loss influence, the parasitic capacitance Increase and the switching rate of transistor and switching loss influence can be ignored.

Therefore the method for the present embodiment, ever-reduced in characteristic size, second formed in mask layer 204 opens Mouth 205 has higher positions and dimensions precision, subsequently carries out channel region ion implanting formation along the second opening 205 accordingly The positions and dimensions precision of first doped region is also higher, and since mask layer 204 covers the semiconductor substrate in third region 13 Surface, therefore when carrying out channel region ion implanting, in the well region 203 in third region 13 will not by implanting impurity ion, to Reduce the parasitic capacitance between the drain region being subsequently formed and channel region.

After forming mask layer 204 it is mask with the mask layer 204 with reference to figure 11, along the second 205 pair first of opening The semiconductor substrate 200 in region 11 carries out channel region ion implanting, 203 surface of well region in first area 11 and second area 12 The first doped region 206 of interior formation, the doping type of first doped region 206 are identical as the doping type of well region 203.

In the present embodiment, edge and the 11 edge weight of first area in the close third region of the first doped region 206 of formation It closes.

In other embodiments of the invention, the edge in the close third region of first doped region and first area Edge close to third region does not contact, i.e. the edge of an end margin of the first doped region and the close third region of first area With a certain distance.

Channel region ion implanting relevant parameter and restriction please refer to previous embodiment, and details are not described herein.

With reference to figure 12, gate structure is formed in the semiconductor substrate 200 of the first area 11, the gate structure covers The first doped region 206 in lid first area 11.

It is also formed with side wall 209 on the side wall of the gate structure both sides.

In other embodiments of the invention, when the close third region for the first doped region and first area being previously formed Edge when not contacting, the first doped region of the gate structure covering first area of formation, and the gate structure close to the One end margin in close third region of the side side wall in three regions beyond the first doped region so that the first doped region of formation leans on The edge in nearly third region and the shallow doped drain subsequently formed in the semiconductor substrate in the third region of gate structure side It does not contact, so that the PN junction that the first doped region will not be formed between shallow doped drain and semiconductor substrate contacts, reduces The Doped ions concentration of PN junction between shallow doped drain and semiconductor substrate is conducive to reduce drain region and be led with channel region and partly Parasitic capacitance between body substrate improves the switching rate of transistor.

The one of close third region of the side side wall in the close third region of the gate structure beyond the first doped region The distance of end margin is that 1~100nm makes the first doped region while effective adjusting threshold voltage, effectively has reduction to leak Parasitic capacitance between area and channel region and semiconductor substrate.

With reference to figure 13, shallow Doped ions injection is carried out, in the semiconductor substrate 200 of the second area 12 of gate structure side It is interior to form shallow doping source region 211, shallow doped drain is formed in the semiconductor substrate 200 in the third region 13 of the gate structure other side Area 210.

Shallow doping source region 211 and the doping type of shallow doped drain 210 are opposite with the doping type of well region.In an embodiment In, when the transistor being subsequently formed is the transistor of N-type, the doping type of well region 203 is p-type, the shallow doping source region 211 Doping type with shallow doped drain 210 is also p-type.In another embodiment, when the crystal that the transistor being subsequently formed is p-type Guan Shi, the doping type of well region 203 are N-type, and the doping type of the shallow doping source region 211 and shallow doped drain 210 is also N Type.

Relevant parameter is injected about shallow Doped ions and restriction please refers to previous embodiment, and details are not described herein.

With reference to figure 14, formed on shallow doping source region 211 and raise source region 213, raise in source region 213 doped with impurity from Son, the top surface for raising source region 213 is higher than the surface of semiconductor substrate 200, described to raise source region 213 and shallow doping source region 211 constitute the source region of transistor；It is formed on shallow doped drain 210 and raises drain region 212, raised in drain region 212 doped with impurity Ion, the top surface for raising drain region 212 is higher than the surface of semiconductor substrate 200, described to raise drain region 212 and shallow doped drain 210 constitute the drain region of transistor.

It should be noted that in the present embodiment about in transistor forming process other limit or description please refer to it is aforementioned Corresponding restriction in embodiment transistor forming process or description, details are not described herein.

The present invention also provides a kind of transistor, 4 are please referred to Fig.1, including：

The first doped region 206 in 203 surface of well region in first area 11 and second area 12, described first mixes The doping type in miscellaneous area 206 is identical as the doping type of well region 203；

Gate structure in the semiconductor substrate 200 of the first area 11, the gate structure cover the firstth area The first doped region 206 in domain 11, the gate structure include the gate dielectric layer 207 being located in semiconductor substrate 200, gate medium Layer 207 covers the surfaces of the first doped regions 206, the gate electrode 208 on gate dielectric layer 207 and is located at gate dielectric layer 207 With the side wall 209 on 208 side wall of gate electrode；

In one embodiment, the first doped region of gate structure covering first area, the close third of gate structure One end margin in close third region of the side side wall in region beyond the first doped region and the close third of the gate structure One end margin in close third region of the side side wall in region beyond the first doped region, the close third area of the gate structure The distance of one end margin in close third region of the side side wall in domain beyond the first doped region is 1~100nm.

It should be noted that other restrictions or description in the present embodiment about transistor arrangement please refer to previous embodiment Corresponding restriction in transistor forming process or description, details are not described herein.

To sum up, the Transistor forming method of the embodiment of the present invention, in the first area, second area and third region After forming well region in semiconductor substrate, channel region ion implanting is then carried out, in first area or first area and second area In well region surface in formed the first doped region, with adjust formed transistor threshold voltage, carry out channel region ion implanting When, the object of channel region ion implanting injection is the well region of first area (or first area and second area), second area Will not be by implanting impurity ion with the well region surface in third region (or third region), therefore the source region of second area and third area The concentration impurity ion in the drain region in domain compared with the existing technology the concentration impurity ion in the source region of transistor and drain region reduce (or The concentration impurity ion in the drain region in third region compared with the existing technology the drain region of transistor concentration impurity ion reduce), from And the parasitic capacitance between the parasitic capacitance between channel region and drain region and source region (or channel region and drain region) is reduced, it improves The switching rate of transistor.In addition, the drain region that the present invention is formed includes raising drain region and shallow doped drain, source region includes described Raise source region and shallow doping source region, reduce between drain region and source region and channel region and drain region and source region and semiconductor substrate it Between contact area, to reduce between drain region and source region and channel region and between drain region and source region and semiconductor substrate The size of parasitic capacitance.

The transistor of the embodiment of the present invention, first doped region are only located in the well region of first area (or the firstth area Domain and second area) well region in, the concentration impurity ion for reducing second area and third region (or reduces third area The concentration impurity ion in domain), to reduce the parasitic capacitance between channel region and drain region and source region (or channel region and leakage Area) between parasitic capacitance, improve the switching rate of transistor.In addition, drain region includes raising drain region and shallow doped drain, source Area include it is described raise source region and shallow doping source region, shallow doping source region and shallow doped drain are located in well region, shallow doping source region with The depth of shallow doped drain can be very shallow, raises source region and is located in the semiconductor substrate of second area, raises drain region and is located at third In the semiconductor substrate in region, thus reduce the contact area of drain region and channel region, to reduce drain region and channel region it Between parasitic capacitance size.

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims

1. a kind of forming method of transistor, which is characterized in that including：

Semiconductor substrate is provided, the semiconductor substrate includes adjacent first area, second area and third region, and second Region and third region are located at the both sides of first area；

Well region ion implanting is carried out, well region is formed in the semiconductor substrate of the first area, second area and third region；

Channel region ion implanting is carried out, only the first doped region of formation in well region surface in the first region, second area and the It will not be by implanting impurity ion, the doping type of the doping type and well region of first doped region in the well region surface in three regions It is identical；

Gate structure is formed in the semiconductor substrate of the first area, the gate structure covers first in first area Doped region；

Shallow Doped ions injection is carried out, forms shallow doping source region in the semiconductor substrate of the second area of gate structure side, Shallow doped drain, the shallow doping source region and shallow doping are formed in the semiconductor substrate in the third region of the gate structure other side The doping type in drain region is opposite with the doping type of well region；

It is formed on shallow doping source region and raises source region, raised doped with foreign ion in source region, the top surface for raising source region is high It is described to raise source region and shallow doping source region composition source region in the surface of semiconductor substrate, it is formed on shallow doped drain and raises leakage Area is raised doped with foreign ion in drain region, and the top surface for raising drain region is higher than the surface of semiconductor substrate, described to raise leakage Area and shallow doped drain constitute drain region.

2. the forming method of transistor as described in claim 1, which is characterized in that before carrying out channel region ion implanting, The semiconductor substrate surface forms mask layer, has the semiconductor substrate surface for exposing first area in the mask layer First opening；After forming mask layer, using the mask layer as mask, along the first opening to the semiconductor substrate of first area into Row channel region ion implanting forms the first doped region in the well region surface of first area.

3. the forming method of transistor as described in claim 1, which is characterized in that the gate structure covering described first is mixed Miscellaneous area, and the both sides side wall of the gate structure exceeds the edges at two ends of the first doped region.

4. the forming method of transistor as claimed in claim 3, which is characterized in that gate structure side side wall is beyond the The distance of the corresponding end margin of one doped region is 1~100nm.

5. the forming method of transistor as described in claim 1, which is characterized in that the transistor of formation is NMOS transistor When, the doping type of the well region and the first doped region is p-type, and the shallow doping source region, raises source region and lift at shallow doped drain The doping type in high drain region is N-type, and the p type impurity ion of the channel region ion implanting injection is boron ion or indium ion, note The dosage range for entering foreign ion is 1E12~4E13atom/cm², implant angle is 0~20 degree, injects energy when boron ion Ranging from 4~30Kev, energy range when injecting indium ion are 30~300Kev；The N-type impurity of the shallow Doped ions injection Ion be one or both of phosphonium ion or arsenic ion, inject arsenic ion when energy be 3~60Kev, dosage be 3E13~ 2E15atom/cm², implant angle be 0~45 degree, inject phosphonium ion when energy be 3~80Kev, dosage for 2E13~ 5E14atom/cm², implant angle is 0~45 degree.

6. the forming method of transistor as described in claim 1, which is characterized in that the transistor of formation is PMOS transistor When, the doping type of the well region and the first doped region is N-type, and the shallow doping source region, raises source region and lift at shallow doped drain The doping type in high drain region is p-type, and the N-type impurity ion of the channel region ion implanting injection is phosphonium ion or arsenic ion, note The dosage range for entering foreign ion is 1E12~4E13atom/cm², implant angle is 0~20 degree, injects energy when boron ion Ranging from 10~70Kev, energy range when injecting arsenic ion are 20~140Kev；The p-type of the shallow Doped ions injection is miscellaneous Matter ion is one or both of boron ion or indium ion, and energy when injecting boron ion is 3~30Kev, dosage 3E13 ~2E15atom/cm², implant angle be 0~45 degree, inject indium ion when energy be 20~80Kev, dosage for 1E13~ 5E13atom/cm², implant angle is 0~45 degree.

7. the forming method of transistor as described in claim 1, which is characterized in that raise source region and raise the doping class in drain region Type is identical as the doping type of shallow doping source region and shallow doped drain, it is described raise source region and raise drain region thickness be 30~ 100nm, the foreign ion activation concentration raised source region and raised in drain region is 1E20~5E20atom/cm³。

8. the forming method of transistor as described in claim 1, which is characterized in that described to raise source region and raise drain region and formed Technique is doping selective epitaxial process in situ.

9. the forming method of transistor as described in claim 1, which is characterized in that the shape raised source region and raise drain region It is at technique：The first epitaxial layer is formed on the shallow doping source region；The second epitaxial layer is formed on the shallow doped drain；Into The first ion implanting of row, in the first epitaxial layer impurity ion, source region is raised in formation, in the second epitaxial layer impurity from Drain region is raised in son, formation, wherein when the first ion implanting injects N-type impurity ion, N-type impurity ion includes phosphonium ion, injection Energy be 4~12Kev, implantation dosage be 2E15~2E16atom/cm², the first ion implanting implanting p-type foreign ion, p-type Foreign ion includes boron ion, and the energy of injection is 2~8Kev, and implantation dosage is 2E15~2E16atom/cm²。

10. a kind of forming method of transistor, which is characterized in that including：

Channel region ion implanting is carried out, only forms the first doped region in the well region surface in first area and second area, the It will not be by implanting impurity ion, the doping type of the doping type and well region of first doped region in the well region surface in three regions It is identical；

11. the forming method of transistor as claimed in claim 10, which is characterized in that before carrying out channel region ion implanting, Mask layer is formed in the semiconductor substrate surface, has in the mask layer and exposes partly leading for first area and second area Second opening of body substrate；After forming mask layer, using the mask layer as mask, along the second opening to first area and second The semiconductor substrate in region carries out channel region ion implanting, forms first in first area and the well region surface of second area and mixes Miscellaneous area.

12. the forming method of transistor as claimed in claim 10, which is characterized in that gate structure covers the of first area One doped region, and close third region of the side side wall in the close third region of the gate structure beyond the first doped region One end margin.

13. the forming method of transistor as claimed in claim 12, which is characterized in that the close third area of the gate structure The distance of one end margin in close third region of the side side wall in domain beyond the first doped region is 1~100nm.

14. a kind of transistor, which is characterized in that including：

Semiconductor substrate, the semiconductor substrate include adjacent first area, second area and third region, second area The both sides of first area are located at third region；

Well region in the semiconductor substrate of first area, second area and third region；

The first doped region being only positioned in the well region surface in first area, the doping type of first doped region and well region Doping type is identical；

Gate structure in the semiconductor substrate of the first area, the gate structure cover first in first area Doped region；

Shallow doping source region in the semiconductor substrate of the second area of gate structure side is located at the gate structure other side Shallow doped drain in the semiconductor substrate in third region, the doping type and well region of the shallow doping source region and shallow doped drain Doping type it is opposite；

Source region is raised on shallow doping source region, is raised doped with foreign ion in source region, the top surface for raising source region is high It is described to raise source region and shallow doping source region composition source region in the surface of semiconductor substrate；

Drain region is raised on shallow doped drain, is raised doped with foreign ion in drain region, the top surface for raising drain region is high It is described to raise drain region and shallow doped drain composition drain region in the surface of semiconductor substrate.

15. transistor as claimed in claim 14, which is characterized in that the depth of first doped region is 30~200nm, the A concentration of 1E17~5E18atom/cm of foreign ion in one doped region³。

16. transistor as claimed in claim 14, which is characterized in that the doping class of the shallow doping source region and shallow doped drain The doping type of type and well region on the contrary, the depth of the shallow doping source region and shallow doped drain be 15~50nm, shallow doping source region It is 3E18~3E20atom/cm with concentration impurity ion in shallow doped drain³；Raise source region and raise the doping type in drain region with Shallow doping source region is identical with the doping type of shallow doped drain, and the thickness raised source region and raise drain region is 30~100nm, The concentration impurity ion raised source region and raised in drain region is 1E20~5E20atom/cm³。

17. transistor as claimed in claim 14, which is characterized in that when the transistor is NMOS transistor, the trap The doping type of area and the first doped region is p-type, and the shallow doping source region, raises source region and raises drain region at shallow doped drain Doping type is N-type；When the transistor is PMOS transistor, the doping type of the well region and the first doped region is N-type, The shallow doping source region, shallow doped drain raise source region and raise the doping type in drain region as p-type.

18. transistor as claimed in claim 14, which is characterized in that the gate structure covers first doped region, and The both sides side wall of the gate structure exceeds the edges at two ends of the first doped region.

19. a kind of transistor, which is characterized in that including：

The first doped region being only positioned in the well region surface in first area and second area, the doping class of first doped region Type is identical as the doping type of well region；

20. transistor as claimed in claim 19, which is characterized in that gate structure covers the first doped region of first area, An and end margin in close third region of the side side wall in the close third region of the gate structure beyond the first doped region.