CN106206719A - Mos transistor and forming method thereof - Google Patents
Mos transistor and forming method thereof Download PDFInfo
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- CN106206719A CN106206719A CN201510224853.8A CN201510224853A CN106206719A CN 106206719 A CN106206719 A CN 106206719A CN 201510224853 A CN201510224853 A CN 201510224853A CN 106206719 A CN106206719 A CN 106206719A
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Abstract
A kind of MOS transistor and forming method thereof, the forming method of MOS transistor includes: providing Semiconductor substrate, described semiconductor substrate surface has grid structure, and described grid structure both sides have offset side wall；The Semiconductor substrate of described grid structure both sides is carried out lightly doped drain injection, is formed and district is lightly doped；At formation gap, described offset side wall surface side wall；Semiconductor substrate in described grid structure both sides forms source-drain area；On formation barrier layer, described source-drain area surface, described barrier layer is used for stopping source-drain area described in ion implanting；Use etching technics to remove described offset side wall and gap side wall forms opening；The Semiconductor substrate exposing described opening carries out the first halo and injects formation the first halo region.The forming method of described MOS transistor, can improve MOS transistor performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of MOS transistor and forming method thereof.
Background technology
MOS (Metal-oxide-semicondutor) transistor, be in modern integrated circuits most important element it
One, the basic structure of MOS transistor includes: Semiconductor substrate；It is positioned at the grid of semiconductor substrate surface
Structure, described grid structure includes: is positioned at the gate dielectric layer of semiconductor substrate surface and is positioned at gate medium
The gate electrode layer on layer surface；Be positioned in grid structure semiconductor substrates on two sides is lightly doped district and is positioned at grid
Source-drain area in structure semiconductor substrates on two sides.
The method forming described MOS transistor is: provide Semiconductor substrate, at described Semiconductor substrate table
Face forms grid structure, and described grid structure includes gate dielectric layer and the grid being positioned at semiconductor substrate surface
The gate electrode layer of dielectric layer surface；Offset side wall is formed, to offset side on described gate structure sidewall surface
Wall and grid structure are mask, and the Semiconductor substrate of grid structure both sides is carried out lightly doped drain (Lightly
Doped Drain, LDD) inject, formed and district is lightly doped；At formation gap, offset side wall surface side wall；
With grid structure, offset side wall and gap side wall as mask, the Semiconductor substrate of grid structure both sides is entered
Row source-drain area injection technology, forms source-drain area.
Along with characteristic size reduces further, the Performance And Reliability of the MOS transistor that prior art is formed
Poor.
Summary of the invention
The problem that the present invention solves is to provide a kind of MOS transistor and forming method thereof, improves MOS brilliant
The performance of body pipe.
For solving the problems referred to above, the present invention provides the forming method of a kind of MOS transistor, including: provide
Semiconductor substrate, described semiconductor substrate surface has grid structure, and described grid structure both sides have partially
Move side wall；The Semiconductor substrate of described grid structure both sides is carried out lightly doped drain injection, and formation is lightly doped
District；At formation gap, described offset side wall surface side wall；Semiconductor substrate in described grid structure both sides
Form source-drain area；On formation barrier layer, described source-drain area surface, described barrier layer is used for stopping ion implanting
Source-drain area；Use etching technics to remove described offset side wall and gap side wall forms opening；To described opening
The Semiconductor substrate exposed carries out the first halo and injects formation the first halo region.
Further, the angle that described first halo injects is 0 degree～10 degree.
Optionally, the direction that described first halo injects is perpendicular to described Semiconductor substrate.
Optionally, longitudinal degree of depth of described first halo region is at least above described longitudinal degree of depth that district is lightly doped.
Optionally, longitudinal degree of depth of described first halo region is 10nm～50nm.
During removing described offset side wall and described gap side wall formation opening, described etching technics
The etch rate of described offset side wall and described gap side wall is more than described etching technics to described barrier layer
Etch rate.
Optionally, in the mistake that described offset side wall and described gap side wall are carried out described etching formation opening
Cheng Zhong, the etching selection ratio on described offset side wall and described barrier layer is 4:1～10:1, described gap side wall and
The etching selection ratio on described barrier layer is 4:1～10:1.
Optionally, it is silicon nitride that described etching technics etches the material of described offset side wall and gap side wall,
It is silicon oxide that described etching technics etches the material on described barrier layer.
Optionally, the thickness on described barrier layer is 50nm～100nm.
Further, also include: before or after described lightly doped drain injects, with described offset side wall
For mask the Semiconductor substrate of described grid structure both sides carried out the second halo inject formed surround described gently
The second areola ring region of doped region.
Optionally, the ion energy that described second halo injects is 20KeV～40KeV, and dosage is
1E13tom/cm2～5E13tom/cm2, ion implantation angle is 20 degree～35 degree.
Optionally, when transistor to be formed is PMOS, described first halo injects and described the
The ion that two halos inject is N-type ion.
When transistor to be formed is NMOS tube, described first halo injects and described second halo note
The ion entered is p-type ion.
Optionally, it is arsenic ion that described first halo injects the ion used, and ion implantation energy is
25KeV～50KeV, ion implantation dosage is 1E13tom/cm2～1E14atom/cm2。
Optionally, it is phosphonium ion that described first halo injects the ion used, and ion implantation energy is
2KeV～5KeV, ion implantation dosage is 1E13tom/cm2～1E14atom/cm2。
Optionally, it is boron ion that described first halo injects the ion used, and ion implantation energy is
5KeV～10KeV, ion implantation dosage is 1E13tom/cm2～1E14atom/cm2。
Optionally, it is boron difluoride ion that described first halo injects the ion used, ion implantation energy
For 25KeV～50KeV, ion implantation dosage is 1E13tom/cm2～1E14atom/cm2。
Present invention also offers a kind of MOS transistor using any of the above-described method to be formed, including: half
Conductor substrate, described semiconductor substrate surface has grid structure；It is positioned at described grid structure both sides partly to lead
Source-drain area in body substrate；It is positioned at the barrier layer on described source-drain area surface；It is positioned at described barrier layer and described
Opening between grid structure；It is positioned at Semiconductor substrate corresponding with described opening that described opening exposes
The first halo region；It is positioned at the district that is lightly doped of described grid structure semiconductor substrates on two sides, described first
The sidewall in district is lightly doped described in the encirclement of halo region.
Optionally, also include: be positioned at the second halo that district is lightly doped described in the encirclement of described grid structure both sides
District, the lateral depth of described second areola ring region is less than the lateral depth of described first halo region.
The invention have the advantages that
Formed open owing to etching away described offset side wall and described gap side wall before injecting at the first halo
Mouthful, the Semiconductor substrate then exposed described opening carries out the first halo and injects formation the first halo region,
Described first halo injects and will not be stopped by described offset side wall and described gap side wall, thus described
First halo region enters the lateral dimension of grid structure underlying channel region to be increased, described first halo region pair
The inhibitory action of the punchthrough effect that district and source-drain area are lightly doped strengthens.On the other hand, the first halo is being carried out
In injection process, due to the stop on barrier layer, the ion that described first halo injects will not enter described resistance
Source-drain area corresponding below barrier, the PN junction bottom described source-drain area is mixing near Semiconductor substrate side
Heteroion concentration largely reduces, and reduces the junction capacity of source-drain area, reduces MOS transistor
Leakage current.The i.e. forming method of the MOS transistor that the present invention provides, it is possible to simultaneously effectively reduce knot electricity
Hold and punchthrough effect, thus improve the performance of MOS transistor.
Further, described first halo injects and uses the direction being perpendicular to Semiconductor substrate to carry out, and simplifies
Control to angle in described first halo injection process；It addition, it is certain at implantation dosage and energy
Under the conditions of, use the direction being perpendicular to Semiconductor substrate to carry out the first halo injection, injection can be increased
The degree of depth, adds longitudinal degree of depth of described first halo region, it is possible to effectively suppress punchthrough effect.
Further, inject before or after formation is lightly doped district, with skew carrying out described lightly doped drain
Side wall is that mask has carried out the second halo injection to Semiconductor substrate, defines and district is lightly doped described in encirclement
Second areola ring region.Described second halo injects and can suppress hot carrier injection effect further and puncture effect
Should, improve the performance of device.Further, since the first halo region surrounds the longitudinal side wall and extremely that district is lightly doped
The longitudinal side wall of small part source-drain area, and the lateral dimension of the first halo region entrance grid structure bottom channel
Increase, so the concentration that need not inject by improving described second areola ring region forms heavily doped second areola
Ring region, to increase the area of described second areola ring region, can carry out low concentration in described second areola ring region
Ion doping.Use low concentration second areola ring region can reduce the junction capacity of MOS transistor.
The forming method of MOS transistor that i.e. present invention provides, it is possible to effectively reduce simultaneously junction capacity and
Punchthrough effect, thus improve the performance of MOS transistor.
In the MOS transistor that the present invention provides, have out between described barrier layer and described grid structure
Mouthful, there is in the Semiconductor substrate that described opening exposes first halo region corresponding with described opening, institute
State the first halo region and surround the sidewall that district is lightly doped in described grid structure semiconductor substrates on two sides, and institute
State first halo region lateral dimension in grid structure underlying channel region relatively big, described first halo region pair
The inhibitory action of the punchthrough effect that district and source-drain area are lightly doped strengthens.It addition, there is resistance on source-drain area surface
Barrier, described first halo region prevents take up the region of source-drain area corresponding below described barrier layer, described source
PN junction bottom drain region largely reduces in the dopant ion concentration near Semiconductor substrate side, source
The junction capacity in drain region reduces, and the leakage current of MOS transistor reduces.
Further, described MOS transistor also has and is positioned at described grid structure both sides and surrounds and described gently mix
The second areola ring region in miscellaneous district, the lateral depth of described second areola ring region is horizontal less than described first halo region
The degree of depth.Described second areola ring region can suppress hot carrier injection effect and punch-through effect further, improves
The performance of MOS transistor.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the cross-section structure signal of the forming process of one embodiment of the invention MOS transistor
Figure；
Fig. 5 to Figure 12 is the structural representation of the forming process of MOS transistor in another embodiment of the present invention
Figure；
Figure 13 and Figure 16 is the structural representation of the forming process of MOS transistor in further embodiment of this invention
Figure.
Detailed description of the invention
Prior art formed MOS transistor along with characteristic size reduce further time, the performance of transistor
Poor with reliability.
Fig. 1 to Fig. 4 is the cross-section structure signal of the forming process of one embodiment of the invention MOS transistor
Figure.
With reference to Fig. 1, it is provided that Semiconductor substrate 100, form grid knot on described Semiconductor substrate 100 surface
Structure 110, gate dielectric layer 111 that described grid structure 110 includes being positioned at Semiconductor substrate 100 surface and
The gate electrode layer 112 on gate dielectric layer 111 surface.
With reference to Fig. 2, form offset side wall 121 in described grid structure 110 sidewall surfaces, with described skew
Side wall 121 and grid structure 110 are mask, enter the Semiconductor substrate 100 of grid structure 110 both sides
Row lightly doped drain (Lightly Doped Drain, LDD) injects, and is formed and district 130 is lightly doped.
Please remain unchanged with reference to Fig. 2, with described offset side wall 121 and grid structure 110 as mask, grid be tied
The Semiconductor substrate 100 of structure 110 both sides carries out halo injection, is formed and district 130 dizzy is lightly doped described in surrounding
Ring region 131.Described halo is infused in before or after described lightly doped drain injects and carries out.
The effect that described halo injects is that (depletion layer of punch though, i.e. source and drain is even for preventing break-through
Logical) and short-channel effect (SCE).
When MOS transistor to be formed is N-type transistor, the ionic type that described lightly doped drain injects
For N-type, the ionic type that described halo injects is p-type, when MOS transistor to be formed is p-type
During transistor, the ionic type that described lightly doped drain injects is p-type, the ionic type that described halo injects
For N-type.
Refer to Fig. 3, at formation gap, offset side wall 121 surface side wall 122, with grid structure 110,
Offset side wall 121 and gap side wall 122 are mask, the Semiconductor substrate 100 to grid structure 110 both sides
Carry out source-drain area injection technology, form source-drain area 140.
In order to effectively play the effect of described halo region, need to increase dosage and the energy that described halo injects,
So that described halo region enlarged area (with reference to Fig. 4) in subsequent anneal, increase and surround described source-drain area
With the described area that district is lightly doped, thus improve described source-drain area and the described horizontal suppression that district is lightly doped
Effect.
It addition, with reference to Fig. 4, during MOS transistor is formed, the dopant ion of source-drain area 140
Kind is different from the conduction type of the dopant well of MOS transistor, and the doping ionic species of halo region 131
Identical with the conduction type of MOS transistor, therefore, can shape between source-drain area 140 and halo region 131
Become PN junction, thus form parasitic load capacitance (i.e. junction capacity), hereon referred to as the first junction capacity；With
Time, the doping ionic species that lightly doped drain injects is different from the conduction type of the dopant well of MOS transistor,
The second junction capacity can be formed being lightly doped between district 130 and halo region 131.Owing to the first junction capacity is long-range
In the second junction capacity, so the size of the first junction capacity mainly affects the junction capacity of described MOS transistor
Size.The performance of MOS transistor is had a major impact by junction capacity, reduces MOS transistor junction capacity energy
Enough reduce junction leakage.
In order to effectively reduce MOS transistor junction capacity, it is desirable to reduce described first junction capacity to greatest extent
The dopant ion concentration on both sides, can be by regulating ion concentration and the energy that described halo injects, as subtracted
The dopant ion concentration of little halo region 131 and reduction ion implantation energy, but this can reduce again halo region
131 surround source-drain area 140 and the area in district 130 are lightly doped, thus reduce halo region 131 to being lightly doped
District 130 and the suppression of source-drain area 140 punchthrough effect.
The reason of visible above-mentioned MOS transistor poor performance be to effectively reduce simultaneously junction capacity and
Punchthrough effect.
The invention provides the forming method of the MOS transistor of another embodiment, it is provided that Semiconductor substrate,
Described semiconductor substrate surface has grid structure, and described grid structure both sides have offset side wall；To institute
The Semiconductor substrate stating grid structure both sides carries out lightly doped drain injection, is formed and district is lightly doped；Described partially
Move formation gap, side wall surface side wall；Source-drain area is formed in the Semiconductor substrate of described grid structure both sides；
On formation barrier layer, described source-drain area surface, described barrier layer is used for stopping that ion implanting arrives source-drain area；Adopt
Remove described offset side wall with etching technics and described gap side wall forms opening；Described opening is exposed
Semiconductor substrate carries out the first halo and injects formation the first halo region.
On the one hand, described first halo injects and will not be hindered by described offset side wall and described gap side wall
Gear, so the lateral dimension that described first halo region enters grid structure underlying channel region increases, first
The inhibitory action of the halo region punchthrough effect to district and source-drain area are lightly doped strengthens.
On the other hand, in carrying out the first halo injection process, due to the stop on barrier layer, described first
The ion that halo injects will not enter source-drain area corresponding below described barrier layer, bottom described source-drain area
PN junction largely reduces in the dopant ion concentration near Semiconductor substrate side, reduces source-drain area
Junction capacity, reduce the leakage current of MOS transistor.
Elaborate a lot of detail in the following description so that fully understanding the present invention.But this
Bright can implement to be much different from the alternate manner of description in this, those skilled in the art can be
Doing similar popularization in the case of intension of the present invention, therefore the present invention is not by following public concrete reality
The restriction executed.Secondly, the present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail,
For convenience of description, described schematic diagram is example, and it the most should not limit the scope of protection of the invention.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Refer to Fig. 5, it is provided that Semiconductor substrate 200, described Semiconductor substrate 200 surface has grid knot
Structure 210, described grid structure both sides have offset side wall 220.
Described Semiconductor substrate 200 can be monocrystal silicon, polysilicon or non-crystalline silicon；Described Semiconductor substrate
200 can also be the semi-conducting materials such as silicon, germanium, SiGe, GaAs；Described Semiconductor substrate 200 can
Be body material can also be composite construction such as silicon-on-insulator；Described Semiconductor substrate 200 can also is that
Other semi-conducting material, illustrates the most one by one.In the present embodiment, described Semiconductor substrate 200
Material is silicon.
Described grid structure 210 includes gate dielectric layer 211, the gate electrode being positioned on described gate dielectric layer 211
Layer 212.
In the present embodiment, the material of described gate dielectric layer 211 is silicon oxide, the material of described gate electrode layer 212
Material is polysilicon.In other embodiments, described gate dielectric layer 211 and described gate electrode layer 212 are constituted
Dummy grid, in rear grid technique, removes dummy gate pole, forms high-k in original dummy grid position
Gate dielectric layer and metal gates, form high K (K is more than 3.9) metal gate structure, be conducive to improving crystalline substance
The breakdown voltage of body pipe, reduces leakage current, improves transistor performance.
The method forming described grid structure 210 is: deposit gate medium in described Semiconductor substrate 200
Material layer and layer of gate electrode material, the mask layer graphically changed is that mask is to described gate dielectric material layer and grid
Electrode material layer etching forms grid structure, the position of described patterned mask layer definition grid structure 210
Put.In the present embodiment, using plasma strengthens gate dielectric material layer described in chemical gaseous phase formation of deposits,
Use layer of gate electrode material described in low-pressure chemical vapor deposition.
Grid structure 210 surface can form hard mask layer (not shown), and described hard mask layer can be rear
Continuous technique protects grid structure 210.
In the present embodiment, also include: in Semiconductor substrate 200, form fleet plough groove isolation structure (do not scheme
Show), the active area that the isolation of described fleet plough groove isolation structure is adjacent.
Described Semiconductor substrate 200 can also be adulterated different according to the type of MOS transistor to be formed
Foreign ion, for regulating the threshold voltage of MOS transistor.In the present embodiment, when N-type to be formed
During MOS transistor, Semiconductor substrate 200 doped p-type ion；In other embodiments of the invention,
When N-type MOS transistor to be formed, Semiconductor substrate 200 doped N-type ion.
The mask functioning as the injection of follow-up lightly doped drain of offset side wall 220, protects grid structure 210
Subsequent technique does not sustains damage, and the thickness passing through offset side wall 220 can adjust and be subsequently formed
The distance being lightly doped between district and grid structure 210；Meanwhile, offset side wall 220 is fallen in subsequent etching
During affect the aperture position of formation.
The method forming offset side wall 220 is: use depositing operation to tie in Semiconductor substrate 200 and grid
Depositing offset side wall material layer on structure 210, then using plasma dry etch process etching is described partially
Move spacer material layer and form offset side wall.The depositing operation of described deposition offset side wall material layer is atomic layer
Depositing operation, plasma enhanced chemical vapor deposition, low-pressure chemical vapour deposition technique, ultrahigh vacuum
Chemical vapour deposition technique or high density plasma CVD method.
The material of offset side wall 220 can be silicon nitride, and silicon oxynitride, silicon oxide or low-K material etc. are situated between
Material.Subsequent technique needs perform etching to form opening to described offset side wall 220, in etching
During described offset side wall 220 forms opening, follow-up shape compared by the material of described offset side wall 220
The barrier material on the source-drain area surface become has high etching selection ratio.In the present embodiment, described skew
The material of side wall 220 is silicon nitride.
With reference to Fig. 6, the Semiconductor substrate 200 of grid structure 210 both sides is carried out lightly doped drain injection, shape
Become district 230 is lightly doped.
The described district 230 that is lightly doped, for reducing the transverse electric field intensity of source-drain area, reduces hot carrier's effect.
Wherein, when described MOS transistor is N-type, described lightly doped drain injects and uses N-type
Ion, described N-type ion includes As or P；When described MOS transistor is p-type, described gently mix
Miscellaneous leakage injection uses p-type ion, such as B, In etc..
Described district 230 is lightly doped formation process be: with grid structure 210 and offset side wall 220 for covering
Film, implanting impurity ion in the Semiconductor substrate 200 of grid structure 210 both sides, formed and district is lightly doped
230；The energy of described ion implanting is 1KeV～4KeV, and dosage is
2E14atom/cm2～1E15atom/cm2, injecting angle is 0 degree～10 degree.
In the present embodiment, make annealing treatment after formation is lightly doped district 230, activate dopant ion and
Eliminate implantation defect.In other embodiments, can anneal in the lump after being subsequently formed source-drain area
Process, or make annealing treatment in the lump after being subsequently formed source-drain area and the first halo region.
With reference to Fig. 7, at formation gap, described offset side wall 220 surface side wall 221.
The effect of gap side wall 221 affects formation during subsequent etching falls gap side wall 221
Aperture position, and then define the position of the first halo region being subsequently formed；Meanwhile, gap side wall 221 can
Using the mask as subsequent source drain region ion implanting, protection grid structure 210 does not sustains damage, and leads to
Cross the thickness of gap side wall 221 can adjust between the source-drain area being subsequently formed and grid structure 210 away from
From.
The method forming gap side wall 221 is: use depositing operation to tie in Semiconductor substrate 200 and grid
Depositing the clearance side walling bed of material on structure 210, the etching clearance side walling bed of material forms gap side wall.Described heavy
The depositing operation of the long-pending clearance side walling bed of material is that atom layer deposition process, PECVD sink
Long-pending, low-pressure chemical vapour deposition technique, ultra-high vacuum CVD method or high-density plasma
Learn vapour deposition process.The technique etching the described clearance side walling bed of material is anisotropic etch process, such as
Plasma dry etch.
Subsequent technique needs perform etching to form opening to gap side wall 221, at etching gap side wall
221 are formed during openings, and the material of gap side wall 221 is compared follow-up in grid structure 210 both sides
The barrier material that source-drain area surface is formed has high etching selection ratio.The material of gap side wall 221 can
Think silicon nitride, the dielectric material such as silicon oxynitride or low-K material.In the present embodiment, described gap side wall
The material of 221 is silicon nitride.
Please continue to refer to Fig. 7, the Semiconductor substrate 200 of grid structure 210 both sides forms source-drain area
231。
Wherein, when described MOS transistor is N-type, in source-drain area 231, dopant ion uses N
Type ion, described N-type ion includes As or P；When described MOS transistor is p-type, source-drain area
In 231st district, dopant ion uses p-type ion, such as B, In etc..
The formation process of source-drain area 231 is: with grid structure 210, offset side wall 220 and gap side wall
221 is mask, implanting impurity ion in the Semiconductor substrate 200 of grid structure 210 both sides, forms source
Drain region 231.The technique that source-drain area carries out ion implanting is: the ion dose of injection is
1E13atom/cm2～2E15atom/cm2, implant angle is 0 degree～10 degree.
In other embodiments, embedded source-drain area can be used, concrete, form described embedded source
The process in drain region includes: is formed and covers described grid structure and the mask layer of part semiconductor substrate, described
Mask layer exposes the Semiconductor substrate of described grid structure both sides；With described mask layer as mask, use
Anisotropic dry etch process etches described Semiconductor substrate, forms groove, fills stress in a groove
Material, carries out source-drain area ion implanting in described stress material, forms source-drain area.Described embedded source
Drain region can introduce stress at the channel region of MOS transistor, improves the performance of transistor.
Concrete, when N-type MOS transistor to be formed, described stress material is SiC, described doping
Ion is N-type ion, such as As, P etc.；When N-type MOS transistor to be formed, described in answer dead-wood
Material is SiGe, and described dopant ion is p-type ion, and described p-type ion includes B, In.
In the present embodiment, make annealing treatment being formed after described source-drain area 231, activate dopant ion and
Eliminate implantation defect.In other embodiments, after the first halo region that can continue after its formation, one goes forward side by side
Row annealing.
With reference to Fig. 8, on formation barrier layer, source-drain area 231 surface 240, barrier layer 240 is used for stopping ion
It is injected into source-drain area 231.
Use depositing operation, such as atom layer deposition process, plasma enhanced chemical vapor deposition, low pressure
Power chemical vapour deposition technique, ultra-high vacuum CVD method or high-density plasma chemical gas phase are heavy
Area method, deposit barrier material layer, described barrier material layer covers grid structure 210, gap side wall
221, offset side wall 220, Semiconductor substrate 200, then described barrier material layer is carried out smooth chemical industry
Skill such as mechanical-chemistry grinding, until exposing the top surface of grid structure 210；In other embodiments,
When there is mask layer on described grid structure 210 surface, the described barrier material floor height of formation of deposits is in institute
State mask layer top, more described barrier material layer is planarized until exposing grid structure 210 top
Surface.
Subsequent technique needs perform etching to form opening to gap side wall 221 and offset side wall 220,
During etching gap side wall 221 and offset side wall 220 form opening, the material on barrier layer 240
The material comparing offset side wall 220 and gap side wall 221 has different etching selection ratio, concrete,
The etch rate of offset side wall 220 and gap side wall 221, much larger than the etch rate on barrier layer 240, makes
Described stop must be retained during subsequent etching gap side wall 221 and offset side wall 220 form opening
Layer 240.In the present embodiment, the material on barrier layer 240 is silicon oxide.
Owing to defining barrier layer 240 on source-drain area 231 surface, described barrier layer 240 can stop follow-up
Source-drain area 231, source-drain area 231 and Semiconductor substrate is implanted ions into during the first halo injects
The junction capacity that 200 dopant wells are formed effectively reduces, thus reduces the knot electricity of MOS transistor source-drain area
Hold, reduce junction leakage.
The thickness on described barrier layer 240 is 50nm～100nm.
With reference to Fig. 9, etching technics is used to remove offset side wall 220 (with reference to Fig. 8) and gap side wall 221
(with reference to Fig. 8).
After removing offset side wall 220 and gap side wall 221, forming opening 250, described opening 250 exposes
Go out the semiconductor substrate surface between gap side wall 221 and grid structure 210 and gap side wall 221 He
The sidewall of grid structure 210.
Described etch bias side wall 220 and gap side wall 221 form the technique of opening 250 and include that wet method is carved
Etching technique and dry etch process；Owing to offset side wall 220, gap side wall 221 and barrier layer 240 have
Different etch rates, can select suitable etching technics to perform etching removal offset side wall 220, gap
Side wall 221, and retain barrier layer 240.
During offset side wall 220 and gap side wall 221 are etched formation opening 250, offset side
The etching selection ratio on wall 220 and barrier layer 240 is 4:1～10:1, gap side wall 221 and barrier layer 240
Etching selection ratio be 4:1～10:1.
In the present embodiment, form opening 250 etch bias side wall 220 and gap side wall 221 are etched
During, selecting offset side wall 220, the material of gap side wall 221 is silicon nitride, barrier layer 240
Material is silicon oxide.
In the present embodiment, Tetramethylammonium hydroxide (TMAH) solution or ammonia (NH are used3) water-soluble
Liquid carry out wet etching remove offset side wall 220, gap side wall 221, wherein, described tetramethyl hydroxide
The concentration of ammonium (TMAH) solution is 3%～30%, described ammonia (NH3) concentration of aqueous solution is 3%～30%.
In another embodiment, phosphoric acid solution etch bias side wall 220, gap side wall 221, etching are used
Temperature is 100 DEG C～200 DEG C, and the concentration of phosphoric acid solution is 85%～88%.
In another embodiment, employing dry etch process etch bias side wall 220, gap side wall 221,
Etching gas includes containing fluorine-based gas, such as CF4、CHF3、CH2F2、C2F2、C3F8In one
Or it is several；Etching gas flow is that 20 standard milliliters are per minute～1000 standard milliliters are per minute, biases merit
Rate is 150 watts～200 watts, and the pressure of etching cavity is 2 millitorrs～200 millitorrs.
With reference to Figure 10, Figure 11, Figure 12, the Semiconductor substrate 200 exposing described opening 250 carries out the
One halo injects and forms the first halo region 260.
Owing to having etched away offset side wall 220 (with reference to Fig. 8) and gap side wall at the first halo before injecting
221 (with reference to Fig. 8), described first halo injects will not be by offset side wall 220 and gap side wall 221
Stop, be effectively increased described first halo region 260 and enter the horizontal of grid structure 210 bottom channel
Size, adds the horizontal inhibitory action that district 230 and source-drain area 231 are lightly doped；Due to not skew
Side wall 220 and the stop of gap side wall 221, described first halo injects and can use approximately perpendicular to half
The implant angle of conductor substrate 200, concrete, the angle that the first halo injects is 0～10 degree, described angle
Degree is the direction angle with Semiconductor substrate normal of the first halo injection.In the present embodiment, employing is hung down
The first halo injection is directly carried out in the direction of Semiconductor substrate 200.
It should be noted that when using the direction being perpendicular to Semiconductor substrate 200 to carry out the first halo injection
Time, the angle that described first halo injects will not be affected by barrier layer 240, simplifies the first halo
Control to angle in injection process；It is perpendicular to the direction of Semiconductor substrate 200 carries out the it addition, use
One halo injects, and under conditions of implantation dosage and energy are certain, can increase the degree of depth of injection, increase
Longitudinal degree of depth of the first halo region 260.
Wherein, when described MOS transistor is N-type MOS transistor, described first halo injects to be adopted
Be p-type ion, such as B, In etc.；When described MOS transistor is N-type MOS transistor,
Described first halo injects and uses N-type ion, and described N-type ion includes As or P.
When described MOS transistor is N-type MOS transistor, in one embodiment, described first swoons
It is arsenic ion that ring injects the ion used, and ion implantation energy is 25KeV～50KeV, ion implantation dosage
For 1E13tom/cm2～1E14atom/cm2；In another embodiment, described first halo injects employing
Ion is phosphonium ion, and ion implantation energy is 2KeV～5KeV, and ion implantation dosage is
1E13tom/cm2～1E14atom/cm2。
When described MOS transistor is N-type MOS transistor, in one embodiment, described first swoons
It is boron ion that ring injects the ion used, and ion implantation energy is 5KeV～10KeV, ion implantation dosage
For 1E13tom/cm2～1E14atom/cm2；In another embodiment, described first halo injects employing
Ion is boron difluoride ion, and ion implantation energy is 25KeV～50KeV, and ion implantation dosage is
1E13tom/cm2～1E14atom/cm2。
Due to the barrier effect on barrier layer 240, during described first halo injects, regulate ion
Junction capacity bottom source-drain area will not be had an impact by the energy and the dosage that inject, the energy of regulation ion implanting
With dosage make the first halo region 260 surround described in the longitudinal side wall in district 230 and at least part of source and drain are lightly doped
The longitudinal side wall in district 231, longitudinal degree of depth of the most described first halo region 260 is lightly doped at least above described
Longitudinal degree of depth in district 230 so that the first halo region 260 can suppress described in district 230 and source and drain are lightly doped
The punchthrough effect in district 231.
In one embodiment, with reference to Figure 10, longitudinal degree of depth of the first halo region 260 is more than source-drain area 231
Longitudinal degree of depth.
In another embodiment, with reference to Figure 11, longitudinal degree of depth of the first halo region 260 is equal to source-drain area
Longitudinal degree of depth of 231.
In yet another embodiment, with reference to Figure 12, longitudinal degree of depth of the first halo region 260 is less than described source
Longitudinal degree of depth in the drain region 231 and longitudinal degree of depth in district 230 is lightly doped described in being more than.
Longitudinal degree of depth of described first halo region 260 is 10nm～50nm.
First halo region 260 of above-mentioned formation surrounds and the longitudinal side wall in district 230 and at least part of source is lightly doped
The longitudinal side wall in drain region 231, and the first halo region 260 enters the horizontal of grid structure 210 bottom channel
Size increases, and is effectively increased the first halo region 260 to the wearing of district 230 and source-drain area 231 is lightly doped
The inhibitory action of logical effect.
On the other hand, in carrying out the first halo injection process, due to the stop on barrier layer 240, described
The ion that first halo injects will not enter source-drain area 231 corresponding below barrier layer 240, source-drain area 231
The PN junction of bottom largely reduces in the dopant ion concentration near Semiconductor substrate side, reduces
The junction capacity of source-drain area 231, reduces the leakage current of MOS transistor.
Although it should be noted that at source-drain area 231 near the region of the longitudinal side wall of grid structure, source
Also junction capacity can be formed between drain region 231 and the first halo region 260, but the junction capacity of described formation
Area is less, MOS transistor is summed up capacitance size impact less.Generally, above-mentioned first is used to swoon
The junction capacity of the MOS transistor that ring region 260 is formed can effectively reduce.
The forming method of the most above-mentioned MOS transistor, effective suppression punchthrough effect also reduces junction capacity.
In the present embodiment, make annealing treatment after forming the first halo region 260, activate dopant ion
With elimination implantation defect.
The invention provides the forming method of the MOS transistor of another embodiment, it is provided that Semiconductor substrate,
Described semiconductor substrate surface has grid structure, and described grid structure both sides have offset side wall；To institute
The Semiconductor substrate stating grid structure both sides carries out lightly doped drain injection, is formed and district is lightly doped；With described partially
Moving side wall is that mask carries out the second halo injection to described Semiconductor substrate, is formed and district is lightly doped described in surrounding
Second areola ring region；At formation gap, described offset side wall surface side wall；In described grid structure both sides
Semiconductor substrate is formed source-drain area；On formation barrier layer, described source-drain area surface, described barrier layer is used for
Stop that ion implanting is to source-drain area；Etching technics is used to remove described offset side wall and described gap side wall shape
Become opening；The Semiconductor substrate exposing described opening carries out the first halo and injects formation the first halo region.
With reference to Figure 13, it is provided that Semiconductor substrate 300, Semiconductor substrate 300 surface has grid structure 310,
Grid structure 310 both sides have offset side wall 320；The Semiconductor substrate 300 of grid structure both sides is carried out
Lightly doped drain injects, and is formed and district 330 is lightly doped.
Described grid structure 310 includes the gate dielectric layer 311 being positioned in Semiconductor substrate 300 and is positioned at grid
Gate electrode layer 312 on dielectric layer.
The present embodiment provide Semiconductor substrate 300, grid structure 310, offset side wall 320, be lightly doped
District 330 and Semiconductor substrate 200, grid structure 210, the offset side wall 220 in Fig. 8, district is lightly doped
The formation process of 230 is consistent, is not described in detail in this.
With reference to Figure 13, for mask, Semiconductor substrate 300 is carried out the second halo injection with offset side wall 320,
Formed and surround the second areola ring region 332 that district 330 is lightly doped.
Described second halo injects and can suppress hot carrier injection effect and punch-through effect further, improves
The performance of device.
It should be noted that described second halo injection can be before or after described lightly doped drain injects
Carry out.
Wherein, when described MOS transistor is N-type, described second halo injects and uses p-type
Ion, such as B, In etc.；When described MOS transistor is p-type, described second halo injects and uses
Be N-type ion, N-type ion includes As or P.
The energy of the ion that described second halo injects is 20KeV～40KeV, and dosage is
1E13atom/cm2～5E13atom/cm2, implant angle is 20 degree～35 degree.
In the present embodiment, anneal in the lump after formation is lightly doped district 330 and second areola ring region 332,
Activate dopant ion and eliminate implantation defect.In other embodiments, can select district to be lightly doped in formation
330 and second areola ring region 332 after make annealing treatment respectively.
With reference to Figure 13, at formation gap, described offset side wall 320 surface side wall 321, at grid structure 310
The Semiconductor substrate 300 of both sides is formed source-drain area 331.
The present embodiment formed gap side wall 321, technique and the gap side wall 221 in Fig. 8 of source-drain area 331,
The formation process of source-drain area 231 is consistent, is not described in detail in this.
With reference to Figure 14, on formation barrier layer, source-drain area 331 surface 340, described barrier layer 340 is used for hindering
Gear ion implanting is to source-drain area 331；Remove offset side wall 320 and gap side wall 321 forms opening 350；
The Semiconductor substrate 300 exposing opening 350 carries out the first halo and injects formation the first halo region 360.
In the present embodiment, the formation process on the barrier layer 240 in the formation process on barrier layer 340 and Fig. 8
Unanimously, it is not described in detail in this.
In the present embodiment, remove offset side wall 320 and gap side wall 321 formed the technique of opening 350 with
Fig. 9 removes offset side wall 220 consistent with the technique that gap side wall 221 forms opening 250, at this not
Describe in detail again.
The technique forming the first halo region 360 in the present embodiment forms work with the first halo region 260 in Figure 10
Skill is consistent, is not described in detail in this.
With reference to Figure 14, in the present embodiment, longitudinal degree of depth of the first halo region 360 is more than source-drain area 331
Longitudinal degree of depth；With reference to Figure 15, in another embodiment, longitudinal degree of depth of the first halo region 360 is less than source
Longitudinal degree of depth in drain region 331 and more than longitudinal degree of depth that district 330 is lightly doped；With reference to Figure 16, real at another
Executing in example, longitudinal degree of depth of the first halo region 360 is equal to longitudinal degree of depth of source-drain area 331.
It should be noted that described second areola ring region 332 is to tie grid with offset side wall 320 for mask
The Semiconductor substrate 300 of structure 310 both sides carries out what the second halo injection was formed, and described first halo region
360 is the quasiconductor lining exposing the opening 350 formed after removing offset side wall 320 and gap side wall 321
The end, carries out the first halo and injects formation, and therefore the first halo region 360 enters bottom grid structure 310
Lateral dimension is bigger than the lateral dimension that second areola ring region 332 enters bottom grid structure 310.
Described second halo injects and can suppress hot carrier injection effect and punch-through effect further, improves
The performance of device.Further, since the first halo region 360 surrounds the longitudinal side wall and extremely that district 330 is lightly doped
The longitudinal side wall of small part source-drain area 331, and the first halo region 360 enters ditch bottom grid structure 310
The lateral dimension in road increases, so the concentration that need not inject by improving described second areola ring region forms weight
The second areola ring region of doping is to increase the area of described second areola ring region, permissible in described second areola ring region
Carry out the ion doping of low concentration.Use low concentration second areola ring region can reduce the knot electricity of MOS transistor
Hold.
The invention provides the MOS transistor of another embodiment, including: Semiconductor substrate, quasiconductor serves as a contrast
Basal surface has grid structure；It is positioned at the source-drain area of described grid structure semiconductor substrates on two sides；It is positioned at
The barrier layer on described source-drain area surface；Opening between described barrier layer and described grid structure；Position
First halo region corresponding with described opening in the Semiconductor substrate that described opening exposes；It is positioned at described
District be lightly doped in grid structure semiconductor substrates on two sides, described first halo region surround described in district is lightly doped
Sidewall.
Refer to Figure 10 to Figure 12, in the present embodiment, MOS transistor includes Semiconductor substrate 200,
Semiconductor substrate 200 surface has grid structure 210；It is positioned at grid structure 210 semiconductor substrates on two sides
Source-drain area 231 in 200；It is positioned at the barrier layer 240 on source-drain area 231 surface；It is positioned at barrier layer 240 He
Opening 250 between grid structure 210；Be positioned at opening 250 expose Semiconductor substrate 200 with open
Mouth 250 corresponding first halo region 260；Be positioned at grid structure semiconductor substrates on two sides is lightly doped district 230,
First halo region 260 surrounds the sidewall that district 230 is lightly doped.
It should be noted that in the present embodiment, in the FEOL forming described MOS transistor,
It is formed with offset side wall, at described offset side wall table in the Semiconductor substrate 200 of grid structure 210 both sides
Face is formed with gap side wall, and described opening 250 is by shape after the described offset side wall of removal and gap side wall
Become.Described first halo region 260 is that the Semiconductor substrate 200 by exposing opening 250 carries out
One halo injects the region formed.
In MOS transistor in the present embodiment, have out between described barrier layer and described grid structure
Mouthful, there is in the Semiconductor substrate that described opening exposes first halo region corresponding with described opening, institute
State the first halo region and surround the sidewall that district is lightly doped in described grid structure semiconductor substrates on two sides, and institute
State first halo region lateral dimension in grid structure underlying channel region relatively big, described first halo region pair
The inhibitory action of the punchthrough effect that district and source-drain area are lightly doped strengthens.It addition, there is resistance on source-drain area surface
Barrier, so described first halo region prevents take up the region of source-drain area corresponding below described barrier layer, institute
State the PN junction bottom source-drain area largely to drop in the dopant ion concentration near Semiconductor substrate side
Low, the junction capacity of source-drain area reduces, and the leakage current of MOS transistor reduces.
The invention provides the MOS transistor of another embodiment, including: Semiconductor substrate, quasiconductor serves as a contrast
Basal surface has grid structure；It is positioned at the source-drain area of described grid structure semiconductor substrates on two sides；It is positioned at
The barrier layer on described source-drain area surface；Opening between described barrier layer and described grid structure；Position
First halo region corresponding with described opening in the Semiconductor substrate that described opening exposes；It is positioned at described
District be lightly doped in grid structure semiconductor substrates on two sides, described first halo region surround described in district is lightly doped
Sidewall；It is positioned at the second areola ring region that district is lightly doped described in the encirclement of described grid structure both sides；Described second
The lateral depth of halo region is less than the lateral depth of described first halo region.
Refer to Figure 14 to Figure 16, in the present embodiment, MOS transistor includes Semiconductor substrate 300,
Semiconductor substrate 300 surface has grid structure 310；It is positioned at grid structure 310 semiconductor substrates on two sides
Source-drain area 331；It is positioned at the barrier layer 340 on source-drain area 331 surface, is positioned at barrier layer 340 and grid knot
Opening 350 between structure 310；It is positioned at the first halo region of the Semiconductor substrate 300 that opening 350 exposes
360；Be positioned at grid structure 310 semiconductor substrates on two sides 300 is lightly doped district 330, the first halo region
360 surround the sidewall that district 330 is lightly doped；It is positioned at grid structure 310 both sides to surround the of district 330 is lightly doped
Two halo region 332；The lateral depth of described second areola ring region 332 is less than the deepest of the first halo region 360
Degree.
It should be noted that in the present embodiment, in the FEOL forming above-mentioned MOS transistor,
It is formed with offset side wall, at described offset side wall table in the Semiconductor substrate 300 of grid structure 310 both sides
Face is formed with gap side wall, and described opening 350 is by shape after the described offset side wall of removal and gap side wall
Become.Described first halo region 360 is that the Semiconductor substrate 300 by exposing opening 350 carries out
One halo injects the region formed.
In the present embodiment, described MOS transistor has and is positioned at described grid structure both sides and surrounds and described gently mix
The second areola ring region in miscellaneous district, the lateral depth of described second areola ring region is horizontal less than described first halo region
The degree of depth.Described second areola ring region can suppress hot carrier injection effect and punch-through effect further, improves
The performance of MOS transistor.
In sum, the present invention provides and has the advantages that
Formed open owing to etching away described offset side wall and described gap side wall before injecting at the first halo
Mouthful, the Semiconductor substrate then exposed described opening carries out the first halo and injects formation the first halo region,
Described first halo injects and will not be stopped by described offset side wall and described gap side wall, thus described
First halo region enters the lateral dimension of grid structure underlying channel region to be increased, and the first halo region is to gently mixing
The inhibitory action of the punchthrough effect of miscellaneous district and source-drain area strengthens.On the other hand, the first halo injection is being carried out
During, due to the stop on barrier layer, the ion that described first halo injects will not enter described barrier layer
The source-drain area that lower section is corresponding, the PN junction bottom described source-drain area the doping near Semiconductor substrate side from
Sub-concentration largely reduces, and reduces the junction capacity of source-drain area, reduces the electric leakage of MOS transistor
Stream.The forming method of MOS transistor that i.e. present invention provides, it is possible to effectively reduce simultaneously junction capacity and
Punchthrough effect, thus improve the performance of MOS transistor.
Further, described first halo injects and uses the direction being perpendicular to Semiconductor substrate to carry out, will not
Affected by barrier layer, simplified the control to angle in described first halo injection process；It addition,
Under conditions of implantation dosage and energy are certain, use the direction being perpendicular to Semiconductor substrate to carry out first and swoon
Ring injects, and can increase the degree of depth of injection, add longitudinal degree of depth of the first halo region, effectively suppress
Punchthrough effect.
Further, inject before or after formation is lightly doped district, with skew carrying out described lightly doped drain
Side wall is that mask has carried out the second halo injection to Semiconductor substrate, defines and district is lightly doped described in encirclement
Second areola ring region.Described second halo injects and can suppress hot carrier injection effect further and puncture effect
Should, improve the performance of device.Further, since the first halo region surrounds the longitudinal side wall and extremely that district is lightly doped
The longitudinal side wall of small part source-drain area, and the lateral dimension of the first halo region entrance grid structure bottom channel
Increase, so the concentration that need not inject by improving described second areola ring region forms heavily doped second areola
Ring region, to increase the area of described second areola ring region, can carry out low concentration in described second areola ring region
Ion doping.Use low concentration second areola ring region can reduce the junction capacity of MOS transistor.
In the MOS transistor that the present invention provides, have out between described barrier layer and described grid structure
Mouthful, there is in the Semiconductor substrate that described opening exposes first halo region corresponding with described opening, institute
State the first halo region and surround the sidewall that district is lightly doped in described grid structure semiconductor substrates on two sides, and institute
State first halo region lateral dimension in grid structure underlying channel region relatively big, described first halo region pair
The inhibitory action of the punchthrough effect that district and source-drain area are lightly doped strengthens.It addition, there is resistance on source-drain area surface
Barrier, described first halo region prevents take up the region of source-drain area corresponding below described barrier layer, described source
PN junction bottom drain region largely reduces in the dopant ion concentration near Semiconductor substrate side, source
The junction capacity in drain region reduces, and the leakage current of MOS transistor reduces.
Further, described MOS transistor have be positioned at described grid structure both sides surround described in be lightly doped
The second areola ring region in district, the lateral depth of described second areola ring region is less than the deepest of described first halo region
Degree.Described second areola ring region can suppress hot carrier injection effect and punch-through effect further, improves MOS
The performance of transistor.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (19)
1. the forming method of a MOS transistor, it is characterised in that including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface has grid structure, described grid structure both sides
There is offset side wall；
The Semiconductor substrate of described grid structure both sides is carried out lightly doped drain injection, is formed and district is lightly doped；
At formation gap, described offset side wall surface side wall；
Semiconductor substrate in described grid structure both sides forms source-drain area；
On formation barrier layer, described source-drain area surface, described barrier layer is used for stopping that ion implanting arrives described source and drain
District；
Use etching technics to remove described offset side wall and described gap side wall forms opening；
The Semiconductor substrate exposing described opening carries out the first halo injection, forms the first halo region.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described first
The angle that halo injects is 0 degree～10 degree.
The forming method of MOS transistor the most according to claim 2, it is characterised in that described first
The direction that halo injects is perpendicular to described Semiconductor substrate.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described first
Longitudinal degree of depth of halo region is at least above described longitudinal degree of depth that district is lightly doped.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described first
Longitudinal degree of depth of halo region is 10nm～50nm.
The forming method of MOS transistor the most according to claim 1, it is characterised in that removing institute
During stating offset side wall and described gap side wall formation opening, described etching technics is to described skew
The etch rate of side wall and described gap side wall is fast to the etching on described barrier layer more than described etching technics
Rate.
The forming method of MOS transistor the most according to claim 6, it is characterised in that described etching
Technique is 4:1～10:1 to the etching selection ratio on offset side wall and described barrier layer, described etching technics pair
The etching selection ratio on gap side wall and described barrier layer is 4:1～10:1.
The forming method of MOS transistor the most according to claim 7, it is characterised in that described skew
The material of side wall and gap side wall is silicon nitride, and the material on described barrier layer is silicon oxide.
The forming method of MOS transistor the most according to claim 1, it is characterised in that described stop
The thickness of layer is 50nm～100nm.
The forming method of MOS transistor the most according to claim 1, it is characterised in that also include:
Before or after described lightly doped drain injects, with described offset side wall for mask to described grid structure
The Semiconductor substrate of both sides carries out the second halo and injects the second halo that district is lightly doped described in formation encirclement
District.
The forming method of 11. MOS transistors according to claim 10, it is characterised in that described second
The ion energy that halo injects is 20KeV～40KeV, and dosage is
1E13atom/cm2～5E13atom/cm2, ion implantation angle is 20 degree～35 degree.
The forming method of 12. MOS transistors according to claim 10, it is characterised in that when to be formed
Transistor when being PMOS, the ion that described first halo injects and described second halo injects is
N-type ion.
The forming method of 13. MOS transistors according to claim 10, it is characterised in that when to be formed
Transistor when being NMOS tube, the ion that described first halo injects and described second halo injects is
P-type ion.
The forming method of 14. MOS transistors according to claim 12, it is characterised in that described first
It is arsenic ion that halo injects the ion used, and ion implantation energy is 25KeV～50KeV, ion implanting
Dosage is 1E13tom/cm2～1E14atom/cm2。
The forming method of 15. MOS transistors according to claim 12, it is characterised in that described first
It is phosphonium ion that halo injects the ion used, and ion implantation energy is 2KeV～5KeV, ion implanting agent
Amount is 1E13tom/cm2～1E14atom/cm2。
The forming method of 16. MOS transistors according to claim 13, it is characterised in that described first
It is boron ion that halo injects the ion used, and ion implantation energy is 5KeV～10KeV, ion implanting
Dosage is 1E13tom/cm2～1E14atom/cm2。
The forming method of 17. MOS transistors according to claim 13, it is characterised in that described first
It is boron difluoride ion that halo injects the ion used, and ion implantation energy is 25KeV～50KeV, from
Sub-implantation dosage is 1E13tom/cm2～1E14atom/cm2。
18. MOS transistors formed according to any one of claim 1～17, including: Semiconductor substrate,
Described semiconductor substrate surface has grid structure；It is positioned at described grid structure semiconductor substrates on two sides
Source-drain area；It is positioned at the barrier layer on described source-drain area surface；It is positioned at described barrier layer and described grid knot
Opening between structure；It is positioned at corresponding with described opening the of the Semiconductor substrate that described opening exposes
One halo region；Being positioned at the district that is lightly doped of described grid structure semiconductor substrates on two sides, described first swoons
The sidewall in district is lightly doped described in ring region encirclement.
19. MOS transistors according to claim 18, it is characterised in that also include: be positioned at described grid
The second areola ring region in district, the lateral depth of described second areola ring region are lightly doped described in the encirclement of electrode structure both sides
Lateral depth less than described first halo region.
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| CN110364570A (en) * | 2018-04-09 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof and semiconductor structure |
| CN111463285A (en) * | 2020-04-10 | 2020-07-28 | 上海华力集成电路制造有限公司 | P-type FET and method of manufacturing the same |
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| CN110364570A (en) * | 2018-04-09 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof and semiconductor structure |
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| CN111463285A (en) * | 2020-04-10 | 2020-07-28 | 上海华力集成电路制造有限公司 | P-type FET and method of manufacturing the same |
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