CN106206719B - MOS transistor and forming method thereof - Google Patents
MOS transistor and forming method thereof Download PDFInfo
- Publication number
- CN106206719B CN106206719B CN201510224853.8A CN201510224853A CN106206719B CN 106206719 B CN106206719 B CN 106206719B CN 201510224853 A CN201510224853 A CN 201510224853A CN 106206719 B CN106206719 B CN 106206719B
- Authority
- CN
- China
- Prior art keywords
- side wall
- halo
- mos transistor
- gate structure
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of MOS transistor and forming method thereof, the forming method of MOS transistor include: offer semiconductor substrate, and the semiconductor substrate surface has gate structure, and the gate structure two sides have offset side wall；Lightly doped drain injection is carried out to the semiconductor substrate of the gate structure two sides, forms lightly doped district；Gap side wall is formed on the offset side wall surface；Semiconductor substrate in the gate structure two sides forms source-drain area；Barrier layer is formed on the source-drain area surface, the barrier layer is for stopping source-drain area described in ion implanting；The offset side wall is removed using etching technics and gap side wall forms opening；The first halo is carried out to the semiconductor substrate of the opening exposure to inject to form the first halo region.MOS transistor performance can be improved in the forming method of the MOS transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of MOS transistor and forming method thereof.
Background technique
MOS (Metal-oxide-semicondutor) transistor, is one of most important element in modern integrated circuits, and MOS is brilliant
The basic structure of body pipe includes: semiconductor substrate；Positioned at the gate structure of semiconductor substrate surface, the gate structure includes:
Gate electrode layer positioned at the gate dielectric layer of semiconductor substrate surface and positioned at gate dielectric layer surface；Positioned at gate structure two sides half
Lightly doped district on conductor substrate and the source-drain area in gate structure semiconductor substrates on two sides.
The method for forming the MOS transistor are as follows: semiconductor substrate is provided, forms grid in the semiconductor substrate surface
Structure, the gate structure include the gate electrode layer of the gate dielectric layer and gate dielectric layer surface positioned at semiconductor substrate surface；
Offset side wall is formed on the gate structure sidewall surface, using offset side wall and gate structure as exposure mask, to gate structure two sides
Semiconductor substrate carry out lightly doped drain (Lightly Doped Drain, LDD) injection, formed lightly doped district；In offset side wall
Surface forms gap side wall；Using gate structure, offset side wall and gap side wall as exposure mask, the semiconductor of gate structure two sides is served as a contrast
Bottom carries out source-drain area injection technology, forms source-drain area.
As characteristic size further reduces, the Performance And Reliability for the MOS transistor that the prior art is formed is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of MOS transistor and forming method thereof, improves the performance of MOS transistor.
To solve the above problems, the present invention provides a kind of forming method of MOS transistor, comprising: semiconductor substrate is provided,
The semiconductor substrate surface has gate structure, and the gate structure two sides have offset side wall；To the gate structure two
The semiconductor substrate of side carries out lightly doped drain injection, forms lightly doped district；Gap side wall is formed on the offset side wall surface；?
The semiconductor substrate of the gate structure two sides forms source-drain area；Barrier layer, the barrier layer are formed on the source-drain area surface
For stopping ion implanting source-drain area；The offset side wall is removed using etching technics and gap side wall forms opening；To described
The semiconductor substrate of opening exposure carries out the first halo and injects to form the first halo region.
Further, the angle of the first halo injection is 0 degree~10 degree.
Optionally, the direction of the first halo injection is perpendicular to the semiconductor substrate.
Optionally, longitudinal depth of the longitudinal depth of first halo region at least more than the lightly doped district.
Optionally, longitudinal depth of first halo region is 10nm~50nm.
During removing the offset side wall and the gap side wall forms opening, the etching technics is to described inclined
The etch rate for moving side wall and the gap side wall is greater than the etching technics to the etch rate on the barrier layer.
Optionally, during carrying out the etching formation opening to the offset side wall and the gap side wall, institute
The etching selection ratio for stating offset side wall and the barrier layer is 4:1~10:1, the etching of the gap side wall and the barrier layer
It selects to compare for 4:1~10:1.
Optionally, it is silicon nitride, the etching that the etching technics, which etches the offset side wall and the material of gap side wall,
The material that technique etches the barrier layer is silica.
Optionally, the barrier layer with a thickness of 50nm~100nm.
Further, further includes: be exposure mask to institute using the offset side wall before or after lightly doped drain injection
The semiconductor substrate for stating gate structure two sides carries out the second halo and injects the second halo region to be formed and surround the lightly doped district.
Optionally, the ion energy of the second halo injection is 20KeV~40KeV, dosage 1E13tom/cm2~
5E13tom/cm2, ion implantation angle is 20 degree~35 degree.
Optionally, when transistor to be formed is PMOS tube, the first halo injection and second halo injection
Ion be N-type ion.
When transistor to be formed is NMOS tube, the ion of the first halo injection and second halo injection is
P-type ion.
Optionally, for the ion that the first halo injection uses for arsenic ion, ion implantation energy is 25KeV~50KeV,
Ion implantation dosage is 1E13tom/cm2~1E14atom/cm2。
Optionally, the ion that the first halo injection uses is phosphonium ion, and ion implantation energy is 2KeV~5KeV, from
Sub- implantation dosage is 1E13tom/cm2~1E14atom/cm2。
Optionally, the ion that the first halo injection uses is boron ion, and ion implantation energy is 5KeV~10KeV,
Ion implantation dosage is 1E13tom/cm2~1E14atom/cm2。
Optionally, the ion that first halo injection uses is boron difluoride ion, ion implantation energy be 25KeV~
50KeV, ion implantation dosage 1E13tom/cm2~1E14atom/cm2。
The present invention also provides a kind of MOS transistors formed using any of the above-described method, comprising: semiconductor substrate,
The semiconductor substrate surface has gate structure；Source-drain area in the gate structure semiconductor substrates on two sides；It is located at
The barrier layer on the source-drain area surface；Opening between the barrier layer and the gate structure；It is sudden and violent positioned at the opening
The first halo region corresponding with the opening in the semiconductor substrate of dew；In the gate structure semiconductor substrates on two sides
Lightly doped district, first halo region surrounds the side wall of the lightly doped district.
Optionally, further includes: surround the second halo region of the lightly doped district positioned at the gate structure two sides, described
The lateral depth of two halo regions is less than the lateral depth of first halo region.
The invention has the following advantages that
Opening is formed due to etching away the offset side wall and the gap side wall before the injection of the first halo, it is then right
The semiconductor substrate of the opening exposure carries out the first halo and injects to form the first halo region, and first halo injection will not be by
To the blocking of the offset side wall and the gap side wall, so first halo region enters gate structure underlying channel region
Lateral dimension increase, first halo region enhances the inhibiting effect of the punchthrough effect of lightly doped district and source-drain area.It is another
Aspect, in carrying out the first halo injection process, due to the blocking on barrier layer, the ion of the first halo injection will not enter
Corresponding source-drain area below the barrier layer, the PN junction of the source-drain area bottom is in the Doped ions close to semiconductor substrate side
Concentration largely reduces, and reduces the junction capacity of source-drain area, reduces the leakage current of MOS transistor.I.e. the present invention provides
MOS transistor forming method, junction capacity and punchthrough effect can be effectively reduced simultaneously, to improve MOS transistor
Performance.
Further, first halo injection is carried out using the direction perpendicular to semiconductor substrate, simplifies described the
Control in one halo injection process to angle；In addition, under conditions of implantation dosage and certain energy, using perpendicular to partly leading
The direction of body substrate carries out the first halo injection, can increase the depth of injection, increases the longitudinal deep of first halo region
Degree, can effectively inhibit punchthrough effect.
It further, is to cover with offset side wall before or after the progress lightly doped drain injects to form lightly doped district
Film has carried out the injection of the second halo to semiconductor substrate, forms the second halo region for surrounding the lightly doped district.Described second
Halo injection can further suppress hot carrier injection effect and punch-through effect, improve the performance of device.In addition, due to first
Halo region surrounds the longitudinal side wall of lightly doped district and the longitudinal side wall of at least partly source-drain area, and the first halo region enters grid knot
The lateral dimension of structure bottom channel increases, so not needing to form heavy doping by the concentration for improving the second halo region injection
The second halo region to increase by the area of second halo region, the ion of low concentration can be carried out in second halo region
Doping.It can reduce the junction capacity of MOS transistor using the second halo region of low concentration.
The forming method of MOS transistor i.e. provided by the invention, can effectively reduce junction capacity and punchthrough effect simultaneously,
To improve the performance of MOS transistor.
In MOS transistor provided by the invention, there is opening between the barrier layer and the gate structure, described
There is the first halo region corresponding with the opening, first halo region surrounds the grid in the semiconductor substrate of exposure that is open
The side wall of lightly doped district in the structure semiconductor substrates on two sides of pole, and first halo region is in gate structure underlying channel region
Lateral dimension it is larger, first halo region enhances the inhibiting effect of the punchthrough effect of lightly doped district and source-drain area.In addition,
There is barrier layer on source-drain area surface, first halo region prevents take up the region of corresponding source-drain area below the barrier layer,
The PN junction of the source-drain area bottom is largely reduced in the Doped ions concentration close to semiconductor substrate side, source-drain area
Junction capacity reduces, and the leakage current of MOS transistor reduces.
Further, the MOS transistor, which also has, surrounds the of the lightly doped district positioned at the gate structure two sides
Two halo regions, the lateral depth of second halo region are less than the lateral depth of first halo region.Second halo region
Hot carrier injection effect and punch-through effect can be further suppressed, the performance of MOS transistor is improved.
Detailed description of the invention
Fig. 1 to Fig. 4 is the schematic diagram of the section structure of the forming process of one embodiment of the invention MOS transistor；
Fig. 5 to Figure 12 is the structural schematic diagram of the forming process of MOS transistor in another embodiment of the present invention；
Figure 13 and Figure 16 is the structural schematic diagram of the forming process of MOS transistor in further embodiment of this invention.
Specific embodiment
When the MOS transistor that the prior art is formed is further reduced with characteristic size, the Performance And Reliability of transistor
It is poor.
Fig. 1 to Fig. 4 is the schematic diagram of the section structure of the forming process of one embodiment of the invention MOS transistor.
With reference to Fig. 1, semiconductor substrate 100 is provided, forms gate structure 110 on 100 surface of semiconductor substrate, it is described
Gate structure 110 includes the gate electrode positioned at 111 surface of gate dielectric layer 111 and gate dielectric layer on 100 surface of semiconductor substrate
Layer 112.
With reference to Fig. 2, offset side wall 121 is formed in 110 sidewall surfaces of gate structure, with 121 He of offset side wall
Gate structure 110 is exposure mask, carries out lightly doped drain (Lightly Doped to the semiconductor substrate 100 of 110 two sides of gate structure
Drain, LDD) injection, form lightly doped district 130.
Fig. 2 please be still referred to, is exposure mask with the offset side wall 121 and gate structure 110, to 110 two sides of gate structure
Semiconductor substrate 100 carry out halo injection, form the halo region 131 for surrounding the lightly doped district 130.The halo is infused in
It is carried out before or after the lightly doped drain injection.
The effect of halo injection is for preventing break-through (punch though, i.e. the depletion layer connection of source and drain) and short
Channelling effect (SCE).
When MOS transistor to be formed is N-type transistor, the ionic type of the lightly doped drain injection is N-type, described
The ionic type of halo injection is p-type, when MOS transistor to be formed is P-type transistor, lightly doped drain injection from
Subtype is p-type, and the ionic type of the halo injection is N-type.
Referring to FIG. 3, gap side wall 122 is formed on 121 surface of offset side wall, with gate structure 110, offset side wall 121
It is exposure mask with gap side wall 122, source-drain area injection technology is carried out to the semiconductor substrate 100 of 110 two sides of gate structure, forms source
Drain region 140.
In order to effectively play the effect of the halo region, need to increase the dosage and energy of the halo injection, so that
Halo region enlarged area (referring to Fig. 4) in subsequent anneal, increases the face for surrounding the source-drain area and the lightly doped district
Product, to improve the lateral inhibiting effect to the source-drain area and the lightly doped district.
In addition, with reference to Fig. 4, during MOS transistor formation, the doping ionic species and MOS crystal of source-drain area 140
The conduction type of the dopant well of pipe is different, and the doping ionic species of halo region 131 are identical as the conduction type of MOS transistor,
Therefore, it will form PN junction between source-drain area 140 and halo region 131, thus form parasitic load capacitance (i.e. junction capacity),
Referred to herein as the first junction capacity；Meanwhile the conduction type of the dopant well of the doping ionic species and MOS transistor of lightly doped drain injection
Difference will form the second junction capacity between lightly doped district 130 and halo region 131.Since the first junction capacity is much larger than the second knot
Capacitor, so the size of the first junction capacity mainly influences the size of the junction capacity of the MOS transistor.Junction capacity is to MOS crystal
The performance of pipe has a major impact, and reducing MOS transistor junction capacity can reduce junction leakage.
In order to effectively reduce MOS transistor junction capacity, it is desirable that reduce mixing for first junction capacity both sides to greatest extent
Heteroion concentration can such as reduce the Doped ions of halo region 131 by adjusting the ion concentration and energy that the halo injects
Concentration and reduction ion implantation energy, but this can reduce the face that halo region 131 surrounds source-drain area 140 and lightly doped district 130 again
Product, to reduce inhibition of the halo region 131 to 140 punchthrough effect of lightly doped district 130 and source-drain area.
It can be seen that the reason of above-mentioned MOS transistor performance difference is that junction capacity and punchthrough effect cannot be effectively reduced simultaneously.
The present invention provides the forming methods of the MOS transistor of another embodiment, provide semiconductor substrate, the semiconductor
Substrate surface has gate structure, and the gate structure two sides have offset side wall；To the semiconductor of the gate structure two sides
Substrate carries out lightly doped drain injection, forms lightly doped district；Gap side wall is formed on the offset side wall surface；In the grid knot
Source-drain area is formed in the semiconductor substrate of structure two sides；Barrier layer is formed on the source-drain area surface, the barrier layer is for stopping
Ion implanting is to source-drain area；The offset side wall is removed using etching technics and the gap side wall forms opening；It opens described
The semiconductor substrate of mouth exposure carries out the first halo and injects to form the first halo region.
On the one hand, the first halo injection not will receive the blocking of the offset side wall and the gap side wall, so
The lateral dimension that first halo region enters gate structure underlying channel region increases, and the first halo region is to lightly doped district and source
The inhibiting effect of the punchthrough effect in drain region enhances.
On the other hand, in carrying out the first halo injection process, due to the blocking on barrier layer, the first halo injection
Ion will not enter corresponding source-drain area below the barrier layer, and the PN junction of the source-drain area bottom is close to semiconductor substrate one
The Doped ions concentration of side largely reduces, and reduces the junction capacity of source-drain area, reduces the leakage current of MOS transistor.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention.But the present invention can be with
Much implement different from the other way of description in this, those skilled in the art can be in the feelings without prejudice to intension of the present invention
Similar popularization is done under condition, therefore the present invention is not limited to the specific embodiments disclosed below.Secondly, the present invention using schematic diagram into
Row detailed description, when describing the embodiments of the present invention, for ease of description, the schematic diagram is example, should not be limited again
The scope of protection of the invention processed.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Referring to FIG. 5, providing semiconductor substrate 200,200 surface of semiconductor substrate has gate structure 210, described
Gate structure two sides have offset side wall 220.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；The semiconductor substrate 200 can also be with
It is the semiconductor materials such as silicon, germanium, SiGe, GaAs；The semiconductor substrate 200 can be body material and be also possible to composite junction
Structure such as silicon-on-insulator；The semiconductor substrate 200 can also be other semiconductor materials, no longer illustrate one by one here.This reality
It applies in example, the material of the semiconductor substrate 200 is silicon.
The gate structure 210 includes gate dielectric layer 211, the gate electrode layer 212 on the gate dielectric layer 211.
In the present embodiment, the material of the gate dielectric layer 211 is silica, and the material of the gate electrode layer 212 is polycrystalline
Silicon.In other embodiments, the gate dielectric layer 211 and the gate electrode layer 212 constitute dummy grid, in rear grid technique, removal
The dummy grid forms high-dielectric-coefficient grid medium layer and metal gates in original dummy grid position, forms high K (K is greater than 3.9)
Metal gate structure is conducive to the breakdown voltage for improving transistor, reduces leakage current, improves transistor performance.
The method for forming the gate structure 210 are as follows: gate dielectric material layer and grid are deposited in the semiconductor substrate 200
Electrode material layer etches to the gate dielectric material layer and layer of gate electrode material using patterned mask layer as exposure mask and to form grid
Structure, the patterned mask layer define the position of gate structure 210.In the present embodiment, using plasma enhancing chemistry
Vapor deposition forms the gate dielectric material layer, using layer of gate electrode material described in low-pressure chemical vapor deposition.
210 surface of gate structure can form hard mask layer (not shown), and the hard mask layer can be in the subsequent process
Protect gate structure 210.
In the present embodiment, further includes: fleet plough groove isolation structure (not shown) is formed in semiconductor substrate 200, it is described shallow
Adjacent active area is isolated in groove isolation construction.
The semiconductor substrate 200 can also adulterate different foreign ions according to the type of MOS transistor to be formed,
For adjusting the threshold voltage of MOS transistor.In the present embodiment, when N-type MOS transistor to be formed, semiconductor substrate 200 is mixed
Miscellaneous P-type ion；In other embodiments of the invention, when N-type MOS transistor to be formed, 200 doped N-type of semiconductor substrate
Ion.
The exposure mask for functioning as subsequent lightly doped drain injection of offset side wall 220, protects gate structure 210 in subsequent work
It is not damaged in skill, and passes through the adjustable lightly doped district being subsequently formed of thickness and gate structure of offset side wall 220
The distance between 210；Meanwhile the aperture position to be formed is influenced during subsequent etching falls offset side wall 220.
The method for forming offset side wall 220 are as follows: sunk in semiconductor substrate 200 and gate structure 210 using depositing operation
Product offset side wall material layer, then using plasma dry etch process etches the offset side wall material layer and forms offset side
Wall.It is described deposition offset side wall material layer depositing operation be atom layer deposition process, plasma enhanced chemical vapor deposition,
Low-pressure chemical vapour deposition technique, ultra-high vacuum CVD method or high density plasma CVD method.
The material of offset side wall 220 can be silicon nitride, the dielectric materials such as silicon oxynitride, silica or low-K material.It is subsequent
It needs to perform etching the offset side wall 220 in technique to form opening, forms opening etching the offset side wall 220
In the process, the barrier material that the material of the offset side wall 220 compares the source-drain area surface being subsequently formed has high etching
Selection ratio.In the present embodiment, the material of the offset side wall 220 is silicon nitride.
With reference to Fig. 6, lightly doped drain injection is carried out to the semiconductor substrate 200 of 210 two sides of gate structure, forms lightly doped district
230。
The lightly doped district 230 reduces hot carrier's effect for reducing the transverse electric field intensity of source-drain area.
Wherein, when the MOS transistor is N-type, lightly doped drain injection using N-type ion, the N-type from
Attached bag includes As or P；When the MOS transistor is p-type, the lightly doped drain injection is using P-type ion, such as B, In
Deng.
The formation process of the lightly doped district 230 are as follows: with gate structure 210 and offset side wall 220 be exposure mask, in grid knot
Implanting impurity ion in the semiconductor substrate 200 of 210 two sides of structure forms lightly doped district 230；The energy of the ion implanting is
1KeV~4KeV, dosage 2E14atom/cm2~1E15atom/cm2, injection angle is 0 degree~10 degree.
It in the present embodiment, is made annealing treatment after forming lightly doped district 230, activation Doped ions and elimination injection lack
It falls into.In other embodiments, it can be made annealing treatment together after being subsequently formed source-drain area, or be subsequently formed source-drain area
It is made annealing treatment together later with the first halo region.
With reference to Fig. 7, gap side wall 221 is formed on 220 surface of offset side wall.
The effect of gap side wall 221 is the aperture position for influencing to be formed during subsequent etching falls gap side wall 221,
The position for the first halo region being subsequently formed is defined in turn；Meanwhile gap side wall 221 can be used as subsequent source-drain area ion implanting
Exposure mask, protect gate structure 210 not to be damaged, and be subsequently formed by the way that the thickness of gap side wall 221 is adjustable
The distance between source-drain area and gate structure 210.
The method for forming gap side wall 221 are as follows: sunk in semiconductor substrate 200 and gate structure 210 using depositing operation
The product clearance side walling bed of material, the etching clearance side walling bed of material form gap side wall.The deposition of the deposition clearance side walling bed of material
Technique is atom layer deposition process, plasma enhanced chemical vapor deposition, low-pressure chemical vapour deposition technique, ultrahigh vacuum
Learn vapour deposition process or high density plasma CVD method.Etch the clearance side walling bed of material technique be it is each to
Anisotropic etch technique, such as plasma dry etch.
It needs to perform etching gap side wall 221 in subsequent technique to form opening, be opened in the etching formation of gap side wall 221
During mouthful, the material of gap side wall 221 is compared to the barrier layer that the subsequent source-drain area surface in 210 two sides of gate structure is formed
Material has high etching selection ratio.The material of gap side wall 221 can be silicon nitride, the media such as silicon oxynitride or low-K material
Material.In the present embodiment, the material of the gap side wall 221 is silicon nitride.
With continued reference to FIG. 7, forming source-drain area 231 in the semiconductor substrate 200 of 210 two sides of gate structure.
Wherein, when the MOS transistor is N-type, Doped ions are using N-type ion, the N in source-drain area 231
Type ion includes As or P；When the MOS transistor is p-type, in 231st area of source-drain area Doped ions using P-type ion,
Such as B, In etc..
The formation process of source-drain area 231 are as follows: it with gate structure 210, offset side wall 220 and gap side wall 221 is exposure mask,
Implanting impurity ion in the semiconductor substrate 200 of 210 two sides of gate structure forms source-drain area 231.Ion note is carried out to source-drain area
The technique entered are as follows: the ion dose of injection is 1E13atom/cm2~2E15atom/cm2, implant angle is 0 degree~10 degree.
In other embodiments, embedded source-drain area can be used, specifically, forming the process of the embedded source-drain area
It include: to form the mask layer for covering the gate structure and part semiconductor substrate, the mask layer exposes the grid knot
The semiconductor substrate of structure two sides；Using the mask layer as exposure mask, the semiconductor is etched using anisotropic dry etch process
Substrate forms groove, fills stress material in a groove, and source-drain area ion implanting is carried out in the stress material, forms source
Drain region.The embedded source-drain area can introduce stress in the channel region of MOS transistor, improve the performance of transistor.
Specifically, when N-type MOS transistor to be formed, the stress material is SiC, the Doped ions be N-type from
Son, such as As, P etc.；When N-type MOS transistor to be formed, the stress material is SiGe, and the Doped ions are P-type ion,
The P-type ion includes B, In.
It in the present embodiment, is made annealing treatment after forming the source-drain area 231, activation Doped ions and elimination injection lack
It falls into.In other embodiments, it is made annealing treatment together after the first halo region that can continue after its formation.
With reference to Fig. 8, barrier layer 240 is formed on 231 surface of source-drain area, barrier layer 240 is for stopping ion implanting to source and drain
Area 231.
Using depositing operation, such as atom layer deposition process, plasma enhanced chemical vapor deposition, low-pressure chemical gaseous phase
Sedimentation, ultra-high vacuum CVD method or high density plasma CVD method, deposit barrier material layer,
The barrier material layer covers gate structure 210, gap side wall 221, offset side wall 220, and semiconductor substrate 200 is then right
The barrier material layer carries out flatening process such as mechanical-chemistry grinding, until exposing the top surface of gate structure 210；?
In other embodiments, when there is mask layer on 210 surface of gate structure, the barrier material layer for depositing formation is higher than institute
It states at the top of mask layer, then the barrier material layer is planarized until exposing 210 top surface of gate structure.
It needs to perform etching gap side wall 221 and offset side wall 220 in subsequent technique to form opening, in etching gap
During side wall 221 and offset side wall 220 form opening, the material on barrier layer 240 compares offset side wall 220 and gap side wall
221 material has different etching selection ratios, specifically, the etch rate of offset side wall 220 and gap side wall 221 is much larger than
The etch rate on barrier layer 240, so that being protected during subsequent etching gap side wall 221 and offset side wall 220 form opening
Stay the barrier layer 240.In the present embodiment, the material on barrier layer 240 is silica.
Due to foring barrier layer 240 on 231 surface of source-drain area, the barrier layer 240 can stop subsequent dizzy first
Ring implants ions into source-drain area 231, the knot electricity that source-drain area 231 and 200 dopant well of semiconductor substrate are formed during injecting
Hold effective reduction, to reduce the junction capacity of MOS transistor source-drain area, reduces junction leakage.
The barrier layer 240 with a thickness of 50nm~100nm.
With reference to Fig. 9, using etching technics removal offset side wall 220 (referring to Fig. 8) and gap side wall 221 (referring to Fig. 8).
After removing offset side wall 220 and gap side wall 221, opening 250 is formed, the opening 250 exposes gap side wall
The side wall of semiconductor substrate surface and gap side wall 221 and gate structure 210 between 221 and gate structure 210.
The etch bias side wall 220 and gap side wall 221 form the technique of opening 250 and include wet-etching technology and do
Method etching technics；Since offset side wall 220, gap side wall 221 and barrier layer 240 have different etch rates, can choose
Suitable etching technics performs etching removal offset side wall 220, gap side wall 221, and retains barrier layer 240.
During forming opening 250 to offset side wall 220 and the etching of gap side wall 221, offset side wall 220 and blocking
The etching selection ratio of layer 240 is 4:1~10:1, and the etching selection ratio on gap side wall 221 and barrier layer 240 is 4:1~10:1.
In the present embodiment, during forming opening 250 to etch bias side wall 220 and the etching of gap side wall 221, choosing
Select offset side wall 220, the material of gap side wall 221 is silicon nitride, the material on barrier layer 240 is silica.
In the present embodiment, using tetramethylammonium hydroxide (TMAH) solution or ammonia (NH3) aqueous solution progress wet process quarter
Etching off remove offset side wall 220, gap side wall 221, wherein the concentration of tetramethylammonium hydroxide (TMAH) solution be 3%~
30%, the ammonia (NH3) aqueous solution concentration be 3%~30%.
In another embodiment, using phosphoric acid solution etch bias side wall 220, gap side wall 221, etching temperature 100
DEG C~200 DEG C, the concentration of phosphoric acid solution is 85%~88%.
In another embodiment, using dry etch process etch bias side wall 220, gap side wall 221, etching gas packet
It includes containing fluorine-based gas, such as CF4、CHF3、CH2F2、C2F2、C3F8One or more of；Etching gas flow is 20 standards milli
Liter Per Minute~1000 standard milliliters are per minute, and bias power is 150 watts~200 watts, the pressure of etching cavity be 2 millitorrs~
200 millitorrs.
With reference to Figure 10, Figure 11, Figure 12, the first halo is carried out to the semiconductor substrate 200 of 250 exposure of opening and injects shape
At the first halo region 260.
Due to having etched away offset side wall 220 (with reference to Fig. 8) and (reference of gap side wall 221 before the injection of the first halo
Fig. 8), the first halo injection not will receive the blocking of offset side wall 220 and gap side wall 221, be effectively increased described
First halo region 260 enters the lateral dimension of 210 bottom channel of gate structure, increases to lightly doped district 230 and source-drain area 231
Lateral inhibiting effect；Due to not having the blocking of offset side wall 220 and gap side wall 221, the first halo injection can be adopted
With the implant angle approximately perpendicular to semiconductor substrate 200, specifically, the angle of the first halo injection is 0~10 degree, the angle
Degree is the direction of the first halo injection and the angle of semiconductor substrate normal.In the present embodiment, it is served as a contrast using perpendicular to semiconductor
The direction at bottom 200 carries out the first halo injection.
It should be noted that when carrying out the injection of the first halo using the direction perpendicular to semiconductor substrate 200, described the
The angle of one halo injection not will receive the influence on barrier layer 240, simplify the control in the first halo injection process to angle；
In addition, the first halo injection is carried out using the direction perpendicular to semiconductor substrate 200, in the certain condition of implantation dosage and energy
Under, the depth of injection can be increased, increase longitudinal depth of the first halo region 260.
Wherein, when the MOS transistor is N-type MOS transistor, first halo is injected using P-type ion,
Such as B, In etc.；When the MOS transistor is N-type MOS transistor, the first halo injection is using N-type ion, institute
Stating N-type ion includes As or P.
When the MOS transistor is N-type MOS transistor, in one embodiment, first halo injection use from
Son is arsenic ion, and ion implantation energy is 25KeV~50KeV, ion implantation dosage 1E13tom/cm2~1E14atom/cm2；
In another embodiment, the ion that the first halo injection uses is phosphonium ion, and ion implantation energy is 2KeV~5KeV, from
Sub- implantation dosage is 1E13tom/cm2~1E14atom/cm2。
When the MOS transistor is N-type MOS transistor, in one embodiment, first halo injection use from
Son is boron ion, and ion implantation energy is 5KeV~10KeV, ion implantation dosage 1E13tom/cm2~1E14atom/cm2；
In another embodiment, the ion that first halo injection uses is boron difluoride ion, ion implantation energy be 25KeV~
50KeV, ion implantation dosage 1E13tom/cm2~1E14atom/cm2。
Since the barrier effect on barrier layer 240 adjusts the energy of ion implanting during first halo injection
Will not have an impact with junction capacity of the dosage to source-drain area bottom, the energy and dosage for adjusting ion implanting make the first halo region 260
The longitudinal side wall of the lightly doped district 230 and the longitudinal side wall of at least partly source-drain area 231 are surrounded, i.e., described first halo region
260 longitudinal depth allows the first halo region 260 to inhibit described at least more than longitudinal depth of the lightly doped district 230
The punchthrough effect of lightly doped district 230 and source-drain area 231.
In one embodiment, with reference to Figure 10, longitudinal depth of the first halo region 260 is greater than the longitudinal deep of source-drain area 231
Degree.
In another embodiment, with reference to Figure 11, longitudinal depth of the first halo region 260 is equal to the longitudinal direction of source-drain area 231
Depth.
In yet another embodiment, with reference to Figure 12, longitudinal depth of the first halo region 260 is less than the source-drain area 231
Longitudinal depth and the longitudinal depth for being greater than the lightly doped district 230.
Longitudinal depth of first halo region 260 is 10nm~50nm.
The longitudinal side wall of the first halo region 260 encirclement lightly doped district 230 of above-mentioned formation and at least partly source-drain area 231
Longitudinal side wall, and the first halo region 260 enters the lateral dimension of 210 bottom channel of gate structure and increases, and is effectively increased the
Inhibiting effect of one halo region 260 to the punchthrough effect of lightly doped district 230 and source-drain area 231.
On the other hand, in carrying out the first halo injection process, due to the blocking on barrier layer 240, the first halo note
The ion entered will not enter the corresponding source-drain area 231 in 240 lower section of barrier layer, and the PN junction of 231 bottom of source-drain area is close to semiconductor
The Doped ions concentration of one side of substrate largely reduces, and reduces the junction capacity of source-drain area 231, reduces MOS transistor
Leakage current.
It should be noted that, although in source-drain area 231 close to the region of the longitudinal side wall of gate structure, 231 He of source-drain area
Also it will form junction capacity between first halo region 260, but the area of the junction capacity of the formation is smaller, it is total to MOS transistor
Junction capacity size influences smaller.Generally, the junction capacity of the MOS transistor formed using above-mentioned first halo region 260 can have
The reduction of effect.
The forming method of i.e. above-mentioned MOS transistor, it is effective to inhibit punchthrough effect and reduce junction capacity.
It in the present embodiment, is made annealing treatment after forming the first halo region 260, activation Doped ions and elimination injection
Defect.
The present invention provides the forming methods of the MOS transistor of another embodiment, provide semiconductor substrate, the semiconductor
Substrate surface has gate structure, and the gate structure two sides have offset side wall；To the semiconductor of the gate structure two sides
Substrate carries out lightly doped drain injection, forms lightly doped district；The is carried out to the semiconductor substrate using the offset side wall as exposure mask
The injection of two halos, forms the second halo region for surrounding the lightly doped district；Gap side wall is formed on the offset side wall surface；?
Source-drain area is formed in the semiconductor substrate of the gate structure two sides；Barrier layer, the blocking are formed on the source-drain area surface
Layer is for stopping ion implanting to source-drain area；The offset side wall is removed using etching technics and gap side wall formation is opened
Mouthful；The first halo is carried out to the semiconductor substrate of the opening exposure to inject to form the first halo region.
With reference to Figure 13, semiconductor substrate 300 is provided, 300 surface of semiconductor substrate has gate structure 310, gate structure
310 two sides have offset side wall 320；Lightly doped drain injection is carried out to the semiconductor substrate 300 of gate structure two sides, formation is gently mixed
Miscellaneous area 330.
The gate structure 310 includes 300 gate dielectric layer 311 and on gate dielectric layer in the semiconductor substrate
Gate electrode layer 312.
Semiconductor substrate 300, gate structure 310, offset side wall 320, lightly doped district 330 and Fig. 8 provided in this embodiment
In semiconductor substrate 200, gate structure 210, offset side wall 220, the formation process of lightly doped district 230 it is consistent, herein no longer
It is described in detail.
With reference to Figure 13, it is that exposure mask carries out the second halo injection to semiconductor substrate 300 with offset side wall 320, is formed and surrounded
Second halo region 332 of lightly doped district 330.
The second halo injection can further suppress hot carrier injection effect and punch-through effect, improve the property of device
Energy.
It should be noted that the second halo injection can carry out before or after the lightly doped drain injects.
Wherein, when the MOS transistor is N-type, the second halo injection is using P-type ion, such as B, In
Deng；When the MOS transistor is p-type, using N-type ion, N-type ion includes As or P for the second halo injection.
The energy of the ion of the second halo injection is 20KeV~40KeV, dosage 1E13atom/cm2~
5E13atom/cm2, implant angle is 20 degree~35 degree.
In the present embodiment, anneal together after forming lightly doped district 330 and the second halo region 332, activation doping
Ion and elimination implantation defect.In other embodiments, can choose formed lightly doped district 330 and the second halo region 332 it
It is made annealing treatment respectively afterwards.
With reference to Figure 13, gap side wall 321 is formed on 320 surface of offset side wall, in partly leading for 310 two sides of gate structure
Source-drain area 331 is formed in body substrate 300.
The present embodiment forms gap side wall 221, source-drain area 231 in the technique and Fig. 8 of gap side wall 321, source-drain area 331
Formation process it is consistent, this will not be detailed here.
With reference to Figure 14, barrier layer 340 is formed on 331 surface of source-drain area, the barrier layer 340 is for stopping ion implanting to arrive
Source-drain area 331；It removes offset side wall 320 and gap side wall 321 forms opening 350；To the semiconductor substrate of the exposure of opening 350
300 the first halos of progress inject to form the first halo region 360.
In the present embodiment, the formation process on barrier layer 340 is consistent with the formation process on barrier layer 240 in Fig. 8, herein not
It is described in detail again.
In the present embodiment, removes offset side wall 320 and gap side wall 321 is formed in the technique and Fig. 9 of opening 350 and removed partially
It is consistent with the technique that gap side wall 221 forms opening 250 to move side wall 220, and this will not be detailed here.
The technique that the first halo region 360 is formed in the present embodiment is consistent with 260 formation process of the first halo region in Figure 10,
This is no longer described in detail.
With reference to Figure 14, in the present embodiment, longitudinal depth of the first halo region 360 is greater than longitudinal depth of source-drain area 331；Ginseng
Figure 15 is examined, in another embodiment, longitudinal depth of the first halo region 360 is less than longitudinal depth of source-drain area 331 and is greater than light
Longitudinal depth of doped region 330；With reference to Figure 16, in another embodiment, longitudinal depth of the first halo region 360 is equal to source-drain area
331 longitudinal depth.
It should be noted that it is exposure mask to 310 two sides of gate structure that second halo region 332, which is with offset side wall 320,
Semiconductor substrate 300 carry out second halo and inject to be formed, and first halo region 360 is to removal offset side wall 320
It carries out the first halo with the semiconductor substrate of the exposure of opening 350 formed after gap side wall 321 to inject to be formed, therefore first is dizzy
The lateral dimension that ring region 360 enters 310 bottom of gate structure enters the transverse direction of 310 bottom of gate structure than the second halo region 332
Size is big.
The second halo injection can further suppress hot carrier injection effect and punch-through effect, improve the property of device
Energy.In addition, surrounding the longitudinal side wall of lightly doped district 330 and the longitudinal direction side of at least partly source-drain area 331 due to the first halo region 360
Wall, and the first halo region 360 enters the lateral dimension increase of 310 bottom channel of gate structure, so not needing by improving institute
The concentration for stating the injection of the second halo region forms the second halo region of heavy doping to increase the area of second halo region, described
The ion doping of low concentration can be carried out in second halo region.MOS transistor can reduce using the second halo region of low concentration
Junction capacity.
The present invention provides the MOS transistors of another embodiment, comprising: semiconductor substrate, semiconductor substrate surface have
Gate structure；Source-drain area in the gate structure semiconductor substrates on two sides；Positioned at the barrier layer on the source-drain area surface；
Opening between the barrier layer and the gate structure；Positioned at it is described opening exposure semiconductor substrate in it is described
Be open corresponding first halo region；Lightly doped district in the gate structure semiconductor substrates on two sides, first halo
Area surrounds the side wall of the lightly doped district.
Please refer to Figure 10 to Figure 12, in the present embodiment, MOS transistor includes semiconductor substrate 200, semiconductor substrate 200
Surface has gate structure 210；Source-drain area 231 in 210 semiconductor substrates on two sides 200 of gate structure；Positioned at source-drain area
The barrier layer 240 on 231 surfaces；Opening 250 between barrier layer 240 and gate structure 210；Positioned at the exposure of opening 250
First halo region 260 corresponding with opening 250 in semiconductor substrate 200；It is light in gate structure semiconductor substrates on two sides
Doped region 230, the first halo region 260 surround the side wall of lightly doped district 230.
It should be noted that in the present embodiment, in the front process for forming the MOS transistor, in gate structure 210
It is formed with offset side wall in the semiconductor substrate 200 of two sides, is formed with gap side wall, the opening on the offset side wall surface
250 be by being formed after removing the offset side wall and gap side wall.First halo region 260 is by opening 250
Exposed semiconductor substrate 200 carries out the first halo and injects the region to be formed.
In MOS transistor in the present embodiment, there is opening between the barrier layer and the gate structure, described
There is the first halo region corresponding with the opening, first halo region surrounds the grid in the semiconductor substrate of exposure that is open
The side wall of lightly doped district in the structure semiconductor substrates on two sides of pole, and first halo region is in gate structure underlying channel region
Lateral dimension it is larger, first halo region enhances the inhibiting effect of the punchthrough effect of lightly doped district and source-drain area.In addition,
There is barrier layer on source-drain area surface, so first halo region prevents take up the area of corresponding source-drain area below the barrier layer
The PN junction in domain, the source-drain area bottom is largely reduced in the Doped ions concentration close to semiconductor substrate side, source and drain
The junction capacity in area reduces, and the leakage current of MOS transistor reduces.
The present invention provides the MOS transistors of another embodiment, comprising: semiconductor substrate, semiconductor substrate surface have
Gate structure；Source-drain area in the gate structure semiconductor substrates on two sides；Positioned at the barrier layer on the source-drain area surface；
Opening between the barrier layer and the gate structure；Positioned at it is described opening exposure semiconductor substrate in it is described
Be open corresponding first halo region；Lightly doped district in the gate structure semiconductor substrates on two sides, first halo
Area surrounds the side wall of the lightly doped district；The second halo region of the lightly doped district is surrounded positioned at the gate structure two sides；Institute
The lateral depth for stating the second halo region is less than the lateral depth of first halo region.
Please refer to Figure 14 to Figure 16, in the present embodiment, MOS transistor includes semiconductor substrate 300, semiconductor substrate 300
Surface has gate structure 310；Source-drain area 331 in 310 semiconductor substrates on two sides of gate structure；Positioned at source-drain area 331
The barrier layer 340 on surface, the opening 350 between barrier layer 340 and gate structure 310；Positioned at partly leading for the exposure of opening 350
The first halo region 360 in body substrate 300；Lightly doped district 330 in 310 semiconductor substrates on two sides 300 of gate structure, the
The side wall of one halo region 360 encirclement lightly doped district 330；The second halo of lightly doped district 330 is surrounded positioned at 310 two sides of gate structure
Area 332；Lateral depth of the lateral depth of second halo region 332 less than the first halo region 360.
It should be noted that in the present embodiment, in the front process for forming above-mentioned MOS transistor, in gate structure 310
It is formed with offset side wall in the semiconductor substrate 300 of two sides, is formed with gap side wall, the opening on the offset side wall surface
350 be by being formed after removing the offset side wall and gap side wall.First halo region 360 is by opening 350
Exposed semiconductor substrate 300 carries out the first halo and injects the region to be formed.
In the present embodiment, the MOS transistor, which has, is located at the gate structure two sides surround the lightly doped district the
Two halo regions, the lateral depth of second halo region are less than the lateral depth of first halo region.Second halo region
Hot carrier injection effect and punch-through effect can be further suppressed, the performance of MOS transistor is improved.
In conclusion present invention offer has the advantages that
Opening is formed due to etching away the offset side wall and the gap side wall before the injection of the first halo, it is then right
The semiconductor substrate of the opening exposure carries out the first halo and injects to form the first halo region, and first halo injection will not be by
To the blocking of the offset side wall and the gap side wall, so first halo region enters gate structure underlying channel region
Lateral dimension increase, the first halo region enhances the inhibiting effect of the punchthrough effect of lightly doped district and source-drain area.On the other hand,
In carrying out the first halo injection process, due to the blocking on barrier layer, the ion of the first halo injection will not enter described
Corresponding source-drain area below barrier layer, the PN junction of the source-drain area bottom is in the Doped ions concentration close to semiconductor substrate side
It largely reduces, reduces the junction capacity of source-drain area, reduce the leakage current of MOS transistor.MOS i.e. provided by the invention
The forming method of transistor can effectively reduce junction capacity and punchthrough effect simultaneously, to improve the property of MOS transistor
Energy.
Further, the first halo injection is carried out using the direction perpendicular to semiconductor substrate, not will receive blocking
The influence of layer, simplifies the control in the first halo injection process to angle；In addition, certain in implantation dosage and energy
Under the conditions of, the first halo injection is carried out using the direction perpendicular to semiconductor substrate, the depth of injection can be increased, increase the
Longitudinal depth of one halo region, effectively inhibits punchthrough effect.
It further, is to cover with offset side wall before or after the progress lightly doped drain injects to form lightly doped district
Film has carried out the injection of the second halo to semiconductor substrate, forms the second halo region for surrounding the lightly doped district.Described second
Halo injection can further suppress hot carrier injection effect and punch-through effect, improve the performance of device.In addition, due to first
Halo region surrounds the longitudinal side wall of lightly doped district and the longitudinal side wall of at least partly source-drain area, and the first halo region enters grid knot
The lateral dimension of structure bottom channel increases, so not needing to form heavy doping by the concentration for improving the second halo region injection
The second halo region to increase by the area of second halo region, the ion of low concentration can be carried out in second halo region
Doping.It can reduce the junction capacity of MOS transistor using the second halo region of low concentration.
In MOS transistor provided by the invention, there is opening between the barrier layer and the gate structure, described
There is the first halo region corresponding with the opening, first halo region surrounds the grid in the semiconductor substrate of exposure that is open
The side wall of lightly doped district in the structure semiconductor substrates on two sides of pole, and first halo region is in gate structure underlying channel region
Lateral dimension it is larger, first halo region enhances the inhibiting effect of the punchthrough effect of lightly doped district and source-drain area.In addition,
There is barrier layer on source-drain area surface, first halo region prevents take up the region of corresponding source-drain area below the barrier layer,
The PN junction of the source-drain area bottom is largely reduced in the Doped ions concentration close to semiconductor substrate side, source-drain area
Junction capacity reduces, and the leakage current of MOS transistor reduces.
Further, the MOS transistor, which has, surrounds the second of the lightly doped district positioned at the gate structure two sides
Halo region, the lateral depth of second halo region are less than the lateral depth of first halo region.Second halo region can
To further suppress hot carrier injection effect and punch-through effect, the performance of MOS transistor is improved.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of MOS transistor characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate surface has gate structure, and the gate structure two sides have offset side
Wall；
Lightly doped drain injection is carried out to the semiconductor substrate of the gate structure two sides, forms lightly doped district, the lightly doped district
Formation process are as follows: using gate structure and offset side wall as exposure mask, the implanted dopant in the semiconductor substrate of gate structure two sides
Ion forms lightly doped district；
Gap side wall is formed on the offset side wall surface；
Semiconductor substrate in the gate structure two sides forms source-drain area；
Barrier layer is formed on the source-drain area surface, the barrier layer is for stopping ion implanting to the source-drain area；
The offset side wall is removed using etching technics and the gap side wall forms opening；
First halo injection is carried out to the semiconductor substrate of the opening exposure, forms the first halo region, first halo region
Surround the side wall of the lightly doped district, wherein the first halo injection not will receive the offset side wall and the clearance side
The blocking of wall, so the lateral dimension that first halo region enters gate structure underlying channel region increases, described first is dizzy
Ring region enhances the inhibiting effect of the punchthrough effect of lightly doped district and source-drain area.
2. the forming method of MOS transistor according to claim 1, which is characterized in that the angle of the first halo injection
Degree is 0 degree~10 degree.
3. the forming method of MOS transistor according to claim 2, which is characterized in that the side of the first halo injection
To perpendicular to the semiconductor substrate.
4. the forming method of MOS transistor according to claim 1, which is characterized in that the longitudinal direction of first halo region
Longitudinal depth of the depth at least more than the lightly doped district.
5. the forming method of MOS transistor according to claim 1, which is characterized in that the longitudinal direction of first halo region
Depth is 10nm~50nm.
6. the forming method of MOS transistor according to claim 1, which is characterized in that remove the offset side wall and
During the gap side wall forms opening, etching speed of the etching technics to the offset side wall and the gap side wall
Rate is greater than the etching technics to the etch rate on the barrier layer.
7. the forming method of MOS transistor according to claim 6, which is characterized in that the etching technics is to offset side
The etching selection ratio on wall and the barrier layer is 4:1~10:1, quarter of the etching technics to gap side wall and the barrier layer
Erosion selects to compare for 4:1~10:1.
8. the forming method of MOS transistor according to claim 7, which is characterized in that the offset side wall and clearance side
The material of wall is silicon nitride, and the material on the barrier layer is silica.
9. the forming method of MOS transistor according to claim 1, which is characterized in that the barrier layer with a thickness of
50nm~100nm.
10. the forming method of MOS transistor according to claim 1, which is characterized in that further include: it is lightly doped described
Before or after leakage injection, second areola is carried out by semiconductor substrate of the exposure mask to the gate structure two sides of the offset side wall
Ring injects the second halo region to be formed and surround the lightly doped district.
11. the forming method of MOS transistor according to claim 10, which is characterized in that the second halo injection
Ion energy is 20KeV~40KeV, dosage 1E13atom/cm2~5E13atom/cm2, ion implantation angle is 20 degree~35
Degree.
12. the forming method of MOS transistor according to claim 10, which is characterized in that when transistor to be formed is
When PMOS tube, the ion of the first halo injection and second halo injection is N-type ion.
13. the forming method of MOS transistor according to claim 10, which is characterized in that when transistor to be formed is
When NMOS tube, the ion of the first halo injection and second halo injection is P-type ion.
14. the forming method of MOS transistor according to claim 12, which is characterized in that the first halo injection is adopted
Ion is arsenic ion, and ion implantation energy is 25KeV~50KeV, ion implantation dosage 1E13tom/cm2~
1E14atom/cm2。
15. the forming method of MOS transistor according to claim 12, which is characterized in that the first halo injection is adopted
Ion is phosphonium ion, and ion implantation energy is 2KeV~5KeV, ion implantation dosage 1E13tom/cm2~
1E14atom/cm2。
16. the forming method of MOS transistor according to claim 13, which is characterized in that the first halo injection is adopted
Ion is boron ion, and ion implantation energy is 5KeV~10KeV, ion implantation dosage 1E13tom/cm2~
1E14atom/cm2。
17. the forming method of MOS transistor according to claim 13, which is characterized in that the first halo injection is adopted
Ion is boron difluoride ion, and ion implantation energy is 25KeV~50KeV, ion implantation dosage 1E13tom/cm2~
1E14atom/cm2。
18. the MOS transistor that any one according to claim 1~17 is formed, comprising: semiconductor substrate, the semiconductor
Substrate surface has gate structure；Source-drain area in the gate structure semiconductor substrates on two sides；Positioned at the source-drain area
The barrier layer on surface；Opening between the barrier layer and the gate structure；Positioned at the semiconductor of the opening exposure
The first halo region corresponding with the opening in substrate；Being lightly doped in the gate structure semiconductor substrates on two sides
Area, first halo region surround the side wall of the lightly doped district.
19. MOS transistor according to claim 18, which is characterized in that further include: it is located at the gate structure two sides and wraps
The second halo region of the lightly doped district is enclosed, the lateral depth of second halo region is less than the laterally deep of first halo region
Degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510224853.8A CN106206719B (en) | 2015-05-05 | 2015-05-05 | MOS transistor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510224853.8A CN106206719B (en) | 2015-05-05 | 2015-05-05 | MOS transistor and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106206719A CN106206719A (en) | 2016-12-07 |
| CN106206719B true CN106206719B (en) | 2019-08-27 |
Family
ID=57457870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510224853.8A Active CN106206719B (en) | 2015-05-05 | 2015-05-05 | MOS transistor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106206719B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109585546A (en) * | 2017-09-29 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110364570B (en) * | 2018-04-09 | 2023-04-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, forming method thereof and semiconductor structure |
| CN113223962B (en) * | 2020-01-21 | 2023-09-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN111463285B (en) * | 2020-04-10 | 2023-06-09 | 上海华力集成电路制造有限公司 | P-type FET and method for manufacturing the same |
| CN112750784B (en) * | 2021-01-22 | 2024-03-12 | 上海华虹宏力半导体制造有限公司 | Process manufacturing method for improving crosstalk failure of split gate flash memory |
| CN112928067B (en) * | 2021-01-22 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing CMOS integrated device |
| CN113937005A (en) * | 2021-12-16 | 2022-01-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing metal oxide semiconductor transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
| US6114211A (en) * | 1998-11-18 | 2000-09-05 | Advanced Micro Devices, Inc. | Semiconductor device with vertical halo region and methods of manufacture |
| US6297117B1 (en) * | 2001-02-12 | 2001-10-02 | Advanced Micro Devices, Inc. | Formation of confined halo regions in field effect transistor |
-
2015
- 2015-05-05 CN CN201510224853.8A patent/CN106206719B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5595919A (en) * | 1996-02-20 | 1997-01-21 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned halo process for reducing junction capacitance |
| US6114211A (en) * | 1998-11-18 | 2000-09-05 | Advanced Micro Devices, Inc. | Semiconductor device with vertical halo region and methods of manufacture |
| US6297117B1 (en) * | 2001-02-12 | 2001-10-02 | Advanced Micro Devices, Inc. | Formation of confined halo regions in field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206719A (en) | 2016-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106206719B (en) | MOS transistor and forming method thereof | |
| KR101822267B1 (en) | Forming punch-through stopper regions in finfet devices | |
| US7208397B2 (en) | Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same | |
| US8330231B2 (en) | Transistor having gate dielectric protection and structure | |
| CN102664165B (en) | Method for manufacturing complementary tunneling field effect transistor (TFET) based on standard complementary metal oxide semiconductor integrated circuit (CMOS IC) process | |
| CN103426769B (en) | Method, semi-conductor device manufacturing method | |
| US20130292774A1 (en) | Method for forming a semiconductor device having raised drain and source regions and corresponding semiconductor device | |
| CN103426768B (en) | Method, semi-conductor device manufacturing method | |
| US20060189066A1 (en) | Semiconductor device having optimized shallow junction geometries and method for fabrication thereof | |
| CN110047754A (en) | Semiconductor devices and its manufacturing method | |
| WO2015169052A1 (en) | Finfet manufacturing method | |
| JP2006060208A (en) | Source and drain structure for high-performance sub-0.1 micrometer transistor | |
| CN108074973A (en) | Semiconductor structure and forming method thereof | |
| US20150249129A1 (en) | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS | |
| CN108630548A (en) | Fin field effect pipe and forming method thereof | |
| CN102468163B (en) | Method for manufacturing NMOS (N-channel metal oxide semiconductor) transistor | |
| EP1488453A1 (en) | Ion implantation of silicon oxide liner to prevent dopant out-diffusion from source/drain extensions | |
| CN106158657B (en) | The forming method of MOS transistor | |
| CN109755297A (en) | Semiconductor devices and its manufacturing method | |
| CN104332409B (en) | Isolate the preparation method of tunneling field-effect transistor based on deep N-well technique | |
| US8377781B2 (en) | Transistor with asymmetric silicon germanium source region | |
| US8940589B2 (en) | Well implant through dummy gate oxide in gate-last process | |
| CN108281485B (en) | Semiconductor structure and forming method thereof | |
| KR100942952B1 (en) | Method for fabricating semiconductor device | |
| CN101572235B (en) | Method for forming N-type lightly doped region and method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |