CN113223962B - Method for forming semiconductor device - Google Patents
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- CN113223962B CN113223962B CN202010072650.2A CN202010072650A CN113223962B CN 113223962 B CN113223962 B CN 113223962B CN 202010072650 A CN202010072650 A CN 202010072650A CN 113223962 B CN113223962 B CN 113223962B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 172
- 238000005468 ion implantation Methods 0.000 claims abstract description 92
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000002513 implantation Methods 0.000 claims abstract description 27
- 238000002955 isolation Methods 0.000 claims description 64
- 230000001154 acute effect Effects 0.000 claims description 14
- 238000010884 ion-beam technique Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000005764 inhibitory process Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The application discloses a method for forming a semiconductor device, which comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, forming a first grid structure on the first region of the semiconductor substrate, forming a first initial photoresist layer on the second region, and then carrying out first well ion implantation by taking the first initial photoresist layer as a mask to form a first well region; and then thinning the first initial photoresist layer to form a first photoresist layer thinner than the first initial photoresist layer, and forming a first halo region in the first active region at two sides of the first gate structure by using the first photoresist layer and the first gate structure as masks and adopting first inclined ion implantation. Namely, only one photoresist layer is needed to be arranged, so that the requirements of the thickness of the photoresist layer during the first trap ion implantation and the first inclined ion implantation can be met at the same time, and the material of the photoresist layer is saved; and the first photoresistance layer obtained by thinning the first initial photoresistance layer can ensure effective implantation during first inclined ion implantation so as to ensure the performance of the device.
Description
Technical Field
The present application relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device.
Background
In the fabrication of semiconductor devices, it is often necessary to form a well region prior to forming a gate electrode; the lightly doped drain Implant (Lightly Doped Drain Implant) and halo region ion implantation (Pocket Implant) processes require self-alignment with the gate, and are therefore typically located after the gate formation. Thus, two photoresist layers are required for this series of operations.
The well region is formed by deep well ion implantation, and high-energy implantation is needed in the process, so that a thicker photoresist layer is selected to block the region which does not need to be implanted with the well ions; in the case of lightly doped drain implantation and halo region ion implantation, the ion implantation is shallow, the implantation energy is low, and the halo region ion implantation requires oblique ion implantation to form the halo region, so that the photoresist layer used is relatively thin.
If the well ion implantation and the lightly doped drain implantation are combined with the halo region ion implantation to simplify the process, a thicker photoresist layer must be used to form the well region, but when the halo region ion implantation is performed, the halo region ion implantation is insufficient due to the blocking of the photoresist layer due to the inclined ion implantation, which causes the leakage current to increase rapidly when the semiconductor device is turned off, thereby affecting the performance of the semiconductor device.
Disclosure of Invention
The application provides a method for forming a semiconductor device, which avoids shielding of first inclined ion implantation, can effectively perform the first inclined ion implantation to form a first halo region, and avoids the problem of electric leakage.
To solve the above technical problems, an embodiment of the present application discloses a method for forming a semiconductor device, including:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region;
forming a first gate structure on a first region of the semiconductor substrate, the first gate structure crossing the first active region;
forming a first initial photoresist layer on the second region after forming the first gate structure, wherein the first initial photoresist layer also extends to part of the surface of the first edge isolation region;
performing first well ion implantation on the first region by taking the first initial photoresist layer as a mask, and forming a first well region in the first region, wherein the first well region is also positioned at the partial bottom of the first edge isolation region and the bottom of the first grid structure;
after forming the first well region, thinning the first initial photoresist layer to form the first photoresist layer;
and forming a first halo region in the first active region at two sides of the first gate structure by using the first photoresist layer and the first gate structure as masks and adopting first inclined ion implantation, wherein the implantation direction of the first inclined ion implantation is an acute angle with the extending direction of the first gate structure and the width direction of the first gate structure respectively.
Preferably, the target thickness of the first photoresist layer is greater than or equal to T min And less than or equal to T max 。
Preferably T max =x/(tan β cos α), wherein,
alpha is an included angle between the projection of the ion beam on the semiconductor substrate and the extending direction of the first grid structure when the first inclined ion implantation is carried out, and alpha is an acute angle;
beta is the included angle between the ion beam and the normal direction of the surface of the semiconductor substrate when the first inclined ion implantation is carried out, and beta is an acute angle;
x is the distance between the outer edge of the first well region at the bottom of the first edge isolation region and the edge of the adjacent first active region in the extending direction of the first gate structure.
Preferably T m i n The range of values is 2500 to 3500.
Preferably, the target thickness takes a target value T target ＝(T min +T max )/2。
Preferably, in the process of thinning the first initial photoresist layer, the first initial photoresist layer is further etched along the extending direction of the first gate structure, so as to reduce the width of the first initial photoresist layer.
Preferably, the first initial photoresist layer is thinned, and after the first initial photoresist layer is formed into the first photoresist layer, the ratio of the reduced thickness of the first initial photoresist layer to the reduced width of the first initial photoresist layer is 4:1 to 6:1.
Preferably, the method further comprises: and after forming the first halo region or before forming the first halo region, performing lightly doped drain injection on the first active regions on two sides of the first gate structure by taking the first photoresist layer and the first gate structure as masks, and forming first lightly doped regions in the first active regions on two sides of the first gate structure.
Preferably, the first region is used to form a first type transistor, and the second region is used to form a second type transistor, the second type transistor and the first type transistor being of opposite device types.
Preferably, the second region includes a second active region and a second isolation region surrounding the second active region, the second isolation region adjacent to the first region is a second edge isolation region, and for the adjacent first region and second region, the adjacent first edge isolation region and second edge isolation region are adjacent;
forming a second gate structure on a second region of the semiconductor substrate during the forming of the first gate structure, the second gate structure crossing the second active region;
after forming the first lightly doped region and the first halo region, removing the first photoresist layer;
after removing the first photoresist layer, forming a second initial photoresist layer on the first region, wherein the second initial photoresist layer also extends to part of the surface of the second edge isolation region;
performing second well ion implantation on the second region by taking the second initial photoresist layer as a mask, and forming a second well region in the second region, wherein the second well region is also positioned at the partial bottom of the second edge isolation region and the bottom of the second grid structure;
after forming the second well region, thinning the second initial photoresist layer to form a second photoresist layer;
and forming a second halo region in the second active region at two sides of the second gate structure by using the second photoresist layer and the second gate structure as masks and adopting second inclined ion implantation, wherein the implantation direction of the second inclined ion implantation is an acute angle with the extending direction of the second gate structure and the width direction of the second gate structure respectively.
The beneficial effects of the application are as follows:
after a first grid structure is formed, a first initial photoresist layer is formed on a second region, and is used as a mask to perform first well ion implantation on the first region, so that a first well region is formed in the first region; after the first well region is formed, the first initial photoresist layer is thinned, the first initial photoresist layer is formed into a first photoresist layer, then the first photoresist layer and the first grid structure are used as masks, first inclined ion implantation is carried out to form a first halo region, the first halo region is formed by adopting the first inclined ion implantation, and the purpose is that the edge morphology of the first halo region, which faces towards a channel, is arc-shaped at the position, close to the crossing corner of the first grid structure and the first active region, of the first halo region, so that the inhibition effect of the first halo region on the lateral diffusion of the first lightly doped region and the first source building region is improved, and electric leakage is avoided. In the application, the first inclined ion implantation is performed on the first photoresist layer from the first initial photoresist layer adopted for the first well ion implantation, so that the material of the photoresist layer is saved. Secondly, the thickness of the first photoresist layer obtained by thinning the first initial photoresist layer is smaller, the first photoresist layer can avoid shielding of first inclined ion implantation on the first region, and effective implantation during the first inclined ion implantation can be ensured, so that the performance of the device is ensured.
Drawings
Fig. 1 to 4 are schematic structural views of a forming process of a semiconductor device in the related art;
fig. 5 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present application;
fig. 6 to 15 are schematic structural views corresponding to a method of forming a semiconductor device according to an embodiment of the present application.
Reference numerals:
1. a semiconductor substrate; 2. a first zone; 21. a first active region; 22. a first edge isolation region; 23. a first halo region; 24. a first lightly doped region; 3. a second zone; 31. a second edge isolation region; 4. a first gate structure; 5. a first photoresist layer; 51. a first initial photoresist layer; 52. a second photoresist layer; 6. a first well region; 7. and a second gate structure.
Detailed Description
Further advantages and effects of the present application will become apparent to those skilled in the art from the disclosure of the present specification, by describing the embodiments of the present application with specific examples. While the description of the application will be described in connection with the preferred embodiments, it is not intended to limit the inventive features to the implementation. Rather, the purpose of the application described in connection with the embodiments is to cover other alternatives or modifications, which may be extended by the claims based on the application. The following description contains many specific details for the purpose of providing a thorough understanding of the present application. The application may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the application. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present embodiment, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", "inner", "bottom", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship in which the inventive product is conventionally put in use, are merely for convenience of describing the present application and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In the description of the present embodiment, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present embodiment can be understood in a specific case by those of ordinary skill in the art.
As described in the background art, the existing process of forming the well region and the inclined ion implantation is complicated and requires two photoresist layers.
For example, a method for forming a semiconductor device (such as a D15HV 1.8V device), referring to fig. 1 to 4, includes: first, a semiconductor substrate 1 is provided, the semiconductor substrate 1 comprising a first region 2 and a second region 3, the first region 2 comprising a first active region and a first isolation region surrounding the first active region, wherein the first isolation region adjacent to the second region 2 is a first edge isolation region 22.
The second region 3 comprises a second active region and a second isolation region surrounding the second active region, wherein the second isolation region adjacent to the first region 2 is a second edge isolation region 31. For the adjacent first region 2 and second region 3, the adjacent first edge isolation region 22 and second edge isolation region 31 are contiguous, and reference may be made in particular to fig. 1 and 2.
Next, referring to fig. 1, a first photoresist layer 51 is formed on the second region 3, and a first well ion implantation is performed on the first region 2 using the first photoresist layer 51 as a mask to form a first well region 6.
The first well region 6 is also located at the bottom of a portion of the first edge isolation region 22.
In this step, since the ion implantation depth is required to be deep when the first well ion implantation is performed, the thickness of the first photoresist layer 51 is required to be larger.
Then, referring to fig. 2, the first photoresist layer 51 is removed and the first gate structure 4 is formed on the first region 2 of the semiconductor substrate 1, and at the same time, the second gate structure 7 is formed on the second region 3; after forming the first gate structure 4 and the second gate structure 7, a second photoresist layer 52 is formed on the second region 3.
The following process only takes the formation of NMOS on the first region as an example.
Specifically, referring to fig. 3, a first angled ion implantation is performed with the second photoresist layer 52 and the first gate structure 4 mask to form a first halo region 23.
The implantation direction of the first inclined ion implantation is respectively acute with an included angle between the extension direction of the first grid structure and the width direction of the first grid structure. The first halo region is formed by adopting first inclined ion implantation, so that the edge morphology of the first halo region, which faces the channel, is arc-shaped at the position, close to the crossing corner of the first gate structure and the first active region, of the first halo region, and the first halo region is used for increasing the inhibition effect of the first halo region on the lateral diffusion of the first lightly doped region and the first source building region and avoiding electric leakage.
Since the first angled ion implantation and the lightly doped drain implantation require shallow implanted ions, the required thickness of the second photoresist layer is small.
Then, referring to fig. 4, a first lightly doped drain implantation is performed on the semiconductor substrate 1 at both sides of the first gate structure 4, to form a first lightly doped region 24.
Note that, since the first gate structure 4 needs to be used as a mask to adjust the width of the channel when the first angled ion implantation and the lightly doped drain implantation are performed, the first angled ion implantation and the lightly doped drain implantation must be performed after the first gate structure 4 is formed.
In the above method, the steps of forming the photoresist layer twice are adopted, namely, the first photoresist layer and the second photoresist layer are formed. In order to save the process and reduce the use cost of the photoresist layer, it is proposed to perform the first well ion implantation after forming the first gate structure 4, and the first inclined ion implantation and the first lightly doped drain implantation using the first photoresist layer as a mask, and the first inclined ion implantation and the first lightly doped drain implantation using the first photoresist layer and the first gate structure 4 as a mask, so as to save the material of the photoresist layer.
However, since the thickness of the photoresist layer is required to be large during the first well ion implantation, and a certain tilt implantation angle is required during the first tilt ion implantation, and the distance between the edge of the first well region located at the bottom of part of the first edge isolation region 22 and the adjacent first active region is small along the extension direction of the first gate structure, the first photoresist layer may block the first region during the first tilt ion implantation, and the first tilt ion implantation may not be performed effectively, thereby causing a rapid increase in leakage current of the semiconductor device, and thus affecting the performance of the semiconductor device. In order to solve the above technical problem, the present application provides a method for forming a semiconductor device, referring to fig. 5, comprising the following steps:
step S1: a semiconductor substrate is provided, the semiconductor substrate comprises a first region and a second region, the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region.
Step S2: a first gate structure is formed over a first region of a semiconductor substrate, the first gate structure crossing the first active region.
Step S3: after the first gate structure is formed, a first initial photoresist layer is formed on the second region, and the first initial photoresist layer also extends to a part of the surface of the first edge isolation region.
Step S4: and performing first well ion implantation on the first region by taking the first initial photoresist layer as a mask, and forming a first well region in the first region, wherein the first well region is also positioned at part of the bottom of the first edge isolation region and the bottom of the first gate structure.
Step S5: after the first well region is formed, the first initial photoresist layer is thinned, so that the first initial photoresist layer forms a first photoresist layer.
Step S6: and forming a first halo region in the first active region at two sides of the first gate structure by using the first photoresist layer and the first gate structure as masks and adopting first inclined ion implantation, wherein the implantation direction of the first inclined ion implantation is respectively acute with an included angle between the extension direction of the first gate structure and the width direction of the first gate structure.
After the first grid structure is formed, a first initial photoresist layer is formed on the second region, and the first initial photoresist layer is used as a mask to perform first well ion implantation on the first region, so that a first well region is formed in the first region; after the first well region is formed, the first initial photoresist layer is thinned, the first initial photoresist layer is formed into a first photoresist layer, and then first oblique ion implantation is performed by taking the first photoresist layer and the first gate structure as masks, so as to form a first halo region. The first inclined ion implantation of the first photoresist layer is performed from the first initial photoresist layer adopted by the first well ion implantation, so that the material of the photoresist layer is saved. Secondly, the thickness of the first photoresist layer obtained by thinning the first initial photoresist layer is smaller, the first photoresist layer can avoid shielding the first inclined ion implantation, the effective implantation during the first inclined ion implantation can be ensured, the problem of the rapid increase of the leakage current of the semiconductor device is avoided, and the device performance is ensured. A method for forming the semiconductor device according to the present embodiment is described in detail below with reference to fig. 6 to 13. Specifically, the method for forming a semiconductor device provided in this embodiment includes:
first, referring to fig. 6 and 7 in combination, fig. 6 shows the structure of the first region and the second region, fig. 7 shows the structure on the first region and the structure on the edge of the second region, a semiconductor substrate 1 is provided, the semiconductor substrate 1 includes a first region 2 and a second region 3, the first region 2 includes a first active region 21 and a first isolation region surrounding the first active region 21, and the first isolation region adjacent to the second region 3 is a first edge isolation region 22.
Specifically, the material of the semiconductor substrate 1 is silicon, germanium, or silicon germanium. And the material of the semiconductor substrate 1 may also be other semiconductor materials, which are not exemplified here.
The first region 2 is used to form a first type transistor, and the second region 2 is used to form a second type transistor, which is opposite in device type to the first type transistor. Specifically, the first region 2 may be an N-type transistor, and the second region 3 may be a P-type transistor; it is also possible that the first region 2 is a P-type transistor and the second region 3 is an N-type transistor. The present embodiment is not particularly limited thereto.
The second region 3 comprises a second active region and a second isolation region surrounding the second active region, wherein the second isolation region adjacent to the first region 2 is a second edge isolation region 31. For adjacent first and second regions 2, 3, adjacent first and second edge isolation regions 22, 31 are contiguous.
In the present embodiment, referring to fig. 7 and 8, only one first active region 21 is shown, and thus the first isolation region surrounding the first active region 21 serves as the first edge isolation region. In other embodiments, the first region has a plurality of first active regions 21 therein, and the first isolation region adjacent to the second region 3 is a first edge isolation region 22. Referring to fig. 6, 7 and 8 in combination, fig. 8 is a top view of fig. 7, a first gate structure 4 is formed on the first region 2 of the semiconductor substrate 1, the first gate structure 4 crossing the first active region 21. The first gate structure 4 is also located on a portion of the first edge isolation region 22.
When the first region 2 includes a plurality of first active regions 21 and a plurality of first isolation regions, the first gate structure 4 also spans the first isolation regions between the first active regions 21 adjacent in the extending direction of the first gate structure. In this embodiment, during the formation of the first gate structure 4, a second gate structure 7 is also formed on the second region 3 of the semiconductor substrate 1, the second gate structure 7 crossing the second active region.
Referring to fig. 9, 10 and 11 in combination, fig. 9 is a schematic view based on fig. 6, fig. 10 is a schematic view based on fig. 7, fig. 11 is a schematic view based on fig. 8, and fig. 11 is a top view of fig. 10, after forming the first gate structure 4, a first initial photoresist layer 51 is formed on the second region 3, and the first initial photoresist layer 51 further extends onto a portion of the surface of the first edge isolation region 22.
The first initial photoresist layer 51 covers the entire second region 3 and also extends onto a portion of the surface of the first edge isolation region 22.
The first initial photoresist layer 51 exposes a portion of the surface of the first edge isolation region 22.
With continued reference to fig. 9, 10 and 11, the first region 2 is subjected to a first well ion implantation using the first initial photoresist layer 51 as a mask, and a first well region 6 is formed in the first region 2, where the first well region 6 is further located at a portion of the bottom of the first edge isolation region and at the bottom of the first gate structure 4.
Because the implantation energy of the first well ion implantation is relatively large, the first well ion implantation is performed through the first gate structure into the semiconductor substrate at the bottom of the first gate structure. The thickness of the first initial photoresist layer 51 needs to be large due to the implantation energy of the first well ion implantation to avoid the ion implantation of the first well ion implantation into the second region 3.
The extent shown by the dashed box in fig. 10 is the first well region 6, and the first well region 6 is also located at a part of the bottom of the first edge isolation region and at the bottom of the first gate structure 4, such that the extent of the first well region 6 is larger than the extent of the first active region, and the first well region 6 surrounds the first active region. Next, referring to fig. 12, after the first well region 6 is formed, the first initial photoresist layer 51 is thinned, so that the first initial photoresist layer 51 forms the first photoresist layer 5.
In this embodiment, in the process of thinning the first initial photoresist layer 51, the first initial photoresist layer 51 is further etched along the extending direction of the first gate structure 4, and the first initial photoresist layer 51 is etched along the width direction of the first gate structure 4, so that the first initial photoresist layer 51 forms the first photoresist layer 5.
In this embodiment, the extending direction of the first gate structure is parallel to the width direction of the channel at the bottom of the first gate structure, and the width direction of the first gate structure is parallel to the length direction of the channel at the bottom of the first gate structure.
It should be noted that, after the first initial photoresist layer 51 is thinned and the first initial photoresist layer 51 is formed into the first photoresist layer 5, the ratio of the reduced thickness of the first initial photoresist layer 51 to the reduced width thereof is 4:1 to 6:1. the reduced value of the thickness of the first initial photoresist layer 51 refers to a reduced dimension of the first initial photoresist layer 51 in the direction of the normal to the surface of the semiconductor substrate, and the reduced value of the width of the first initial photoresist layer 51 refers to a reduced dimension of the first initial photoresist layer 51 in the direction parallel to the surface of the semiconductor substrate. In the thinning process, not only the first initial photoresist layer 51 in the direction perpendicular to the top surface of the semiconductor substrate 1 (i.e., the thickness direction of the first initial photoresist layer 51) is thinned, but also the size of the first initial photoresist layer 51 is reduced in the extending direction of the first gate structure 4.
The ratio of the reduced value of the thickness of the first initial photoresist layer 51 to the reduced value of the width thereof is 4:1 to 6:1, which may be specifically 4: 1. 5: 1. 6:1 or any other ratio. That is, when the thickness is reduced by 100 angstroms, the width may be reduced by 16-25 angstroms.
Preferably, in this embodiment, the target thickness of the first photoresist layer 5 is greater than or equal to T min And less than or equal to T max 。
Specifically, the thickness of the first photoresist layer 5 is the thickness of the first photoresist layer 5 in the direction perpendicular to the top plane of the semiconductor substrate 1. In order to ensure that the subsequent first angled ion implantation process will not use ion implantation into the second region, so that the first photoresist layer 5 can play a masking role in the subsequent first angled ion implantation, in this embodiment, the thickness of the first photoresist layer 5 needs to be greater than or equal to T min 。
Meanwhile, in order to ensure that the first photoresist layer 5 will not be blocked by the implantation of the first inclined example adopted to form the first halo region later, the thickness of the first photoresist layer 5 is less than or equal to T max 。
In the present embodiment, T max ＝x/(tanβ*cosα)。
Wherein, alpha is an included angle between the projection of the ion beam on the semiconductor substrate 1 and the extending direction of the first grid structure 4 when the first inclined ion implantation is carried out subsequently, and alpha is an acute angle; reference may be made in particular to fig. 14.
Beta is the angle between the ion beam and the normal direction of the surface of the semiconductor substrate 1 when the first inclined ion implantation is performed subsequently, and beta is an acute angle.
x is the distance between the outer edge of the first well region 6 at the bottom of the first edge isolation region 22 and the edge of the adjacent first active region 21 in the extending direction of the first gate structure 4, and fig. 14 may be referred to specifically.
Preferably T m i n The range of values is 2500 to 3500, such as 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, etc,3300 angstroms may be 3400 or 3500 angstroms, but may be any other value, and the embodiment is not particularly limited.
In one embodiment, the target thickness is a target value T target ＝(T min +T max )/2. Specifically, the target thickness is a target value of the thickness of the first photoresist layer 5, and the range of the target value is half of the sum of the maximum value and the minimum value of the thickness of the first photoresist layer 5.
Next, referring to fig. 13 and 14, fig. 14 is a top view of fig. 13, in which the first photoresist layer 5 and the first gate structure 4 are used as masks, and first halo regions 23 are formed in the first active regions on both sides of the first gate structure 4 by using first oblique ion implantation, and the implantation direction of the first oblique ion implantation is respectively at an acute angle to the extending direction of the first gate structure 4 and the width direction of the first gate structure 4.
The first halo region is formed by adopting first inclined ion implantation, so that the edge morphology of the first halo region, which faces the channel, is arc-shaped at the position, close to the crossing corner of the first gate structure and the first active region, of the first halo region, and the first halo region is used for increasing the inhibition effect of the first halo region on the lateral diffusion of the first lightly doped region and the first source building region and avoiding electric leakage.
As shown in fig. 15, in this embodiment, after the first halo region 23 is formed, the first active regions on both sides of the first gate structure 4 are lightly doped drain implanted with the first photoresist layer 5 and the first gate structure 4 as masks, and the first lightly doped regions 24 are formed in the first active regions on both sides of the first gate structure 4.
In other embodiments, before forming the first halo region, the first active region on both sides of the first gate structure is lightly doped with the first photoresist layer and the first gate structure as masks, and a first lightly doped region is formed in the first active region on both sides of the first gate structure.
After the first grid structure is formed, a first initial photoresist layer is formed on the second region, and the first initial photoresist layer is used as a mask to perform first well ion implantation on the first region, so that a first well region is formed in the first region; after the first well region is formed, the first initial photoresist layer is thinned, the first initial photoresist layer is formed into a first photoresist layer, and then first oblique ion implantation is performed by taking the first photoresist layer and the first gate structure as masks, so as to form a first halo region. The first inclined ion implantation of the first photoresist layer is performed from the first initial photoresist layer adopted by the first well ion implantation, so that the material of the photoresist layer is saved. Secondly, the thickness of the first photoresist layer obtained by thinning the first initial photoresist layer is smaller, the first photoresist layer can avoid shielding of first inclined ion implantation in the first area, effective implantation in the first inclined ion implantation process can be ensured, the problem of leakage current surge in the closing process of the semiconductor device can not occur, and the device performance is ensured. The following describes the process of performing the second well ion implantation, the second inclined ion implantation, the lightly doped drain implantation of the second region, and the like in the second region 3.
After forming the first lightly doped region 24 and the first halo region, the first photoresist layer 5 is removed.
After removing the first photoresist layer 5, a second initial photoresist layer is formed on the first region 2, and the second initial photoresist layer also extends to a part of the surface of the second edge isolation region 31.
Performing second well ion implantation on the second region 3 by using the second initial photoresist layer as a mask, and forming a second well region in the second region 3, wherein the second well region is also positioned at part of the bottom of the second edge isolation region 31 and at the bottom of the second gate structure 7;
after forming the second well region, thinning the second initial photoresist layer to form a second photoresist layer;
and forming a second halo region in the second active region at two sides of the second gate structure 7 by using the second photoresist layer and the second gate structure 7 as masks and adopting second inclined ion implantation, wherein the implantation direction of the second inclined ion implantation is respectively acute with an included angle between the extension direction of the second gate structure 7 and the width direction of the second gate structure 7.
It should be further noted that after forming the second halo region or before forming the second halo region, the method further includes: and carrying out lightly doped drain injection on the second active regions at two sides of the second gate structure 7 by taking the second photoresist layer and the second gate structure as masks, and forming second lightly doped regions in the second active regions at two sides of the second gate structure 7.
While the application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a further detailed description of the application with reference to specific embodiments, and it is not intended to limit the practice of the application to those descriptions. Various changes in form and detail may be made therein by those skilled in the art, including a few simple inferences or alternatives, without departing from the spirit and scope of the present application.
Claims (7)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region;
forming a first gate structure on the first region of the semiconductor substrate, the first gate structure crossing the first active region;
forming a first initial photoresist layer on the second region after forming the first gate structure, the first initial photoresist layer further extending to a portion of the surface of the first edge isolation region;
performing first well ion implantation on the first region by taking the first initial photoresist layer as a mask, and forming a first well region in the first region, wherein the first well region is also positioned at part of the bottom of the first edge isolation region and the bottom of the first gate structure;
after the first well region is formed, thinning the first initial photoresist layer to enable the first initial photoresist layer to form a first photoresist layer;
forming a first halo region in the first active region at two sides of the first gate structure by using the first photoresist layer and the first gate structure as masks and adopting first inclined ion implantation, wherein the implantation direction of the first inclined ion implantation is an acute angle with the extension direction of the first gate structure and the width direction of the first gate structure respectively;
the target thickness of the first photoresist layer is greater than or equal to T min And less than or equal to T max ；
T max =x/(tan β cos α), wherein,
alpha is an included angle between the projection of the ion beam on the semiconductor substrate and the extending direction of the first grid structure when the first inclined ion implantation is carried out, and alpha is an acute angle;
beta is the included angle between the ion beam and the normal direction of the surface of the semiconductor substrate when the first inclined ion implantation is carried out, and beta is an acute angle;
x is the distance between the outer edge of the first well region at the bottom of the first edge isolation region and the adjacent edge of the first active region in the extending direction of the first gate structure;
T min the range of values is 2500 to 3500.
2. The method for forming a semiconductor device according to claim 1, wherein a target value T of the target thickness target ＝(T min +T max )/2。
3. The method of forming a semiconductor device of claim 1, wherein during thinning of said first initial photoresist layer, said first initial photoresist layer is further etched in a direction along which said first gate structure extends to reduce a width of said first initial photoresist layer.
4. The method of forming a semiconductor device according to claim 3, wherein after the first initial photoresist layer is thinned so that the first initial photoresist layer is formed into the first photoresist layer, a ratio of a reduced value of a thickness of the first initial photoresist layer to a reduced value of a width thereof is 4:1 to 6:1.
5. The method of forming a semiconductor device according to claim 1, further comprising: after forming the first halo region or before forming the first halo region, lightly doped drain injection is performed on the first active regions on two sides of the first gate structure by taking the first photoresist layer and the first gate structure as masks, and first lightly doped regions are formed in the first active regions on two sides of the first gate structure.
6. The method of forming a semiconductor device of claim 1, wherein the first region is for forming a first type transistor and the second region is for forming a second type transistor, the second type transistor and the first type transistor being of opposite device types.
7. The method of forming a semiconductor device of claim 5, wherein the second region comprises a second active region and a second isolation region surrounding the second active region, the second isolation region adjacent to the first region being a second edge isolation region, adjacent first and second edge isolation regions being contiguous for adjacent first and second regions;
forming a second gate structure on the second region of the semiconductor substrate during formation of the first gate structure, the second gate structure crossing the second active region;
after forming the first lightly doped region and the first halo region, removing the first photoresist layer;
after removing the first photoresist layer, forming a second initial photoresist layer on the first region, wherein the second initial photoresist layer also extends to part of the surface of the second edge isolation region;
performing second well ion implantation on the second region by taking the second initial photoresist layer as a mask, and forming a second well region in the second region, wherein the second well region is also positioned at part of the bottom of the second edge isolation region and the bottom of the second gate structure;
after the second well region is formed, thinning the second initial photoresist layer to enable the second initial photoresist layer to form a second photoresist layer;
and forming a second halo region in the second active region at two sides of the second gate structure by using the second photoresist layer and the second gate structure as masks and adopting second inclined ion implantation, wherein the implantation direction of the second inclined ion implantation is an acute angle with the extension direction of the second gate structure and the width direction of the second gate structure respectively.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6040208A (en) * | 1997-08-29 | 2000-03-21 | Micron Technology, Inc. | Angled ion implantation for selective doping |
| JP2008288526A (en) * | 2007-05-21 | 2008-11-27 | Sharp Corp | Manufacturing method of semiconductor device |
| CN106206719A (en) * | 2015-05-05 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6040208A (en) * | 1997-08-29 | 2000-03-21 | Micron Technology, Inc. | Angled ion implantation for selective doping |
| JP2008288526A (en) * | 2007-05-21 | 2008-11-27 | Sharp Corp | Manufacturing method of semiconductor device |
| CN106206719A (en) * | 2015-05-05 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
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