JP2006059843A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress short-channel effect in a PMOSFET and can assure an operation in a shorter gate length, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device has an n-well region formed in a semiconductor substrate and a gate electrode formed on the n-well region, a pair of boron-containing diffusion regions formed on the surface layer of the n-well at both ends of the gate electrode, a diffusion suppressing element diffusion region which is equivalent to or wider than the boron-containing diffusion region underneath a gate electrode and in which any one of diffusion suppressing element selected from among a group consisting of fluorine, a nitrogen and carbon is diffused, and a p-type impurity diffusion region at a position which is deeper than the boron-containing diffusion region and in which the lateral end is isolated from a gate electrode end from the lateral direction end of the boron-containing diffusion region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a structure of a source / drain region having a high short channel suppressing effect and a manufacturing method thereof.

  In recent years, in the LSI technology, with the integration and the speeding up of the device operation, the gate length is shortened and the junction depth of the source / drain regions is shallowed.

  Conventionally, the following process is used for forming source / drain regions in the manufacturing process of a MOS transistor. That is, after forming the gate electrode, impurity ions are implanted using this gate electrode pattern as a mask to form a shallow impurity ion implantation region corresponding to the extension portion of the source / drain region, and an annealing process is performed. Next, a sidewall is formed of an oxide film on the side wall of the gate electrode, and a second impurity ion implantation is performed using the sidewall and the gate electrode as a mask to form a deep impurity ion implantation region. Further, in order to recover and activate the crystal defects formed in the shallow ion implantation region and the deep ion implantation region formed by the two ion implantation steps, the annealing process is performed again.

  In general, when forming a PMOSFET (Pchannel MOS Field Effect Transistor), boron (B) having a high activation rate is used as impurity ions, and when forming an NMOSFET (N channel MOS Field Effect Transistor), arsenic (As ) Is used (Patent Document 1).

  However, when the source / drain regions are formed by the conventional method as described above, the PMOSFET uses boron having a larger diffusion coefficient than the arsenic used in the NMOSFET as the impurity element to be implanted. Easier to diffuse deeper. In particular, it has been pointed out that boron ions cause accelerated diffusion by pairing with silicon existing between lattices during annealing, and it is difficult to form a shallow junction equivalent to a MOSFET in a PMOSFET.

  Recently, a method (Rapid Thermal Annealing: RTA treatment) in which annealing is performed for a short time of about several seconds at a high temperature of 1000 ° C. or higher has been studied in order to suppress deep diffusion occurring during annealing. However, even if such an RTA process is adopted, the accelerated diffusion of boron caused in a pair with the interstitial silicon described above cannot be sufficiently suppressed.

Therefore, in the PMOSFET, when an equivalent junction depth is obtained as compared with the NMOSFET, the lateral diffusion region expands in the source / drain region at the gate end, that is, in the shallow impurity diffusion region of the extension portion. The overlap region between the electrode and the source / drain region increases, and the steepness of the impurity profile at the end of the lateral diffusion region under the gate electrode is inferior. For this reason, it is difficult to control the short channel effect as compared with NMOSFET, and there is a high possibility that parasitic resistance is increased.
JP 2000-269596 A, [0004] and the like.

  In order to put into practical use a fine CMOSFET having a gate length of 30 nm or less, which is currently under development, it is desired to suppress the lateral diffusion of boron in the extension portion of the PMOSFET described above.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device in which diffusion of boron in an extension portion of a source / drain region is suppressed and a method for manufacturing the same so that a short channel effect can be suppressed and a finer PMOSFET operation can be secured in the PMOSFET. Is to provide.

  The semiconductor device of the present invention is characterized by an n-well region formed in a semiconductor substrate, a gate electrode formed on the n-well region, and a boron diffusion region formed in the surface layer of the n-well at both ends of the gate electrode. A diffusion suppressing element diffusion in which at least one diffusion suppressing element selected from the group consisting of fluorine, nitrogen, and carbon including the boron diffusion region in the lateral direction at least under the gate electrode from the boron diffusion region is diffused And a p-type impurity diffusion region which is deeper than the boron diffusion region and whose lateral end is located farther from the gate electrode end than the lateral end of the boron diffusion region.

  The semiconductor device manufacturing method of the present invention is characterized in that an n-well region is formed on a substrate surface layer of a semiconductor substrate, a gate oxide film and a gate electrode are formed on the n-well region, and a surface of the n-well region. Ion implantation of at least one diffusion suppressing element selected from the group consisting of fluorine, nitrogen, and carbon into the layer to form a diffusion suppressing element ion implantation region, and annealing the diffusion suppressing element ion implantation region After forming the diffusion suppressing element diffusion region and forming the diffusion suppressing element ion implantation region, boron ions or boron compounds are ion-implanted into the surface layer of the n-well region, and boron ions included in the diffusion suppressing element diffusion region are formed. A step of forming an implantation region, a step of annealing the boron ion implantation region, a step of forming a sidewall with an insulating film on the side surface of the gate electrode, Using the electrodes and sidewalls as an implantation mask, p-type impurity ions are implanted to form a p-type impurity ion implantation region deeper than the boron ion implantation region, and a step of annealing the p-type impurity ion implantation region. That is.

  In the semiconductor device manufacturing method of the present invention, the order of steps not particularly described is not limited.

  According to the semiconductor device of the present invention, a boron diffusion region serving as an extension portion of the PMOSFET is included in the diffusion suppressing element diffusion region in which at least one element selected from the group consisting of fluorine, nitrogen, and carbon is diffused. Since the diffusion of boron in the lateral direction under the gate electrode can be suppressed, a fine PMOSFET with high controllability of the short channel effect can be provided.

  In addition, according to the method for manufacturing a semiconductor device of the present invention, annealing may be performed by implanting at least one ion selected from the group consisting of fluorine, nitrogen, and carbon before forming the boron ion implantation region. Since the diffusion of boron ions at the time is suppressed, it is possible to suppress the lateral diffusion under the gate electrode in the boron diffusion region that becomes the extension portion of the PMOSFET. Therefore, the occurrence of the short channel effect can be suppressed in a finer PMOSFET.

(First embodiment)
The first embodiment relates to a semiconductor device having a CMOSFET structure and a method for manufacturing the same, and before forming an extension portion of a source / drain region of a PMOSFET, fluorine (F) ions as a diffusion suppressing element are implanted in advance. Boron diffusion that remains in the fluorine diffusion region 20b by suppressing the diffusion of boron ions during the annealing process by forming a fluorine ion implantation region (diffusion suppression element ion implantation flow region) or a fluorine diffusion region (diffusion suppression element diffusion region). A region 22b is provided.

  The CMOSFET according to the first embodiment will be described below with reference to the drawings.

In the present specification, the “ion implantation region” generated by ion implantation is distinguished from the region after annealing by referring to the “diffusion region”.

  As shown in FIG. 1, in the CMOSFET according to the first embodiment, a p-well 16 and an n-well 17 are formed on the surface layer of the silicon substrate 10 in each element formation region defined by the element isolation region 15a. , An NMOSFET is formed on the p-well 16, and a PMOSFET is formed on the n-well 17, respectively.

  In the PMOSFET, a gate insulating film 18 is formed on the surface of the n-well 17, and a gate electrode 19 is formed on the gate insulating film 18. A sidewall 25 is formed of an insulating film on the side wall of the gate electrode 19. Source / drain regions are formed in the n-wells 17 on both sides of the gate electrode 19, which include a shallow boron diffusion region 22 b that is an extension portion in the vicinity of the gate electrode 19 and a boron diffusion formed on the outside thereof. A deep n-type impurity diffusion region 27 having an impurity concentration higher than that of the region 22b is formed.

  Further, salicide regions 28 are preferably formed on the surfaces of the gate electrode 19 and the source / drain regions to reduce the resistance, and each salicide region 28 has a wiring 31 and an interlayer formed in the interlayer insulating layer 29. The wiring 32 formed on the insulating layer 29 is connected to necessary external wiring.

  The PMOSFET according to the first embodiment has a fluorine diffusion region 20b having an effect of suppressing boron diffusion around the boron diffusion region 22b in addition to the above-described MOSFET configuration. . That is, the fluorine diffusion region 20b includes the boron diffusion region 20b at least in the lateral direction below the gate electrode 19 from the boron diffusion region 20b. Due to the presence of fluorine, in the PMOSFET according to the first embodiment shown in FIG. 1, diffusion of boron in the lateral direction extending under the gate electrode 19 is suppressed, the overlap length under the gate electrode is shortened, and steep Has a significant impurity concentration change. The occurrence of a short channel effect can be prevented with a shorter gate length than in the prior art.

  NMOSFET also has almost the same structure as PMOSFET. That is, a source / drain region is formed in the p-well 16 below both ends of the gate electrode 19, an arsenic diffusion region 21b as an extension portion is formed in the vicinity of the gate electrode 19, and an arsenic diffusion region is formed outside the arsenic diffusion region 21b. A deep n-type impurity diffusion region 26 having an impurity concentration higher than that of 21b is formed. As shown in FIG. 1, the fluorine diffusion region 20b is formed around the arsenic diffusion region 21b. However, in the NMOSFET, the existence of the fluorine diffusion region 20b is not necessarily required. This is because arsenic used as an impurity element in an NMOSFET is less diffusive than boron used as an impurity element in a PMOSFET, and thus there are few problems such as generation of parasitic resistance due to lateral diffusion. Other NMOSFET structures have substantially the same structure as the PMOSFET.

  Next, a manufacturing method of the CMOSFET according to the first embodiment will be described with reference to FIGS.

  First, the silicon substrate 10 is prepared. The silicon substrate 10 to be used may be p-type or n-type. For example, a p-type silicon substrate having a specific resistance of about 1 to 5 Ωcm manufactured by a CZ (Czochralski) method is used.

  Next, an element isolation region 15 a is formed on the silicon substrate 10. Although there is no particular limitation on the process for forming the element isolation region, for example, the element isolation region can be formed by the procedure shown in FIGS. That is, as shown in FIG. 2A, the surface of the silicon substrate 10 is thermally oxidized to form a silicon oxide film 11 having a film thickness of about 2 to 20 nm. Further, an LPCVD (low pressure CVD) method or the like is formed on the oxide film 11. A silicon nitride film 12 of about 100 nm is formed using Next, the silicon nitride film 12 corresponding to the element formation region is covered with a resist film, and the silicon nitride film 12 and the silicon oxide film 11 are etched by RIE using the resist film as an etching mask. Further, using the remaining silicon nitride film 12 as an etching mask, the silicon substrate 10 is etched by the RIE method to form a trench as shown in FIG. The depth of the trench is preferably set to a depth of about 1 to 2 times the design rule. For example, a trench having a depth of about 300 nm is formed. Preferably, as shown in the figure, an oxide film 14 having a film thickness of about 5 to 10 nm is formed on the bottom and side surfaces of the trench using a thermal oxidation method. The oxide film 14 is not always necessary.

  Subsequently, a silicon oxide film is deposited by LPCVD method or HDP method (deposition method using high density plasma), and the previously formed trench is filled with the oxide film 15. The deposited film thickness is about the sum of the depth of the trench and the thickness of the silicon nitride film 12 used as a mask material. Thereafter, the surface of the substrate is polished by CMP (chemical mechanical polishing) until the surface of the silicon nitride film 12 is exposed, and the surface is flattened. In this way, the structure shown in FIG.

Thereafter, in order to adjust the height of the oxide film 15 in the element isolation region and the surface of the silicon substrate in the element formation region, an etching process is performed using ammonium fluoride (NH ₄ F), and then the element formation region is covered. The silicon nitride film 12 is removed by etching using, for example, hot phosphoric acid. In this way, an element isolation region 15a shown in FIG.

  As a method for forming the element isolation region 15a, a so-called post-selection oxidation method in which oxidation is performed in a state where the element formation region is covered with a silicon nitride film may be used in addition to the above-described method of filling the trench.

Subsequently, the silicon oxide film 11 remaining on the surface is removed by etching with an NH ₄ F solution, and the surface of the silicon substrate 10 is again oxidized by a thermal oxidation method by about 5 nm to 10 nm to form a dummy gate oxide film. Thereafter, boron is ion-implanted into one of the pair of element formation regions at an acceleration voltage of 250 KeV to 350 KeV and a dose of about 5 × 10 ¹² cm ⁻² to 2 × 10 ¹³ cm ⁻² to form a p-well 16. In the element formation region, phosphorus is ion-implanted at an acceleration voltage of about 300 KeV to 500 KeV, about 5 × 10 ¹² cm ⁻² to 2 × 10 ¹³ cm ⁻² to form an n-well 17. Subsequently, the produced dummy gate oxide film is peeled off using a diluted HF solution. Thereafter, a gate oxide film 18 having a thickness of about 0.6 nm to 4 nm is formed again. As a method for forming the gate insulating film 18, thermal oxidation treatment may be performed in an oxygen atmosphere of about 750 ° C. using a normal vertical diffusion furnace, or a fast temperature rising and high temperature furnace (RTO apparatus) may be used. Thermal oxidation treatment may be performed in a high-temperature oxygen atmosphere at about 1000 ° C. Although an oxide film is formed here as the gate insulating film 18, various insulating films such as a nitride film and a high dielectric film may be formed. Further, nitrogen or the like may be introduced into the gate insulating film 18 using a plasma process. Further, a gate electrode 19 is formed on the gate insulating film 18. In this way, the structure shown in FIG.

  As a method for forming the gate electrode 19, for example, after depositing about 30 to 200 nm of poly-Si or amorphous Si by the LPCVD method, a resist film is coated thereon, and then the gate electrode 19 is formed by a photolithography method or an electron beam exposure method. A resist pattern corresponding to the electrode pattern is formed. Thereafter, using this resist pattern as an etching mask, poly-Si or amorphous Si is etched using the RIE method. As an etching gas, a halide can be used. Thus, for example, a gate pattern having a minimum gate length of about 10 nm to 30 nm is formed. Thereafter, the remaining resist pattern is removed.

  After forming the gate electrode 19, the surface of the gate electrode 19 and the surface of the silicon substrate may be oxidized by about 0.5 nm to 10 nm in order to improve the breakdown voltage of the gate insulating film 18 by using a thermal oxidation method. Note that this step can be omitted.

Although not shown, before the gate electrode 19 is formed, ion implantation may be performed in the channel region in order to control the threshold voltages of the PMOSFET and NMOSFET transistors. For example, boron is ion-implanted into the channel region of the p-well 16 at an acceleration voltage of 20 KeV and about 1 × 10 ¹³ cm ⁻² . Note that indium may be implanted instead of boron. Arsenic ions are implanted into the channel region of the n-well 17 at an acceleration voltage of 100 KeV from 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² .

Next, a diffusion suppressing element diffusion region and source / drain regions are formed according to the procedure shown in FIGS. First, as shown in FIG. 3E, fluorine ion implantation region 20a is formed by performing ion implantation of fluorine as a diffusion suppressing element using gate electrode 19 as an ion implantation mask. The oblique ion implantation of fluorine is preferably performed obliquely with respect to the substrate normal, preferably from an angle (θ) of 30 to 45 degrees. When oblique ion implantation is performed, it is preferable to perform ion implantation from a plurality of directions. For example, the substrate is rotated 90 degrees in the substrate surface, and injection is performed from four directions. By performing oblique ion implantation, it is possible to form a fluorine ion implanted region 20a that penetrates further under the gate electrode 19. The implantation conditions for fluorine ions, for example 1KeV~20KeV the ion acceleration voltage, preferably 3 KeV, a dose of 1E14cm ^-2 ~2E15cm ^-2, more preferably from 1E15 cm ^-2. Subsequently, the fluorine ion implantation region 20a is annealed to form a fluorine diffusion region 20b in which crystal defects introduced at the time of ion implantation are recovered. As the annealing condition, for example, a condition of heating at 900 ° C. for 10 seconds using an RTA (Rapid Thermal Anneal) method can be used. Here, the fluorine ion implantation region 20a is formed in both the NMOSFET region and the PMOSFET region, but fluorine ion implantation may be performed only in the PMOSFET region.

Subsequently, as shown in FIG. 3F, impurity ions are implanted into each well of the p well 16 and the n well 17 to form a shallow impurity ion implanted region in order to form extension portions of the source / drain regions. . That is, for example, arsenic (As) ions are implanted into the NMOSFET region by an ion implantation method using the gate electrode 19 as a mask to form an arsenic ion implanted region 21a. As the implantation conditions, the acceleration voltage is set to 1.5 KeV to 0.5 KeV, and the dose is set to about 1 × 10 ¹⁴ cm ⁻² to 10 ¹⁵ cm ⁻² .

Further, in the PMOSFET region, for example, boron (B) or boron fluoride (BF ₂ ) ions are implanted by an ion implantation method using the gate electrode 19 as a mask to form a boron ion implantation region 22a. As the implantation conditions, for example, when boron is implanted, the amount of energy applied is set to 100 eV to 1 KeV, and the dose is set to about 1 × 10 ¹⁴ cm ⁻² to 10 ¹⁵ cm ⁻² . Here, it is desirable to form the boron impurity ion implantation region 22a formed in the PMOSFET region so as to be included in the fluorine diffusion region 20b formed in the previous step. This is because when the boron ion implantation region 22a is wider than the fluorine diffusion region 20b, the diffusion suppression effect at the time of annealing cannot be expected for the boron diffusion in the region not included in the fluorine diffusion region 20b.

  Therefore, it is desirable to implant each impurity ion from a direction substantially perpendicular to the substrate surface as usual without performing oblique ion implantation. By changing the implantation angle in this way, the end of the boron ion implantation region 22a can be more reliably included in the fluorine diffusion region 20b in the lateral direction below the gate electrode 19.

  Subsequently, as shown in FIGS. 3G and 4H, the arsenic ion implantation region 21a and the boron ion implantation region 22a are annealed and activated to form the arsenic diffusion region 21b and the boron diffusion region 22b. To do. As the annealing treatment, for example, an RTA method is used and is performed at 900 ° C. for about 10 seconds. This annealing treatment recovers crystal defects caused by ion implantation and causes diffusion of impurity ions, but diffusion of impurity ions is suppressed by the presence of fluorine implanted in the previous step. In particular, in the boron ion implantation region 22a of the PMOSFET region, the enhanced diffusion that has occurred in the conventional annealing is suppressed, and the steepness of the concentration gradient at the lateral end is maintained. The mechanism by which the presence of previously implanted fluorine suppresses the diffusion of boron ions is not clear, but the point defects that accelerate the diffusion of boron are combined with fluorine, reducing the number of boron point defect pairs. It is considered that diffusion is reduced.

  In the first embodiment, the annealing process for the fluorine ion implantation region 20a is performed independently before the boron ion implantation region 22a is formed. However, it can be performed simultaneously with the annealing process for the boron ion implantation region 22a. . In this case, the process can be simplified. However, when the boron ion implantation is performed after the fluorine ion implantation region 20a is previously annealed to recover the crystal defects caused by the ion implantation process, it is more effective in the annealing process of the boron ion implantation region 22a. In addition, boron diffusion can be suppressed, and a boron diffusion region 22b having a steep concentration gradient at the lateral end can be formed.

  As shown in FIG. 3G, the pocket ion implantation regions 23a and 24a may be formed before annealing the arsenic ion implantation region 21a and the boron ion implantation region 22a. The pocket ion implantation region is an impurity of the same conductivity type as the channel region implanted into the end of the source / drain region in order to suppress the extension of the depletion layer from the source / drain region and suppress the short channel effect. An area. For example, boron ions of the same conductivity type are implanted into the surface layer of the p-well 16 in the NMOSFET region to form a pocket ion implantation region 23a, and arsenic or phosphorus ions of the same conductivity type are implanted into the surface layer of the n-well 17 in the PMOSFET region. Then, the pocket ion implantation region 24a is formed. Thereafter, annealing is performed again to obtain the structure shown in FIG.

  Next, as shown in FIG. 4 (i), each gate electrode is formed by depositing a silicon oxide film or a silicon nitride film using LPCVD or plasma CVD, and further performing etching using RIE. Sidewalls 25 are formed on the side surfaces 19. The thickness of the sidewall 25 is preferably about 0.5 to 1.5 times the minimum design rule, for example, about 70 nm.

Subsequently, as shown in FIG. 4J, an n-type impurity diffusion region 26 and a p-type impurity diffusion region 27, which are deep impurity diffusion regions for forming source / drain regions, are formed. That is, using the gate electrode 19 and the sidewall 25 as an ion implantation mask, n-type and p-type impurity ions are implanted into the NMOSFET region and the PMOSFET region, respectively, and an annealing process is further performed. Specifically, arsenic ions are implanted into the NMOSFET region under the conditions of an acceleration voltage of 10 KeV to 50 KeV and a dose of 10 ¹⁵ cm ^{−2 to} 7 × 10 ¹⁵ cm ⁻² . Further, boron ions are implanted into the PMOSFET region under the conditions of an acceleration voltage of 3 KeV to 10 KeV and a dose of 10 ¹⁵ cm ^{−2 to} 7 × 10 ¹⁵ cm ⁻² . Thereafter, for example, heat treatment is performed at 1000 ° C. for about 10 seconds by the RTA method. Alternatively, the ion implantation region may be activated by a spike annealing heat treatment method.

  Thereafter, dilute HF treatment is performed to form salicide 28 in the surface layer of each source / drain region and the surface layer of gate electrode 19 as shown in FIG. To form the salicide 28, first, after etching the surface layer of each source / drain region and the gate electrode 19, about 7 nm to 1 nm of cobalt (Co) is deposited by a sputtering method. Subsequently, a heat treatment is performed at 500 ° C. for 60 seconds in a nitrogen atmosphere to induce a cobalt silicidation reaction, thereby forming a silicide 28 made of a cobalt monosilicide layer. Note that after removing the oxide film on the surface, the unreacted metal remaining on the surface is removed by etching with a mixed solution of hydrogen peroxide and sulfuric acid. Subsequently, heat treatment is performed at 700 ° C. for 60 seconds in a nitrogen atmosphere, thereby causing phase transition of cobalt monosilicide to lower the resistance. Instead of depositing cobalt, nickel (Ni) may be deposited to form nickel salicide.

  Subsequently, as shown in FIG. 5L, a silicon oxide film which is an interlayer insulating film 29 is deposited by a well-known method such as LPCVD, and then a contact hole necessary for wiring is formed in the interlayer insulating film 29. Is formed using the RIE method. Metal is embedded in the contact hole and necessary patterning is performed to form wirings 31 and 32, thereby obtaining the CMOSFET according to the first embodiment shown in FIG.

FIG. 6 shows the short channel characteristics of the PMOSFET among the CMOSFETs thus manufactured. The horizontal axis represents the gate length, and the vertical axis represents the threshold voltage (Vth) of the transistor. In the conventional PMOSFET structure, when the gate length is 40 nm or less, the threshold voltage (Vth) is sharply reduced and the short channel effect becomes remarkable, whereas the fluorine diffusion region 20b is formed according to the first embodiment. In the case of PMOSFET, it was confirmed that the gate length at which the threshold value starts to decrease due to the short channel effect can be shortened. For example, it was confirmed that a threshold voltage in a practical range could be maintained even at a gate length of 30 nm, and it was confirmed that practical use with a finer transistor would be possible.

  Table 1 shows the result of measuring the gate-drain capacitance in the PMOS transistor having the structure according to the first embodiment. When the gate-drain capacitance value in the conventional CMOSFET with a gate length of 100 nm is 100%, the gate-drain capacitance value in the CMOSFET according to the first embodiment having the same gate length is 80%. The gate-drain capacitance corresponds to the capacitance of the capacitor formed by the gate electrode 19, the gate insulating film 18, and the drain region extending laterally under the gate electrode 19, that is, the boron diffusion region 20b. Therefore, the decrease in the gate-drain capacitance indicates that the lateral diffusion of the boron diffusion region 10b under the gate electrode 19 is suppressed and the overlap length with the gate electrode is shortened.

As described above, in the CMOSFET manufactured by the manufacturing method according to the first embodiment of the present invention, before the source / drain regions are formed, fluorine ions are implanted into a region wider than the extension portion in advance. , Suppress the diffusion of boron. As a result, since the steep concentration gradient at the lateral end portion under the gate electrode of the boron diffusion region 20b which is the extension portion can be maintained, the short channel effect can be suppressed. Therefore, the gate length can be reduced, that is, the transistor can be reduced.

(Second Embodiment)
Like the CMOSFET according to the first embodiment, the CMOSFET according to the second embodiment performs a short channel effect by performing fluorine ion implantation in advance before forming the extension portion of the source / drain region of the PMOSFET. Is suppressed.

  7A to 7C show a manufacturing method from the fluorine ion implantation process to the source / drain formation process according to the second embodiment. The difference from the CMOSFET in the first embodiment is that an offset spacer 30 which is an insulating film side wall thinner than the side wall is formed on the side wall of the gate electrode, so that the boron ion implantation region is more reliably in the fluorine ion implantation region 20a. 22c is included.

  Hereinafter, a method for manufacturing a CMOSFET according to the second embodiment will be described with reference to the drawings. Note that the process up to the formation process of the gate electrode 19 and the process from the formation of the source / drain regions to the wiring formation process can be used because the method according to the manufacturing method according to the first embodiment can be used. Description is omitted.

As shown in FIG. 7A, after the gate electrode 19 is formed, fluorine ions are implanted using the gate electrode 19 as an ion implantation mask. In the first embodiment, oblique ion implantation is performed at this time, but in the second embodiment, it is not necessary to perform oblique ion implantation, and fluorine ions may be implanted from a direction substantially perpendicular to the substrate. . The fluorine ion implantation conditions are, for example, an ion acceleration voltage of 30 KeV and a dose of 3 × 10 ¹⁴ cm ⁻² .

  Subsequently, the fluorine implantation region 20a is annealed to recover crystal defects introduced at the time of ion implantation. Thus, the fluorine diffusion region 20b is formed. As the annealing conditions, for example, an RTA method can be used, which is heated at 900 ° C. for 10 seconds. Here, the fluorine ion implantation region 20a is formed in both the NMOSFET region and the PMOSFET region, but fluorine ion implantation may be performed only in the PMOSFET region.

  Subsequently, as shown in FIG. 7B, a thin offset spacer 30 is formed of an insulating film on the side wall of the gate electrode 19. The manufacturing method of the offset spacer 30 can use the same method as that for forming the sidewall. For example, after forming a silicon oxide film or silicon nitride film with a thickness of about 10 nm using LPCVD or the like, etching is performed by RIE to form a thin offset spacer 30 with a thickness of about 6 nm.

Next, using the offset spacer 30 and the gate electrode 19 as an ion implantation mask, impurity ions such as arsenic and boron are implanted into each well of the p well 16 and the n well 17, respectively, and impurity ion implantation regions 21c and 22c are implanted. Form. The NMOSFET region, using the gate electrode 19 as a mask, by ion implantation, arsenic ions, for example an acceleration voltage 1.5KeV～0.5KeV, and implanted at a dose ^{1 × 10 14 cm -2 ~10 15} cm -2 Then, an arsenic ion implantation region 21c is formed.

In the PMOSFET region, using the offset spacer 30 and the gate electrode 19 as a mask, for example, boron (B) or boron fluoride (BF ₂ ) ions are implanted to form a boron ion implanted region 22c. As the implantation conditions, for example, when boron alone is implanted, the effective amount is 100 eV to 1 KeV, and the dose is about 1 × 10 ¹⁴ cm ⁻² to 10 ¹⁵ cm ⁻² . Due to the presence of the offset spacer 30, the end of each ion implantation region under the gate electrode 19 recedes from the end of the fluorine diffusion region 20 b, so that the boron ion implantation region 22 c is surely contained in the fluorine diffusion region 20 b. Can do. Similarly, the arsenic ion implantation region 21c is also accommodated in the fluorine diffusion region 20b.

  Subsequently, the arsenic ion implantation region 21c and the boron ion implantation region 22c are annealed and activated to form the arsenic diffusion region 21b and the boron diffusion region 22b. The annealing process is performed at 900 ° C. for about 10 seconds using, for example, the RTA method. Annealing treatment can recover crystal defects generated in the ion implantation step and diffusion of impurity ions occurs. However, diffusion of impurity ions is suppressed by the presence of fluorine. In particular, in the boron ion implantation region 22c in the PMOSFET region, the diffusion of boron at the time of annealing is suppressed due to the presence of the previously implanted fluorine, and in particular, the steepness of the concentration gradient at the lateral end extending under the gate electrode 19 Can be maintained.

  Although illustration is omitted, also in the method of manufacturing the semiconductor device according to the second embodiment, the pocket ion implantation region may be formed before annealing the impurity ion implantation regions 21c and 22c.

  Further, if the annealing process of the fluorine ion implantation region 20a is performed simultaneously with the annealing of the subsequent boron ion implantation region, the process can be simplified, but the fluorine ion implantation region 20a is annealed before the boron implantation step. If the crystal defects are recovered, the diffusion of boron can be suppressed more effectively.

  Next, as shown in FIG. 7C, a LPCVD method or a plasma CVD method is used to deposit a silicon oxide film or a silicon nitride film, and further, etching is performed using the RIE method. Sidewalls 31 are formed on the side surfaces 19. The thickness of the sidewall 31 is preferably about 0.5 to 1.5 times the minimum design rule. For example, the thickness combined with the offset spacer 30 is about 70 nm.

Subsequently, as shown in FIG. 7C, deep impurity diffusion regions for forming source / drain regions are formed. That is, arsenic ions and boron ions are implanted into the NMOSFET region and the PMOSFET region using the gate electrode 19, the sidewall 31 and the offset spacer 30 as an ion implantation mask. Further, an n-type impurity diffusion region 26 and a p-type impurity diffusion region 27 are formed by performing an annealing process. Specifically, arsenic ions are implanted into the NMOSFET region under the conditions of an acceleration voltage of 10 KeV to 50 KeV and a dose of 10 ¹⁵ cm ^{−2 to} 7 × 10 ¹⁵ cm ⁻² . Further, boron ions are implanted into the PMOSFET region under the conditions of an acceleration voltage of 3 KeV to 10 KeV and a dose of 10 ¹⁵ cm ^{−2 to} 7 × 10 ¹⁵ cm ⁻² . Thereafter, for example, heat treatment is performed at 1000 ° C. for about 10 seconds by the RTA method. Alternatively, the ion implantation region may be activated by a spike annealing heat treatment method.

  According to the method of manufacturing a semiconductor device according to the second embodiment, by using the offset spacer 30, the boron ion implantation region 22 c can be reliably included in the fluorine diffusion region 20 b. The lateral diffusion under the gate electrode of 22d can be reliably suppressed, and the short channel effect can be prevented. Therefore, the gate length can be shortened, that is, the PMOSFET can be miniaturized.

(Third embodiment)
Similar to the CMOSFET according to the first embodiment, the CMOSFET according to the third embodiment performs the short channel effect by performing fluorine ion implantation before forming the extension portion of the source / drain region of the PMOSFET. This is characterized in that a deep impurity diffusion region constituting a source / drain region is formed before fluorine ion implantation and extension portion fabrication.

  8A to 8D show a source / drain region forming process according to the third embodiment. Hereinafter, a method of manufacturing the CMOSFET according to the third embodiment will be described with reference to the drawings. In addition, the process according to the manufacturing method which concerns on 1st Embodiment can be used for the process from the formation process of the gate electrode 19 to the wiring formation process after the formation of the source / drain regions.

  First, after forming the gate insulating film 18 and the gate electrode 19, an insulating film is deposited conformally using, for example, a plasma CVD method. Thereafter, the insulating film is etched back by using the RIE method to form the sidewall 25a.

  Subsequently, using the gate electrode 19 and the sidewall 25a as an ion implantation mask, an n-type impurity such as phosphorus or arsenic is ion-implanted into the NMOSFET region, and a p-type impurity such as boron or boron fluoride is implanted into the PMOSFET region. As ion implantation conditions, conditions similar to the formation conditions of the deep impurity diffusion regions in the first or second embodiment can be used. Thereafter, annealing is performed to activate the implanted impurity ions. For the annealing, for example, a spike RTA process is performed with a peak temperature of 1050 ° C. Thus, as shown in FIG. 8A, the n-type impurity diffusion region 26 and the p-type impurity diffusion region 27 are formed in the NMOSFET region and the PMOSFET region, respectively.

Next, as shown in FIG. 8B, the sidewall 25a of the gate electrode 19 is removed by wet etching. Subsequently, using the gate electrode 19 as an ion implantation mask, fluorine ions are implanted to form a fluorine ion implanted region 20c. As in the case of the first embodiment, it is preferable to rotate 90 degrees in the substrate plane and perform oblique ion implantation from four directions from an angle of 30 to 45 degrees with respect to the substrate normal. Examples of the fluorine ion implantation conditions, the maximum dose is set to 1 × 10 ¹⁶ cm ^-2, for example, 30 KeV and ion accelerating voltage, the conditions of a dose amount 3 × 10 ¹⁴ cm ^-2 may be used.

Subsequently, the fluorine ion implantation region 20c is annealed to obtain a fluorine diffusion region 20d in which crystal defects introduced at the time of ion implantation are recovered. As the annealing condition, for example, a condition of heating at 900 ° C. for 10 seconds using the RTA method can be used. Here, NMOSFET
Fluorine ion implantation may be performed only in the MOSFET region.

Subsequently, as shown in FIG. 8C, arsenic ions and boron ions are implanted into each well of the p well 16 and the n well 17 in order to form extension portions of the source / drain regions. 21e and boron ion implantation region 22e are formed. That is, for example, arsenic ions are implanted into the NMOSFET region by ion implantation using the gate electrode 19 as a mask to form an arsenic ion implanted region 21e. As the implantation conditions, the acceleration voltage is set to 0.5 KeV to 1.5 KeV, and the dose is set to about 1 × 10 ¹⁴ cm ⁻² to 10 ¹⁵ cm ⁻² . Further, in the PMOSFET region, for example, boron or boron fluoride ions are implanted by an ion implantation method using the gate electrode 19 as a mask to form a boron ion implanted region 22e. As the implantation conditions, for example, when boron is implanted, the amount of energy applied is set to 100 eV to 1 KeV, and the dose is set to about 1 × 10 ¹⁴ cm ⁻² to 10 ¹⁵ cm ⁻² . The arsenic ion implantation region 21e and the boron ion implantation region 22e thus formed are included in the previously formed fluorine diffusion region 20d.

  Subsequently, as shown in FIG. 8D, the arsenic ion implantation region 21e and the boron ion implantation region 22e are annealed and activated to form the arsenic diffusion region 21f and the boron diffusion region 22f. The annealing process is performed at 900 ° C. for about 10 seconds using, for example, the RTA method. The annealing treatment can recover crystal defects in the arsenic ion implantation region 21e and the boron ion implantation region 22e, and diffusion of each impurity ion occurs. However, due to the presence of fluorine implanted in the previous step, the impurity ions Can be suppressed.

  In particular, in the third embodiment, the n-type impurity diffusion region 26 and the p-type impurity diffusion region 27, which are deep impurity diffusion regions, are formed before forming the arsenic ion implantation region 21e and the boron ion implantation region 22e. Therefore, the diffusion of each region is not affected by the annealing process necessary for forming the deep impurity diffusion region. That is, when the deep impurity diffusion region is formed later, the progress of boron diffusion in the boron diffusion region 22f cannot be prevented in the annealing step of the deep impurity diffusion region performed later, but in the third embodiment, Since the boron diffusion in the boron diffusion region 22f does not occur in the annealing step for forming this deep impurity diffusion region, the position of the end of the boron diffusion region 22f constituting the extension portion can be controlled more accurately. .

  Thereafter, a silicon oxide film having a thickness of about 100 nm is deposited by using a plasma CVD method or the like, and this insulating film is etched back by the RIE method to form the sidewall 25b again. Thereafter, as shown in FIG. 8D, the surface layer of the gate electrode 19 and the surface layer of the source / drain region exposed on the surface are silicided by the method according to the first embodiment, and the salicide 28 is formed. To do.

  Thereafter, according to the manufacturing method according to the first embodiment, an interlayer insulating film and a necessary wiring layer are formed to obtain a CMOSFET structure.

  In the CMOSFET manufactured by the manufacturing method according to the third embodiment, before the source / drain regions are formed, fluorine ions are implanted into a region wider than the extension portion, and the impurity ion implantation region having a shallow extension portion is formed. Since the deep impurity diffusion region is formed before forming the, the steep concentration gradient at the edge portion of the shallow impurity diffusion region is more reliably maintained, and the short channel effect can be effectively suppressed.

(Fourth embodiment)
The CMOSFET according to the fourth embodiment is the same as the first embodiment in the CMOSFET structure having a structure in which the source / drain regions formed on both sides of the gate electrode are lifted (elevated source / drain structure). Further, the short channel effect is suppressed by performing fluorine ion implantation before forming the extension portion of the source / drain region of the PMOSFET.

  Hereinafter, the manufacturing method according to the fourth embodiment will be described with reference to FIG. 9A to FIG.

  First, as shown in FIG. 9A, an element isolation region 15a, a p-well 16 and an n-well 17, a gate oxide film 18 and a gate electrode 19 are formed according to the manufacturing method of the first embodiment. Subsequently, fluorine ions are implanted using the gate electrode 19 as an ion implantation mask to form a fluorine ion implantation region 20a. Fluorine ion implantation is preferably performed from a direction oblique to the substrate normal, and the same conditions as those according to the first embodiment can be used. Subsequently, in order to remove crystal defects generated in the fluorine ion implantation region, annealing is performed to form a fluorine diffusion region 20b. Before performing fluorine ion implantation, the silicon substrate (p-well and n-well surfaces) is activated by lamp annealing in an oxygen atmosphere to form an oxide film (post-oxide film) on the silicon substrate surface. May be.

  After depositing a silicon nitride film by about 10 nm by LPCVD or the like, the silicon nitride film is etched back by RIE to form a thin offset spacer 30a.

Subsequently, the gate oxide film 18 formed on the source / drain regions is removed by etching to expose the silicon substrate surface. Thereafter, a silicon film or a silicon germane film having the same crystal structure is selectively grown only on the exposed silicon surface by a selective epitaxial method to about 10 nm. For example, in order to selectively grow a silicon film, SiH ₂ Cl ₂ , H ₂ and HCl gas are used as reaction gases. Thus, as shown in FIG. 9C, the epitaxial layer 33 is formed on the source / drain regions and on the gate electrode 19.

Subsequently, as shown in FIG. 10D, for example, arsenic ions and boron ions are implanted into the NMOSFET region and the PMOSFET region using the gate electrode 19 and the offset spacer 30a as an ion implantation mask, respectively. In order to form an extension portion of the drain region, an arsenic ion implantation region 21g and a boron ion implantation region 22g are formed. For example, when arsenic ions are implanted into the NMOSFET region, the acceleration voltage is 1 KeV and the dose is 8E14 cm ⁻² . When boron or boron fluoride ions are implanted into the PMOSFET region, the effective acceleration voltage for boron is 0.5 KeV and the dose is 1E15 cm ⁻² . Due to the presence of the offset spacer 30a, the boron ion implantation region 22g is surely included in the fluorine diffusion region 20b.

  Thereafter, annealing is performed using the RTA method at, for example, about 800 ° C. for 10 seconds to activate the implanted ions, thereby forming the arsenic diffusion region 21f and the boron diffusion region 22f.

  Thus, in the fourth embodiment, since the structure in which the source / drain regions are lifted is formed, the depths of the arsenic diffusion region 21f and the boron diffusion region 22f constituting the extension portion with respect to the channel region are effectively set. Can be shallow. In the fourth embodiment, since the sidewall 25a is formed on the side wall of the gate electrode 19, the arsenic ion implantation region 21g and the boron ion implantation region 22g are included in the fluorine diffusion region 20b. Therefore, the presence of the pre-implanted fluorine diffusion region 20b suppresses the diffusion during annealing, and the shallow boron diffusion region 21h and the arsenic diffusion region 22h can be reliably formed.

  Further, as shown in FIG. 10 (e), a sidewall 25a is formed on the side wall of the gate electrode by a method according to the first embodiment, and then, as shown in FIG. 10 (f), this gate is formed. By using the electrode 19 and the sidewall 25a as an ion implantation mask, boron and phosphorus are ion-implanted into the PMOSFET region and the NMOSFET region, respectively, and then an activation process is performed using the RTA method, thereby forming an n-type impurity diffusion region. A type impurity diffusion region 26a and a p-type impurity diffusion region 27a are formed.

  Subsequently, the surface layer of the gate electrode and the surface layer of the source / drain region exposed on the surface are silicided by the method according to the first embodiment, and salicide is formed. Further, an interlayer insulating film and a necessary wiring layer are formed to complete the CMOSFET structure.

  Since the CMOSFET manufactured by the manufacturing method according to the fourth embodiment described above forms the fluorine diffusion region 20b before forming the boron ion implantation region 22g, boron diffusion during annealing is prevented. Since the boron diffusion region 22h having a steep concentration gradient at the lateral end can be formed with certainty, the short channel effect can be suppressed. Further, since the source / drain region is lifted with respect to the height of the channel region, the substantial junction interface between the source / drain regions can be shallowed. Therefore, it is possible to further suppress the short channel effect.

(Fifth embodiment)
The CMOSFET according to the fifth embodiment performs continuous fluorine diffusion between the source and drain regions under the gate electrode by performing fluorine ion implantation on substantially the entire surface of the substrate in the element formation region before forming the gate electrode. A region is formed.

  A method for manufacturing a CMOSFET according to the fifth embodiment will be described with reference to FIGS. An element isolation region 15a, a p-well 16 and an n-well 17 are formed in the silicon substrate 10 by a method according to the first embodiment. Thereafter, the surface of the silicon substrate is thermally oxidized to form a dummy gate oxide film 18a. As manufacturing conditions, a thermal oxidation method similar to a normal gate oxide film forming method can be used.

Next, as shown in FIG. 11A, fluorine ions are implanted into the substrate surface layer in the element formation region to form a fluorine ion implanted region 20c. As ion implantation conditions, for example, the ion acceleration voltage is set to 30 KeV, and the dose amount to 3 × 10 ¹⁴ cm ⁻² . Note that it is not necessary to perform oblique ion implantation or the like when performing ion implantation. As in the other embodiments, when fluorine ions are implanted, the gate electrode is not used as a mask, so that a continuous fluorine ion implantation region 20c is formed over the entire element formation region.

  Subsequently, the fluorine ion implantation region 20c is annealed to recover crystal defects introduced at the time of ion implantation, thereby forming a fluorine diffusion region 20d. As the annealing conditions, for example, an RTA method can be used, which is heated at 900 ° C. for 10 seconds.

  Thereafter, the dummy gate oxide film 18a is removed by etching, and the substrate surface is thermally oxidized again as shown in FIG. 11B, and the gate oxide film 18b and the gate oxide film 18b are formed in accordance with the manufacturing conditions according to the first embodiment. A gate electrode 19 is formed. Further, using the gate electrode 19 as an ion implantation mask, arsenic and boron are implanted into the p well 16 and the n well 17, respectively, to form an arsenic ion implanted region 21i and a boron ion implanted region 22i. Since the fluorine diffusion region 20d is formed at a substantially uniform depth in a wide range under the gate electrode 19, the arsenic ion implantation region 21i and the boron ion implantation region 22i can be reliably included in the fluorine diffusion region 20d. . Therefore, in the annealing step of the impurity ion implantation region, boron diffusion in the PMOSFET region can be reliably suppressed, and the boron diffusion region 22j having a steep impurity concentration gradient at the lateral end can be formed.

  In accordance with the manufacturing conditions according to the first embodiment, the gate electrode 19 and the sidewall 25 are formed, and an n-type impurity such as phosphorus or arsenic is added to the NMOSFET region using the gate electrode 19 and the sidewall 25 as an ion implantation mask. In the PMOSFET region, p-type impurities such as boron or boron fluoride are ion-implanted. As ion implantation conditions, conditions similar to the formation conditions of the deep impurity diffusion regions in the first or second embodiment can be used. Thereafter, annealing is performed to activate the implanted impurity ions. For the annealing, for example, a spike RTA process is performed with a peak temperature of 1050 ° C. Thus, as shown in FIG. 11C, the n-type impurity diffusion region 26 and the p-type impurity diffusion region 27, which are deep impurity diffusion regions, are formed in the NMOSFET region and the PMOSFET region, respectively.

  In the CMOSFET manufactured by the manufacturing method according to the fifth embodiment described above, the fluorine ion implantation 20c is formed in a wide region, so that the boron ion implantation region 22i can be easily and reliably made into the fluorine diffusion region 20d. Can be included. Therefore, boron diffusion during annealing can be reliably suppressed, and a boron diffusion region 22j having a steep concentration gradient at the lateral end can be formed. Therefore, the short channel effect can be effectively suppressed.

(Sixth embodiment)
In the first to sixth embodiments described above, a general silicon substrate is used, but instead of this substrate, an insulating layer 41 is provided on a silicon layer 40 as shown in FIG. An SOI substrate (Silicon on Insulator) having a silicon layer 42 on the insulating layer 41 can also be used. FIG. 12 is a cross-sectional view showing the structure of the CMOSFET according to the seventh embodiment using an SOI substrate. Even when an SOI substrate is used, the basic structure is common to the CMOSFET structure according to the first embodiment. However, when an SOI substrate is used, each element formation region is surrounded by the insulating layer 41 and the element isolation region 15b, and can be electrically separated from the adjacent element isolation region, so that a latch-up phenomenon that occurs in the CMOSFET structure. Can be prevented.

(Seventh embodiment)
The CMOSFET according to the seventh embodiment suppresses the short channel effect by implanting nitrogen (N) ions in advance before forming the extension portion of the source / drain region of the PMOSFET. That is, the seventh embodiment is characterized in that nitrogen is used as a diffusion suppressing element instead of fluorine.

  For steps other than the nitrogen ion implantation step, the conditions according to the first embodiment can be used as they are. That is, as shown in FIGS. 2A to 2D, after forming an element isolation region and defining an element formation region, a p well region and an n well region are formed, and channel ion implantation is performed. Thereafter, a gate insulating film is formed on the surface of each well, and a gate electrode is further formed on the gate insulating film.

Thereafter, nitrogen ion implantation is performed using the gate electrode as a mask. Also in this case, it is preferable to perform oblique ion implantation from an angle of 30 to 45 degrees with respect to the substrate normal. For example, the ion implantation is performed from an angle of 30 degrees with respect to the substrate normal from four directions rotating 90 degrees in the substrate plane. When performing, the acceleration voltage is set to 1 KeV to 30 KeV, and the dose amount is set to 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² . After ion implantation of nitrogen, heat treatment is performed at about 850 ° C. to 900 ° C. to recover crystal defects caused by the ion implantation, and a nitrogen diffusion region is formed.

  Subsequently, in order to form extension portions of the source / drain according to the manufacturing method according to the first embodiment, boron or boron fluoride is ion-implanted into the PMOSFET region, and arsenic is ion-implanted into the NMOSFET region. The boron diffusion region and the arsenic diffusion region are formed by performing the RTA process. Note that phosphorus may be injected instead of arsenic.

  By this RTA treatment, crystal defects in each impurity ion implantation region are recovered and boron is diffused, but the diffusion of boron is suppressed by the presence of nitrogen implanted in the previous step. The reason is not clear, but it is expected that the activation of boron during annealing is suppressed as in the case of fluorine, and as a result, the boron diffusion distance during annealing is shortened.

  As in the case of the first embodiment in which fluorine ions are implanted, the diffusion of boron is suppressed by the presence of the previously implanted nitrogen, and in particular, the boron concentration gradient at the lateral end extending under the gate electrode. Can be maintained.

  Further, a side wall is formed on the side wall of the gate electrode by the method according to the first embodiment, and boron and phosphorus are ion-implanted in the PMOSFET region and the NMOSFET region, respectively, using the gate electrode and the side wall as an ion implantation mask. Subsequently, deep n-type and p-type impurity diffusion regions are formed by performing an activation process using the RTA method.

  Subsequently, the surface layer of the gate electrode and the surface layer of the source / drain region exposed on the surface are silicided by the method according to the first embodiment, and salicide is formed. Further, an interlayer insulating film and a necessary wiring layer are formed to complete the CMOSFET structure. The obtained CMOSFET structure corresponds to the CMOSFET structure according to the first embodiment shown in FIG. 1 in which the fluorine diffusion region is replaced with a nitrogen diffusion region.

  In addition, although it demonstrated along the manufacturing method according to 1st Embodiment, it can use nitrogen ion implantation instead of fluorine ion implantation in the manufacturing method according to 2nd-6th embodiment. it can.

(Eighth embodiment)
The CMOSFET according to the eighth embodiment suppresses the short channel effect by implanting carbon (C) ions in advance before forming the extension portion of the source / drain region of the PMOSFET. That is, the seventh embodiment is characterized in that carbon is used instead of fluorine as a diffusion suppressing element.

  For steps other than the carbon ion implantation step, the conditions according to the first embodiment can be used as they are. That is, as shown in FIGS. 2A to 2D, after forming an element isolation region and defining an element formation region, a p well region and an n well region are formed, and channel ion implantation is performed. Thereafter, a gate insulating film is formed on the surface of each well, and a gate electrode is further formed on the gate insulating film.

Carbon ion implantation is performed using the gate electrode as a mask. Also in this case, it is preferable to perform oblique ion implantation from an angle of 30 to 45 degrees with respect to the substrate normal. For example, the ion implantation is performed from an angle of 30 degrees with respect to the substrate normal from four directions rotating 90 degrees in the substrate plane. When performing, the acceleration voltage is 1 KeV to 30 KeV, and the dose is 1 × 10 ¹² cm ⁻² 1 × 10 ¹⁴ cm ⁻² . After ion implantation of carbon, heat treatment is performed at about 850 ° C. to 900 ° C. to recover crystal defects caused by the ion implantation.

  Thereafter, boron or boron fluoride is ion-implanted into the PMOSFET region and arsenic is ion-implanted into the NMOSFET region in order to form source / drain extension portions according to the manufacturing method according to the first embodiment. The boron diffusion region and the arsenic diffusion region are formed by performing the RTA process. Note that phosphorus may be ion-implanted instead of arsenic.

  This RTA treatment recovers crystal defects in each impurity ion implantation region and causes diffusion of impurity ions. However, diffusion of impurity ions is suppressed by the presence of carbon implanted in the previous step. If carbon is previously implanted in this way, the carbon selectively captures Si existing between the lattices that causes the accelerated diffusion of boron and functions as a sink for interstitial silicon. The number of interstitial silicon can be reduced. As a result, the number of boron that diffuses at a high speed in pairs with interstitial silicon is reduced, and the diffusion of impurity ions is suppressed. Thus, carbon is considered to bring about the same effect of suppressing the diffusion of boron by a mechanism different from that of fluorine and nitrogen. Thus, as in the case of the first embodiment in which fluorine ions are implanted, the accelerated diffusion of boron is suppressed by the presence of the previously implanted carbon, and the end of the boron diffusion region, particularly under the gate electrode, is suppressed. The spreading in the lateral direction is suppressed, and a boron diffusion region having a steep concentration gradient at the end can be obtained.

  Further, a side wall is formed on the side wall of the gate electrode by the method according to the first embodiment, and boron and phosphorus are ion implanted into the PMOSFET region and the NMOSFET region, respectively, using the gate electrode and the side wall as an ion implantation mask. Then, deep impurity diffusion regions are formed by performing an activation process using the RTA method.

  Subsequently, the surface layer of the gate electrode and the surface layer of the source / drain region exposed on the surface are silicided by the method according to the first embodiment, and salicide is formed. Further, an interlayer insulating film and a necessary wiring layer are formed to complete the CMOSFET structure. The obtained CMOSFET structure is obtained by replacing the fluorine diffusion region with the carbon diffusion region in the CMOSFET structure according to the first embodiment shown in FIG.

  In addition, although it demonstrated along the manufacturing method according to 1st Embodiment mainly, also in the manufacturing method according to 2nd-6th embodiment, carbon ion implantation was carried out instead of fluorine ion implantation. Can be used.

(Other embodiments)
Although the first to eighth embodiments have been described above, the conditions of each annealing step are not limited to the above-described conditions. For example, although the RTA method is mainly used in the above-described embodiment in the annealing step, annealing may be performed with light irradiation in a very short time of several hundreds μs to 10 ms using a xenon flash lamp or an excimer laser. it can. As described above, when high-temperature annealing in a shorter time is used as compared with RTA, the impurity can be activated with little diffusion of the ion-implanted impurity. Therefore, almost no diffusion in the depth direction and the lateral direction occurs, and an extension portion having a steep concentration gradient can be formed. Therefore, when used in combination with the above-described embodiment, the suppression of the short channel effect can be further improved.

  In addition, the fluorine ion implantation effect described in the above-described embodiment of the present invention can be applied not only to a normal planar type transistor but also to a FinFET that is attracting attention as a next generation type transistor. A FinFET has a rectangular semiconductor layer covered with an insulating film on an insulating substrate, and has a structure covered with a strip-shaped conductive film in a direction intersecting the major axis direction of the rectangular semiconductor layer. is there. The conductive film is used as a gate electrode, and the insulating film between the gate electrode and the semiconductor layer is used as a gate insulating film. Source / drain regions are formed in the semiconductor layers on both sides of the gate electrode.

  For example, in such a FinFET, the upper silicon layer of the SOI substrate is etched to form the rectangular semiconductor layer, and the surface of the semiconductor layer is thermally oxidized to form an oxide film on the surface of the semiconductor layer. Then, a gate electrode covering the semiconductor layer is formed. Further, the source / drain regions can be formed by ion implantation of impurities using the gate electrode as a mask and an annealing process. Also in this case, when the PMOSFET is formed in advance, since boron diffusion can be prevented by ion implantation of fluorine, nitrogen or carbon in advance when boron ion implantation is performed, the source / drain region adjacent to the channel region can be prevented. An impurity concentration distribution having a steep impurity concentration at the end can be obtained, and a short channel effect can be prevented.

  As described above, the semiconductor device and the manufacturing method thereof of the present invention have been described according to the embodiment of the present invention. However, the semiconductor device and the manufacturing method of the present invention are not limited to the above description, and various modifications can be made. Is possible.

It is sectional drawing of the apparatus which shows the structure of CMOSFET which concerns on the 1st Embodiment of this invention. It is sectional drawing of the apparatus in each process which shows the process of the manufacturing method of CMOSFET which concerns on the 1st Embodiment of this invention. It is sectional drawing of the apparatus in each process which shows the process of the manufacturing method of CMOSFET which concerns on the 1st Embodiment of this invention. It is sectional drawing of the apparatus in each process which shows the process of the manufacturing method of CMOSFET which concerns on the 1st Embodiment of this invention. It is sectional drawing of the apparatus in each process which shows the process of the manufacturing method of CMOSFET which concerns on the 1st Embodiment of this invention. It is a graph which shows the roll-off characteristic of the threshold voltage of PMOSFET which concerns on the 1st Embodiment of this invention. It is sectional drawing of the apparatus in each process which shows the process of the manufacturing method of CMOSFET which concerns on the 2nd Embodiment of this invention. It is apparatus sectional drawing in each process which shows the formation process of the source / drain region based on the manufacturing method of CMOSFET which concerns on the 3rd Embodiment of this invention. It is apparatus sectional drawing in each process which shows the formation process of a source / drain region based on the manufacturing method of CMOSFET which concerns on the 4th Embodiment of this invention. It is apparatus sectional drawing in each process which shows the formation process of a source / drain region based on the manufacturing method of CMOSFET which concerns on the 5th Embodiment of this invention. It is apparatus sectional drawing in each process which shows the formation process of the source / drain area | region based on the manufacturing method of CMOSFET which concerns on the 6th Embodiment of this invention. It is apparatus sectional drawing which shows the structure of CMOSFET which concerns on the 7th Embodiment of this invention.

Explanation of symbols

10 silicon substrate 15a element isolation region 15 oxide film 16 p well 17 n well 18 gate oxide film 19 gate electrodes 20a, 20c fluorine ion implantation region 20b, 20d fluorine diffusion region 21a boron ion implantation region 21b boron diffusion region 22a arsenic ion implantation region 22b Arsenic diffusion region 23a Pocket ion implantation region 24a Pocket ion implantation region 25 Side wall 26 p-type impurity diffusion region 27 n-type impurity diffusion region 28 Salicide 30 Offset spacer 31 Wiring 32 Wiring
33 Epitaxial layer 40 Silicon layer 41 Silicon oxide film layer 42 Silicon layer

Claims (5)

An n-well region formed in a semiconductor substrate; a gate electrode formed on the n-well region;
A boron diffusion region formed in a surface layer of the n-well at both ends of the gate electrode;
A diffusion suppressing element in which at least one diffusion suppressing element selected from the group consisting of fluorine, nitrogen, and carbon, which includes the boron diffusion region at least in the lateral direction below the gate electrode from the boron diffusion region, is diffused. A diffusion region;
A semiconductor device having a p-type impurity diffusion region deeper than the boron diffusion region and having a lateral end located farther from the gate electrode end than a lateral end of the boron diffusion region. Forming an n-well region in a substrate surface layer of a semiconductor substrate;
Forming a gate oxide film and a gate electrode on the n-well region;
A step of ion-implanting at least one diffusion suppressing element selected from the group consisting of fluorine, nitrogen, and carbon into the surface layer of the n-well region to form a diffusion suppressing element ion-implanted region;
Annealing the diffusion suppression element ion implantation region to form a diffusion suppression element diffusion region;
After the diffusion suppression element ion implantation region is formed, boron or a boron compound is ion-implanted into the surface layer of the n-well region to form a boron ion implantation region included in the diffusion suppression element diffusion region;
Annealing the boron ion implantation region; forming a sidewall with an insulating film on a side surface of the gate electrode;
Using the gate electrode and the sidewall as an implantation mask, implanting p-type impurity ions to form a p-type impurity ion implantation region deeper than the boron ion implantation region, and annealing the p-type impurity ion implantation region And a method of manufacturing a semiconductor device. The step of forming the gate oxide film and the gate electrode is performed before the step of forming the diffusion suppressing element ion implantation region,
3. The semiconductor device according to claim 2, wherein the ion implantation for forming the diffusion-inhibiting element ion implantation region is performed by implanting ions from an oblique direction with respect to a substrate surface normal using the gate electrode as an implantation mask. Production method. Furthermore, after forming the diffusion suppressing element ion implantation region, before the step of forming the boron ion implantation region, there is a step of forming an insulating film sidewall thinner than the sidewall on the side surface of the gate electrode,
4. The method of manufacturing a semiconductor device according to claim 2, wherein the boron or boron compound ion implantation uses the gate electrode and the insulating film sidewall as an implantation mask. Forming the sidewall, forming the p-type impurity ion implantation region, and annealing the p-type impurity ion implantation region.
The method for manufacturing a semiconductor device according to claim 2, wherein the method is performed before the step of forming the boron ion implantation region.

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