JP2010153501A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variation in the thresholds of a MISFET. <P>SOLUTION: An element separation region 2 is formed on a semiconductor substrate 1. After performing channel dope ion implantation for adjusting the threshold of the MISFET, gate insulating films 5a, 5b and gate electrodes GE1, GE2 are formed. Then, extension regions 7a, 7b and halo regions 8a, 8b are formed by ion implantation, and moreover, diffusion preventing regions 10a, 10b are formed by the ion implantation of one or more kinds from among carbon (C), nitrogen (N), and fluorine (F). Then, after forming sidewalls SW on the sidewalls of the gate electrodes GE1, GE2, n<SP>+</SP>-type semiconductor region 11a and p<SP>+</SP>-type semiconductor region 11b for source-drain are formed by the ion implantation, thereby forming an n-channel type MISFET and a p-channel type MISFET. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device having a MISFET.

  A semiconductor device is manufactured by forming a semiconductor element such as a MISFET on a semiconductor substrate, forming a multilayer wiring structure on the semiconductor substrate, and connecting the semiconductor elements.

  Japanese Patent Laying-Open No. 2008-42059 (Patent Document 1) discloses a highly reliable semiconductor device in which variation in transistor characteristics due to random components is suppressed in a semiconductor device including at least a MIS transistor having a retrograde channel structure and its Techniques providing manufacturing methods are described.

  Japanese Patent Laying-Open No. 2008-47698 (Patent Document 2) describes a technology related to a semiconductor memory device capable of suppressing an increase in variation in transistor characteristics due to miniaturization.

  International Publication No. 2004/076673 pamphlet (Patent Document 3) describes a technique for suppressing variations in operating speed by controlling the substrate potential of a MOS transistor.

Non-Patent Document 1 describes a technique related to variations in threshold values of MOSFETs.
JP 2008-42059 A JP 2008-47698 A International Publication No. 2004/076673 Pamphlet K. Takeuchi, T. Tsunomura, AT Putra, A. Nishida, S. Kamohara, Tea Hiramoto ( T. Hiramoto), “Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies” “2007 INTERNATIONAL ELECTRON DEVICES MEETING (IEDM 2007) ) ", (USA), 2007, p. 467

  According to the study of the present inventor, the following has been found.

  A semiconductor device having a MISFET can be manufactured as follows. That is, an element isolation region is formed in a semiconductor substrate, and channel doping ion implantation for adjusting the threshold value of the MISFET is performed in an active region defined by the element isolation region, and then a gate insulating film and a gate electrode are formed. To do. Then, an extension region for LDD and a halo region are formed by ion implantation using the gate electrode as a mask, and then a sidewall insulating film is formed on the sidewall of the gate electrode, and the gate electrode and the sidewall insulating film are used as a mask. By implantation, source / drain regions having a higher impurity concentration than the extension region are formed. Thereafter, a metal silicide layer is formed on the source / drain regions by a salicide process.

  In general, in an n-channel MISFET using a gate electrode made of polycrystalline silicon to which an n-type impurity is added, boron (B) is used for channel doping ion implantation. However, when boron (B) is used for channel-doped ion implantation, the threshold variation of the actually formed MISFET is larger than the threshold variation calculated by the discreteness of the channel-doped impurity distribution. It is known from Non-Patent Document 1 above.

  The inventor examined the reason why the threshold variation of the MISFET formed by a general technique shows a larger value than the threshold variation calculated by the discreteness of the distribution of the channel-doped impurities. I found the following. That is, when channel-doped ions are implanted into a semiconductor substrate, the implanted impurities are randomly arranged at the stage immediately after the implantation. However, when impurities are diffused (moved) in various subsequent heating processes, the impurities are randomly arranged. Collapses, and the impurity distribution is biased compared to immediately after the implantation. In other words, in the stage immediately after the channel dope ion implantation, the randomness of the implanted impurity is high, but if the impurity diffuses (moves) in the subsequent various heating processes, the randomness of the impurity is reduced. It will end up.

  In addition, in a state where the randomness of the arrangement of impurities is high, the impurities are not arranged uniformly (regularly) microscopically (at the level of atomic arrangement) but are present in a random (random) manner. However, since they are microscopically random, the impurities are distributed equally in a macroscopic manner (channel region level). For this reason, in a state where the randomness of the impurity arrangement is high, the difference in impurity distribution (difference between the impurity distribution in the channel region of one MISFET and the impurity distribution in the channel region of another MISFET) when the channel regions are compared with each other. Small, variation in threshold of MISFET is small. However, if the randomness of the impurity arrangement decreases, this state collapses, and the macroscopic impurity distribution (impurity distribution at the channel region level) is biased. Therefore, in the state where the randomness of the impurity arrangement is lowered by thermal diffusion after the implantation, the difference in impurity distribution when comparing the channel regions (impurity distribution in the channel region of one MISFET and the channel region of another MISFET) The difference between the impurity distribution and the MISFET becomes large.

  As described above, in the MISFET formed by a general technique, the dispersion of the threshold value of the MISFET becomes large because the arrangement of the impurity implanted with the channel dope ion reduces the randomness by the thermal diffusion after the implantation. . If the variation in the threshold value of the MISFET is large, the performance of the semiconductor device is degraded. Therefore, it is desired to improve the performance of the semiconductor device by suppressing the variation in the threshold value of the MISFET.

  In the above-mentioned Patent Document 1, in order to reduce the variation in the characteristics of the MISFET, a countermeasure is taken by applying modulation to the impurity profile for channel-doped ion implantation. This technique is partially effective because the distribution of channel impurities near the surface of the semiconductor substrate has the greatest influence on the variation in the characteristics of the MISFET. However, unless the device is improved to increase the randomness of the channel impurity arrangement (distribution), the actual MISFET characteristic variation can be reduced to the characteristic (threshold value) variation level explained by the discrete impurity distribution. Have difficulty.

  In Patent Document 2, the influence of variations in transistor characteristics is avoided by increasing the gate length and gate width of the minimum transistor of a memory cell in which variations in device characteristics are a problem. However, this method is not a fundamental solution for improving variations in transistor characteristics (thresholds), and makes it difficult to miniaturize transistors (miniaturize semiconductor devices).

  In the above-mentioned Patent Document 3, a change in threshold value is dealt with by controlling the substrate potential. However, when variation in characteristics due to discrete impurities becomes a problem, the difference in characteristics between adjacent transistors is large. In a semiconductor device in which a large number of transistors are formed, the characteristics of individual transistors by controlling the substrate potential It is difficult to control the variation of (threshold).

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device by suppressing variations in threshold values of MISFETs.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to a representative embodiment includes (a) a step of preparing a semiconductor substrate, (b) a step of ion implantation for adjusting the threshold value of the first MISFET into the semiconductor substrate, (c) ) Forming a first insulating film for the gate insulating film of the first MISFET on the main surface of the semiconductor substrate; (d) forming a first gate electrode of the first MISFET on the first insulating film; e) After the step (d), ion implantation is performed on the semiconductor substrate using the first gate electrode as a mask to form a first semiconductor region of a first conductivity type in the semiconductor substrate, (f) the step (d) ) After the step, the step of ion-implanting the first element into the semiconductor substrate, (g) After the step (e) and the step (f), a step of forming a sidewall insulating film on the sidewall of the first gate electrode , (H) ago Performing ion implantation on the semiconductor substrate using the first gate electrode and the sidewall insulating film as a mask to form a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region in the semiconductor substrate; have. The first and second semiconductor regions function as a semiconductor region for the source or drain of the first MISFET, and the first element ion-implanted in the step (f) is carbon, nitrogen, or fluorine. At least a part of the region where the first element is introduced in the step (f) is located between the channel region of the first MISFET and the first semiconductor region.

  According to another exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a semiconductor layer into which one or more of carbon, nitrogen, and fluorine are introduced at the top, and MISFET in the semiconductor layer Is formed.

  Further, the semiconductor device manufacturing method according to another representative embodiment includes (a) a step of preparing a semiconductor substrate, (b) a gate insulating film of a first MISFET on the main surface of the semiconductor substrate after the step (a). Forming a first insulating film for the semiconductor substrate, (c) forming a first conductor layer on the first insulating film after the step (b), (d) forming the semiconductor substrate on the semiconductor substrate after the step (c) Performing ion implantation for adjusting the threshold value of the first MISFET, (e) forming a second conductor layer on the first conductor layer after the step (d), and (f) the second conductivity. Forming a first gate electrode of the first MISFET by patterning a body layer and the first conductor layer; (g) a semiconductor region for the source or drain of the first MISFET on the semiconductor substrate after the step (f); The process of forming It is intended to.

  Further, a method of manufacturing a semiconductor device according to another representative embodiment includes (a) a step of preparing a semiconductor substrate, (b) a step of performing ion implantation for adjusting a threshold value of a MISFET in the semiconductor substrate, c) forming a first insulating film for a gate insulating film on the main surface of the semiconductor substrate; (d) forming a gate electrode on the first insulating film; and (e) a source or drain on the semiconductor substrate. Forming a semiconductor region. In addition, as the element to be ion-implanted in the step (b), one or both of indium and gallium, or an element in which boron is added thereto is used.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the typical embodiment, it is possible to improve the performance of the semiconductor device by suppressing the variation in the threshold value of the MISFET.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
A manufacturing process of the semiconductor device of the present embodiment will be described with reference to the drawings. FIG. 1 to FIG. 15 are cross-sectional views of a principal part during a manufacturing process of a semiconductor device according to an embodiment of the present invention, here, a semiconductor device having a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor).

  First, as shown in FIG. 1, a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared. Then, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. The element isolation region 2 is made of an insulator such as silicon oxide, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation region 2 can be formed by an insulating film embedded in a groove (element isolation groove) formed in the semiconductor substrate 1. The element isolation region 2 forms an nMIS formation region 1A, which is a region (active region) where an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qn is formed, and a p-channel MISFET Qp. A pMIS formation region 1B which is a region (active region) is defined.

  Next, after forming a thin insulating film (through film) 3 for preventing surface contamination on the surface (main surface) of the semiconductor substrate 1, as shown in FIG. 2, a photoresist covering the pMIS formation region 1B. A film (photoresist pattern) RP1a is formed using a photolithography technique. The nMIS formation region 1A is exposed without being covered with the photoresist film RP1a. The photoresist film RP1a can function as an ion implantation blocking mask for the pMIS formation region 1B.

  Next, in the nMIS formation region 1A, ion implantation for adjusting a threshold value of an n channel MISFET Qn (that is, channel dope ion implantation) IM1a is performed on the upper layer portion of the semiconductor substrate 1 later. In FIG. 2, the channel dope ion implantation IM1a is schematically indicated by an arrow.

  The ion implantation for adjusting the threshold value of the MISFET can also be referred to as channel doping ion implantation. By this channel doping ion implantation (ion implantation for adjusting the threshold value), impurities are introduced (doped) into the channel region of the MISFET. Is done. That is, in channel dope ion implantation, impurities (impurity ions) are introduced (doped) into a region including the channel region of the MISFET. The “channel region of the MISFET” here corresponds to a region that becomes a channel region of the MISFET when the MISFET is formed afterwards even though the MISFET is not formed at the channel doping ion implantation stage. This is common to channel dope ion implantation (threshold adjustment ion implantation) described in the first embodiment and the following second to sixth embodiments.

  In the ion implantation IM1a for adjusting the threshold, that is, the channel dope ion implantation IM1a, impurities (impurity ions) are introduced (ion implantation) into a region including the channel region of the n-channel MISFET Qn to form the channel dope layer 4a. Is done. The channel dope layer 4a includes a region that later becomes a channel region of the n-channel type MISFET Qn. As an impurity introduced into the channel dope layer 4a by the channel dope ion implantation IM1a, for example, a p-type impurity such as boron (B) can be used. In this channel dope ion implantation IM1a, the photoresist film RP1a covering the pMIS formation region 1B functions as an ion implantation blocking mask, so that ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B.

  Next, in the nMIS formation region 1A, a p-type well (p-type semiconductor region) PW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth. The p-type well PW is formed by, for example, ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate 1 in the nMIS formation region 1A using the photoresist film RP1a covering the pMIS formation region 1B as an ion implantation blocking mask. Can be formed. The channel dope layer 4a is formed shallow in the upper layer portion of the semiconductor substrate 1, and the p-type well PW is formed deeper than the channel dope layer 4a in the semiconductor substrate 1. As another form, the p-type well PW can be formed by ion implantation first, and then the channel dope ion implantation IM1a can be used to form the channel dope layer 4a. This is also the case with the following second to fourth embodiments. It is the same.

  Next, as shown in FIG. 3, after removing the photoresist film RP1a by ashing or the like, a photoresist film (photoresist pattern) RP1b covering the nMIS formation region 1A is formed by using a photolithography technique. The pMIS formation region 1B is exposed without being covered with the photoresist film RP1b. The photoresist film RP1b can function as an ion implantation blocking mask for the nMIS formation region 1A.

  Next, in the pMIS formation region 1B, ion implantation for adjusting a threshold value of a p-channel type MISFET Qp to be formed later (that is, channel dope ion implantation) IM1b is performed on the upper layer portion of the semiconductor substrate 1. In FIG. 3, the channel dope ion implantation IM1b is schematically indicated by an arrow.

  In the ion implantation IM1b for adjusting the threshold, that is, the channel dope ion implantation IM1b, impurities (impurity ions) are introduced (ion implantation) into a region including the channel region of the p-channel MISFET Qp to form the channel dope layer 4b. Is done. This channel dope layer 4b includes a region that will later become a channel region of the p-channel type MISFET Qp. As an impurity introduced into the channel dope layer 4b by channel dope ion implantation, for example, an n-type impurity such as phosphorus (P) can be used. In this channel dope ion implantation IM1b, the photoresist film RP1b covering the nMIS formation region 1A functions as an ion implantation blocking mask, so that ions are not implanted into the semiconductor substrate 1 in the nMIS formation region 1A.

  Next, in the pMIS formation region 1B, an n-type well (n-type semiconductor region) NW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth. The n-type well NW is formed by, for example, ion-implanting n-type impurities such as phosphorus (P) into the semiconductor substrate 1 in the pMIS formation region 1B using the photoresist film RP1b covering the nMIS formation region 1A as an ion implantation blocking mask. Can be formed. The channel dope layer 4b is formed shallow in the upper layer portion of the semiconductor substrate 1, and the n-type well NW is formed deeper than the channel dope layer 4b in the semiconductor substrate 1. As another form, the n-type well NW can be formed by ion implantation first, and then the channel dope ion implantation IM1b can be used to form the channel dope layer 4b. This is also the case in the following second to fourth embodiments. It is the same. As yet another form, after the channel dope layer 4b and the n-type well NW are first formed in the pMIS formation region 1B, the channel dope layer 4a and the p-type well PW can be formed in the nMIS formation region 1A. The same applies to the following second to fourth embodiments.

  Next, as shown in FIG. 4, after removing the photoresist film RP <b> 1 b by ashing or the like, the insulating film 3 is removed by wet etching using a hydrofluoric acid (HF) aqueous solution, for example. After the surface is cleaned (washed), the gate insulating film is formed on the surface of the semiconductor substrate 1 (main surface, here, the surface of the p-type well PW and the n-type well NW) in the nMIS formation region 1A and the pMIS formation region 1B. An insulating film (first insulating film) 5 is formed. This insulating film 5 will later become a gate insulating film of the n-channel MISFET Qn and the p-channel MISFET Qp. The insulating film 5 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method.

  Next, on the entire main surface of the semiconductor substrate 1 (that is, on the insulating film 5 in the nMIS formation region 1A and the pMIS formation region 1B), a silicon film such as a polycrystalline silicon film is formed as a conductor film for forming a gate electrode. A film 6 is formed. The nMIS formation region 1A (region to be a gate electrode GE1 described later) in the silicon film 6 is an n-type impurity such as phosphorus (P) or arsenic (As) using a photoresist film (not shown) as a mask. Is ion-implanted to form a low-resistance n-type semiconductor film (doped polysilicon film). Further, the pMIS formation region 1B (region to be a gate electrode GE2 described later) in the silicon film 6 is made of p-type impurities such as boron (B) using another photoresist film (not shown) as a mask. By ion implantation or the like, a low-resistance p-type semiconductor film (doped polysilicon film) is obtained. Further, the silicon film 6 can be changed from an amorphous silicon film at the time of film formation to a polycrystalline silicon film by heat treatment after film formation (after ion implantation).

  Next, as shown in FIG. 5, the silicon film 6 is patterned using a photolithography method and a dry etching method, thereby forming gate electrodes GE1 and GE2.

  The gate electrode GE1 serving as the gate electrode of the n-channel type MISFET Qn is made of polycrystalline silicon (n-type semiconductor film, doped polysilicon film) into which an n-type impurity is introduced, and the p-type well PW (of the nMIS formation region 1A) An insulating film 5 is formed on the upper channel doped layer 4a). The insulating film 5 remaining under the gate electrode GE1 becomes the gate insulating film 5a of the n-channel type MISFET Qn. That is, the gate electrode GE1 is formed on the insulating film 5 (that is, the gate insulating film 5a) in the nMIS formation region 1A. Further, the gate electrode GE2 serving as the gate electrode of the p-channel type MISFET Qp is made of polycrystalline silicon (p-type semiconductor film, doped polysilicon film) into which p-type impurities are introduced, and the n-type well NW in the pMIS formation region 1B. (On the upper channel doped layer 4b) with an insulating film 5 interposed therebetween. The insulating film 5 remaining under the gate electrode GE2 becomes the gate insulating film 5b of the p-channel type MISFET Qp. That is, the gate electrode GE2 is formed on the insulating film 5 (that is, the gate insulating film 5b) in the pMIS formation region 1B.

  Next, as shown in FIG. 6, a photoresist film (photoresist pattern) RP2a covering the pMIS formation region 1B is formed using a photolithography technique. The nMIS formation region 1A is exposed without being covered with the photoresist film RP2a. The photoresist film RP2a can function as an ion implantation blocking mask for the pMIS formation region 1B. For this reason, in ion implantation IM2a, IM3a, and IM4a described later, the photoresist film RP2a functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B.

Next, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into regions on both sides of the gate electrode GE1 of the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. A pair of extension regions (first semiconductor region, source / drain extension region, n ⁻ type semiconductor region) 7 a is formed. The extension region 7a is an n-type semiconductor region, and has an impurity concentration lower than that of the n ⁺ -type semiconductor region 11a to be formed later. In FIG. 6, ion implantation IM2a for forming the extension region 7a is schematically indicated by an arrow. In this ion implantation IM2a, since the gate electrode GE1 can also function as a mask (ion implantation blocking mask), the extension region 7a is formed in alignment with the gate electrode GE1 (side wall thereof) and directly below the gate electrode GE1. No impurities are introduced (ion implantation). The depth (junction depth) of the extension region 7a is shallower than the depth (junction depth) of the n ⁺ type semiconductor region 11a to be formed later. Further, the ion implantation IM2a for forming the extension region 7a is preferably not the oblique ion implantation but the ion implantation in the direction perpendicular to the main surface of the semiconductor substrate 1.

  Next, as shown in FIG. 7, p-type impurity ion implantation (halo ion implantation) IM3a is performed on the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A to form a halo region (p-type semiconductor region) 8a. Form. In FIG. 7, ion implantation (halo ion implantation) IM3a for forming the halo region 8a is schematically indicated by an arrow. The halo region 8a has a conductivity type opposite to that of the extension region 7a and the same conductivity type as that of the p-type well PW, and is a p-type (p-type semiconductor region) here. The halo region 8a is formed to suppress short channel characteristics. In the ion implantation IM3a for forming the halo region 8a, the gate electrode GE1 can also function as a mask (ion implantation blocking mask). The halo region 8a is formed so as to enclose (cover) the extension region 7a, and has an impurity concentration (p-type impurity concentration) higher than that of the p-type well PW. The ion implantation IM3a for forming the halo region 8a is more preferably an oblique ion implantation (gradient ion implantation), whereby the halo region 8a is accurately formed so as to wrap (cover) the extension region 7a. Can do. In general ion implantation, impurity ions are accelerated and implanted in a direction perpendicular to the main surface of the semiconductor substrate 1. In oblique ion implantation, a predetermined direction from a direction perpendicular to the main surface of the semiconductor substrate 1 is used. Impurity ions are accelerated and implanted in an inclined direction.

Next, as shown in FIG. 8, the diffusion prevention region 10a is formed by ion implantation IM4a of the first element in the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. In FIG. 8, the ion implantation IM4a for forming the diffusion prevention region 10a is schematically indicated by an arrow. In this ion implantation IM4a, the gate electrode GE1 can also function as a mask (ion implantation blocking mask). The diffusion preventing region 10a is a region where the first element is introduced (doped). The first element implanted into the semiconductor substrate 1 by the ion implantation IM4a for forming the diffusion prevention region 10a is made of one or more of carbon (C), nitrogen (N), and fluorine (F). The concentration of the first element in the diffusion preventing region 10a is, for example, about 5 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ^{2 in} terms of the implantation amount (dose amount) of the ion implantation IM4a, and in the volume concentration, for example, 1 × 10 ¹⁸ to 1 × 10. It can be about ²⁰ / cm ³ .

The diffusion prevention region 10a prevents point defects generated by ion implantation when forming the extension region 7a, the halo region 8a, and an n ⁺ type semiconductor region 11a described later from diffusing into the channel region of the n channel MISFET Qn. It has a function to prevent. For this reason, at least a part of the diffusion prevention region 10a needs to be located between the extension region 7a, the halo region 8a, the n ⁺ type semiconductor region 11a described later, and the channel region of the n channel MISFET Qn. . Therefore, it is preferable to form the diffusion preventing region 10a so as to wrap (cover) the halo region 8a.

  For this reason, in the ion implantation IM4a for forming the diffusion prevention region 10a, it is preferable to ion-implant the first element at a position deeper than the halo region 8a. Further, the ion implantation IM4a for forming the diffusion prevention region 10a is preferably oblique ion implantation (tilted ion implantation). As a result, the diffusion prevention region 10a can be accurately positioned between the halo region 8a and the channel region of the n-channel type MISFET Qn.

  Further, it is more preferable that the inclination angle of the ion implantation IM4a for forming the diffusion prevention region 10a is larger than the inclination angle of the ion implantation IM3a for forming the halo region 8a. As a result, the diffusion prevention region 10a can be positioned more accurately between the halo region 8a and the channel region of the n-channel type MISFET Qn. Here, the tilt angle of ion implantation corresponds to the tilt angle from the direction perpendicular to the main surface of the semiconductor substrate 1 in the ion implantation direction, and when impurity ions are implanted in the direction perpendicular to the main surface of the semiconductor substrate 1. The tilt angle is 0 °.

  Next, as shown in FIG. 9, after removing the photoresist film RP2a by ashing or the like, a photoresist film (photoresist pattern) RP2b covering the nMIS formation region 1A is formed by using a photolithography technique. The pMIS formation region 1B is exposed without being covered with the photoresist film RP2b. The photoresist film RP2b can function as an ion implantation blocking mask for the nMIS formation region 1A. For this reason, in ion implantation IM2b, IM3b, and IM4b described later, the photoresist film RP2b functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the nMIS formation region 1A.

Next, a p-type impurity such as boron (B) is ion-implanted into regions on both sides of the gate electrode GE2 of the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B, thereby (a pair of) extension regions. (First semiconductor region, source / drain extension region, p ⁻ type semiconductor region) 7b is formed. The extension region 7b is a p-type semiconductor region, and has an impurity concentration lower than that of the p ⁺ -type semiconductor region 11b to be formed later. An ion implantation IM2b for forming the extension region 7b, an ion implantation IM3b for forming a halo region 8b described later, and an ion implantation IM4b for forming a diffusion prevention region 10b described later are respectively separate. Although it is performed as an ion implantation process, in FIG. 9, it is schematically shown by an arrow together.

In the ion implantation IM2b for forming the extension region 7b, the gate electrode GE2 can also function as a mask (ion implantation blocking mask). Therefore, the extension region 7b is formed in alignment with the gate electrode GE2 (side wall thereof). Impurities are not introduced (ion implantation) immediately below the gate electrode GE2. The depth (junction depth) of the extension region 7b is shallower than the depth (junction depth) of the p ⁺ type semiconductor region 11b to be formed later. Further, the ion implantation IM2b for forming the extension region 7b is preferably not ion implantation but oblique implantation in a direction perpendicular to the main surface of the semiconductor substrate 1.

  Next, n-type impurity ion implantation (halo ion implantation) IM3b is performed on the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B to form a halo region (n-type semiconductor region) 8b. The halo region 8b has a conductivity type opposite to that of the extension region 7b and the same conductivity type as that of the n-type well NW, and here is an n-type (n-type semiconductor region). The halo region 8b is formed for suppressing short channel characteristics. In the ion implantation IM3b for forming the halo region 8b, the gate electrode GE2 can also function as a mask (ion implantation blocking mask). The halo region 8b is formed so as to enclose (cover) the extension region 7b, and has an impurity concentration (n-type impurity concentration) higher than that of the n-type well NW. The ion implantation IM3b for forming the halo region 8b is more preferably an oblique ion implantation (gradient ion implantation), whereby the halo region 8b is accurately formed so as to wrap (cover) the extension region 7b. Can do.

Next, a first element ion implantation IM4b is performed on the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B to form a diffusion prevention region 10b. The diffusion prevention region 10b is a region into which the first element is introduced (doped). During the ion implantation IM4b, the gate electrode GE2 can also function as a mask (ion implantation blocking mask). The first element implanted by the ion implantation IM4b for forming the diffusion prevention region 10b is made of one or more of carbon (C), nitrogen (N), and fluorine (F). The concentration of the first element in the diffusion prevention region 10b is, for example, about 5 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ^{2 in} terms of the implantation amount (dose amount) of the ion implantation IM4b, and in the volume concentration, for example, 1 × 10 ¹⁸ to 1 × 10. It can be about ²⁰ / cm ³ .

The diffusion prevention region 10b prevents the point defects generated by ion implantation when forming the extension region 7b, the halo region 8b, and the p ⁺ type semiconductor region 11b described later from diffusing into the channel region of the p channel MISFET Qp. It has a function to prevent. For this reason, at least a part of the diffusion prevention region 10b needs to be located between the extension region 7b, the halo region 8b, the p ⁺ type semiconductor region 11b described later, and the channel region of the p channel type MISFET Qp. . Therefore, it is preferable to form the diffusion prevention region 10b so as to wrap (cover) the halo region 8b.

  For this reason, in the ion implantation IM4b for forming the diffusion prevention region 10b, it is preferable to ion-implant the first element at a position deeper than the halo region 8b. The ion implantation IM4b for forming the diffusion prevention region 10b is preferably an oblique ion implantation (gradient ion implantation). Thereby, the diffusion prevention region 10b can be accurately positioned between the halo region 8b and the channel region of the n-channel type MISFET Qp.

  It is further preferable that the inclination angle of the ion implantation IM4b for forming the diffusion prevention region 10b is larger than the inclination angle of the ion implantation for forming the halo region 8b. As a result, the diffusion prevention region 10b can be positioned more accurately between the halo region 8b and the channel region of the p-channel type MISFET Qp.

  As another form, after the extension region 7b, the halo region 8b, and the diffusion prevention region 10b are first formed in the pMIS formation region 1B, the extension region 7a, the halo region 8a, and the diffusion prevention region 10a are formed in the nMIS formation region 1A. It can also be formed, and this is the same in the following second to fourth embodiments.

  The halo regions 8a and 8b are preferably formed to suppress short channel characteristics. However, the formation of the halo regions 8a and 8b can be omitted if unnecessary, and this is the same in the following second to fourth embodiments. .

  Further, the extension region 7a, the halo region 8a, and the diffusion prevention region 10a are not necessarily formed in this order, but the respective ion implantations IM2a, IM3a, IM4a for forming the extension region 7a, the halo region 8a, and the diffusion prevention region 10a. It is necessary to perform at least after forming the gate electrode GE1 and before forming a sidewall SW described later on the sidewall of the gate electrode GE1. Similarly, the extension region 7b, the halo region 8b, and the diffusion prevention region 10b do not necessarily have to be formed in this order, but the respective ion implantations IM2b, IM3b, which form the extension region 7b, the halo region 8b, and the diffusion prevention region 10b, IM4b needs to be performed at least after forming the gate electrode GE2 and before forming a later-described sidewall SW on the sidewall of the gate electrode GE2.

  Next, as shown in FIG. 10, after removing the photoresist film RP2b by ashing or the like, as an insulating film (sidewall insulating film) on the side walls of the gate electrodes GE1 and GE2, for example, silicon oxide or silicon nitride or Sidewall spacers or sidewalls (sidewall insulating films, sidewall spacers) SW made of a laminated film of these insulating films are formed. For example, the sidewall SW is formed by depositing a silicon oxide film, a silicon nitride film, or a laminated film thereof on the semiconductor substrate 1 (entire main surface thereof), and depositing the silicon oxide film, the silicon nitride film, or the laminated film thereof by RIE ( Reactive Ion Etching (reactive ion etching) can be formed by anisotropic etching.

  Next, as shown in FIG. 11, a photoresist film (photoresist pattern) RP3a covering the pMIS formation region 1B is formed using a photolithography technique. The nMIS formation region 1A is exposed without being covered with the photoresist film RP3a. The photoresist film RP3a can function as an ion implantation blocking mask for the pMIS formation region 1B. For this reason, in the ion implantation IM5a described later, the photoresist film RP3a functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B.

Next, an n-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into regions on both sides of the gate electrode GE1 and the sidewall SW of the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. Thereby, (a pair of) n ⁺ type semiconductor regions 11a (source and drain) are formed. In FIG. 11, ion implantation IM5a for forming the n ⁺ type semiconductor region 11a is schematically indicated by an arrow. In this ion implantation IM5a, since the gate electrode GE1 and the sidewall SW on the side wall thereof can also function as a mask (ion implantation blocking mask), the n ⁺ -type semiconductor region 11a is formed on the side wall on the side wall of the gate electrode GE1. Impurities are not introduced (ion-implanted) immediately below the gate electrode GE1 and the side wall SW. The depth (junction depth) of the n ⁺ -type semiconductor region 11a is deeper than the depth (junction depth) of the extension region 7a.

The n ⁺ type semiconductor region (second semiconductor region) 11a and the extension region (first semiconductor region) 7a have the same conductivity type, but the n ⁺ type semiconductor region 11a has an impurity concentration (n type) than the extension region 7a. Impurity concentration) is high. Thereby, an n-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the n-channel type MISFET Qn is formed by the n ⁺ -type semiconductor region (impurity diffusion layer) 11a and the extension region (n ⁻ -type semiconductor region) 7a. Is done. In other words, the extension region 7a and the n ⁺ type semiconductor region 11a having a higher impurity concentration function as a semiconductor region for the source or drain of the n-channel type MISFET Qn. Therefore, the source / drain region of the n-channel type MISFET Qn has an LDD (Lightly doped Drain) structure. As described above, the extension region 7a is formed in a self-aligned manner with respect to the gate electrode GE1, and the n ⁺ type semiconductor region 11a is in a self-aligned manner with respect to the sidewall SW formed on the sidewall of the gate electrode GE1. Formed.

In addition, after forming the sidewall SW, before or after ion implantation for forming the n ⁺ -type semiconductor region 11a, the semiconductor substrate 1 is made of one or more of carbon (C), nitrogen (N), and fluorine (F). The first element can be ion-implanted. In this case, it is preferable that the region implanted with the first element by this ion implantation wraps (covers) the n ⁺ type semiconductor region 11a. Thereby, it is possible to more accurately prevent the point defect generated in the n ⁺ type semiconductor region 11a from diffusing into the channel region of the n channel type MISFET Qn.

  Next, as shown in FIG. 12, after removing the photoresist film RP3a by ashing or the like, a photoresist film (photoresist pattern) RP3b covering the nMIS formation region 1A is formed by using a photolithography technique. The pMIS formation region 1B is exposed without being covered with the photoresist film RP3b. The photoresist film RP3b can function as an ion implantation blocking mask for the nMIS formation region 1A. For this reason, in ion implantation IM5b described later, the photoresist film RP3b functions as an ion implantation blocking mask, and ions are not implanted into the semiconductor substrate 1 in the nMIS formation region 1A.

Next, a p-type impurity such as boron (B) is ion-implanted into regions on both sides of the gate electrode GE2 and the side wall SW of the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B. The p ⁺ type semiconductor region 11b (source, drain) is formed. In FIG. 12, ion implantation IM5b for forming the p ⁺ type semiconductor region 11b is schematically indicated by an arrow. In this ion implantation IM5b, the gate electrode GE2 and the sidewall SW on the side wall thereof can also function as a mask (ion implantation blocking mask), so that the p ⁺ type semiconductor region 11b is formed on the side of the gate electrode GE2 on the side wall. Impurities are not introduced (ion-implanted) immediately below the gate electrode GE2 and the side wall SW. The depth (junction depth) of the p ⁺ -type semiconductor region 11b is deeper than the depth (junction depth) of the extension region 7b.

The p ⁺ type semiconductor region (second semiconductor region) 11b and the extension region (first semiconductor region) 7b have the same conductivity type, but the impurity concentration (p type) of the p ⁺ type semiconductor region 11b is higher than that of the extension region 7b. Impurity concentration) is high. Thereby, a p-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the p-channel type MISFET Qp is formed by the p ⁺ -type semiconductor region (impurity diffusion layer) 11b and the extension region (p ⁻ -type semiconductor region) 7b. Is done. In other words, the extension region 7b and the p ⁺ type semiconductor region 11b having a higher impurity concentration function as a semiconductor region for the source or drain of the p-channel type MISFET Qp. Therefore, the source / drain regions of the p-channel type MISFET Qp have an LDD structure. As described above, the extension region 7b is formed in a self-aligned manner with respect to the gate electrode GE2, and the p ⁺ type semiconductor region 11b is in a self-aligned manner with respect to the sidewall SW formed on the side wall of the gate electrode GE2. Formed.

In addition, after forming the sidewall SW, before or after ion implantation for forming the p ⁺ -type semiconductor region 11b, the semiconductor substrate 1 is made of one or more of carbon (C), nitrogen (N), and fluorine (F). The first element can be ion-implanted. In this case, it is preferable that the region implanted with the first element by this ion implantation wraps (covers) the p ⁺ type semiconductor region 11b. Thereby, it is possible to more accurately prevent the point defects generated in the p ⁺ type semiconductor region 11b from diffusing into the channel region of the p channel type MISFET Qp.

As another form, after forming the p ⁺ type semiconductor region 11b in the pMIS formation region 1B first, the n ⁺ type semiconductor region 11a can be formed in the nMIS formation region 1A. The same applies to Embodiments 2 to 4.

  Next, the photoresist film RP3b is removed by ashing or the like. Then, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed. This annealing process can be performed, for example, by a spike annealing process at about 1050 ° C.

  In this manner, an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qn is formed as a field effect transistor in the nMIS formation region 1A (the p-type well PW). A p-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qp is formed as a field effect transistor in the pMIS formation region 1B (n-type well NW thereof). Thereby, the structure of FIG. 13 is obtained. The n-channel type MISFET Qn can be regarded as an n-channel field effect transistor, and the p-channel type MISFET Qp can be regarded as a p-channel field effect transistor.

Next, the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b are exposed, and a metal film such as a cobalt (Co) film or nickel (Ni) is deposited and heat-treated. As a result, as shown in FIG. 14, metal silicide layers 12 are formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b, respectively. Thereby, the diffusion resistance, contact resistance, etc. of the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b can be reduced. Thereafter, the unreacted metal film is removed.

  Next, an insulating film 21 is formed on the main surface of the semiconductor substrate 1. That is, the insulating film 21 is formed on the semiconductor substrate 1 including the metal silicide layer 12 so as to cover the gate electrodes GE1 and GE2. The insulating film 21 is made of, for example, a silicon nitride film, and can be formed using a plasma CVD method or the like. Then, an insulating film 22 thicker than the insulating film 21 is formed on the insulating film 21. The insulating film 22 is made of, for example, a silicon oxide film or the like, and can be formed by a plasma CVD method or the like using TEOS (Tetraethoxysilane: Tetra Ethyl Ortho Silicate). Thereby, an interlayer insulating film composed of the insulating films 21 and 22 is formed. Thereafter, the upper surface of the insulating film 22 is planarized by polishing the surface of the insulating film 22 by CMP or the like. Even if unevenness is formed on the surface of the insulating film 21 due to the base step, by polishing the surface of the insulating film 22 by the CMP method, an interlayer insulating film having a flattened surface can be obtained. .

Next, by using the photoresist pattern (not shown) formed on the insulating film 22 as an etching mask, the insulating films 22 and 21 are dry-etched to form contact holes (through holes, holes) in the insulating films 22 and 21. ) 23. At this time, first, the insulating film 22 is dry-etched under conditions that allow the insulating film 22 to be etched more easily than the insulating film 21, and the insulating film 21 functions as an etching stopper film, whereby the contact hole 23 is formed in the insulating film 22. After the formation, the insulating film 21 at the bottom of the contact hole 23 is removed by dry etching under the condition that the insulating film 21 is more easily etched than the insulating film 22. At the bottom of the contact hole 23, a part of the main surface of the semiconductor substrate 1, for example, a part of the metal silicide layer 12 on the surface of the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b, and the gate electrodes GE1 and GE2 A part of the metal silicide layer 12 on the surface is exposed.

Next, a plug (connecting conductor portion) 24 made of tungsten (W) or the like is formed in the contact hole 23. In order to form the plug 24, for example, a barrier conductor film 24a (for example, a titanium film, a titanium nitride film, or a laminate thereof) is formed on the insulating film 22 including the inside (on the bottom and side walls) of the contact hole 23 by a plasma CVD method. Film). Then, a main conductor film 24b made of a tungsten film or the like is formed so as to fill the contact hole 23 on the barrier conductor film 24a by CVD or the like, and the unnecessary main conductor film 24b and barrier conductor film 24a on the insulating film 22 are CMPed. The plug 24 can be formed by removing it by the method or the etch back method. The plug 24 formed on the gate electrodes GE1, GE2, n ⁺ type semiconductor region 11a or p ⁺ type semiconductor region 11b has a gate electrode GE1, GE2, n ⁺ type semiconductor region 11a or p ⁺ type semiconductor region 11b at the bottom. The metal silicide layer 12 on the surface of the metal is in contact with and electrically connected.

  Next, as shown in FIG. 15, a stopper insulating film 25 and a wiring forming insulating film 26 are sequentially formed on the insulating film 22 in which the plugs 24 are embedded. The stopper insulating film 25 is a film that becomes an etching stopper when the groove is formed in the insulating film 26, and a material having an etching selectivity with respect to the insulating film 26 is used. The stopper insulating film 25 can be a silicon nitride film formed by, for example, plasma CVD, and the insulating film 26 can be, for example, a silicon oxide film formed by plasma CVD. The stopper insulating film 25 and the insulating film 26 are formed with a first layer wiring described below.

Next, a first layer wiring is formed by a single damascene method. First, after forming a wiring groove 27 in a predetermined region of the insulating film 26 and the stopper insulating film 25 by dry etching using a photoresist pattern (not shown) as a mask, the wiring groove 27 is formed on the main surface of the semiconductor substrate 1 (that is, the wiring groove 27). A barrier conductor film (barrier metal film) 28 is formed on the insulating film 26 including the bottom and side walls. As the barrier conductor film 28, for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like can be used. Subsequently, a copper seed layer is formed on the barrier conductor film 28 by a CVD method or a sputtering method, and further a copper plating film is formed on the seed layer by an electrolytic plating method or the like. 27 is embedded. In FIG. 15, a combination of the seed film and the copper plating film is shown as a copper main conductor film 29. Then, the main conductor film 29 (copper plating film and seed layer) and the barrier metal film 28 in the region other than the wiring groove 27 are removed by CMP, and the first layer is buried in the wiring groove 27 and uses copper as the main conductive material. An eye wiring M1 is formed. The wiring M1 is electrically connected to the n ⁺ -type semiconductor region 11a and p ⁺ -type semiconductor region 11b for the source or drain of the n-channel type MISFET Qn and p-channel type MISFET Qp, the gate electrodes GE1, GE2, etc. via the plug 24. ing. Thereafter, a second layer wiring is formed by a dual damascene method, but illustration and description thereof are omitted here.

  Next, the effect of this embodiment will be described in more detail.

  When an impurity is ion-implanted into a semiconductor substrate, the implanted impurity is randomly arranged at the stage immediately after the implantation. However, when the impurity diffuses (moves) in various subsequent heating processes, the random arrangement of the impurity is destroyed. As a result, the distribution of impurities is biased compared to immediately after the implantation. That is, in the stage immediately after ion implantation, the randomness of the arrangement of implanted impurities is high, but if the impurities diffuse (move) in various subsequent heating steps, the randomness of the arrangement of impurities deteriorates. This is the same even when the ion implantation is channel doping ion implantation for adjusting the threshold value of the MISFET. Accordingly, in the stage immediately after channel doping ion implantation, the arrangement of impurities doped in the channel region is highly random, but when the impurities diffuse (move) in various subsequent heating processes, the impurities doped in the channel region The randomness of the arrangement of will be reduced.

  In addition, in a state where the randomness of the arrangement of impurities is high, the impurities are not arranged uniformly (regularly) microscopically (at the level of atomic arrangement) but are present in a random (random) manner. However, since they are microscopically random, the impurities are distributed equally in a macroscopic manner (channel region level). For this reason, in a state where the randomness of the impurity arrangement is high, the difference in impurity distribution (difference between the impurity distribution in the channel region of one MISFET and the impurity distribution in the channel region of another MISFET) when the channel regions are compared with each other. Small, variation in threshold of MISFET is small.

  However, if the randomness of the impurity arrangement decreases, this state collapses, and the macroscopic impurity distribution (impurity distribution at the channel region level) is biased. For this reason, after the channel doping ion implantation, in the state where the randomness of the channel doping impurities is reduced by thermal diffusion, the difference in the impurity distribution when comparing the channel regions (impurity distribution in the channel region of a certain MISFET and others) (Difference from the impurity distribution in the channel region of the MISFET) increases, and the variation in threshold value of the MISFET increases. That is, the state of the channel region (arrangement state of impurities in the channel region) varies for each MISFET, and the threshold voltage varies for each MISFET. In order to improve the performance of the semiconductor device, it is desired to suppress variations in threshold voltage for each MISFET.

  For this reason, it is possible to suppress as much as possible the impurities introduced in the channel doping ion implantation from being rearranged (diffused) during the subsequent heating process, and to arrange the channel doped impurities immediately after the implantation (arrangement with high randomness). It is important to maintain as much as possible after the implantation in order to suppress variation in threshold voltage for each MISFET.

Further, when ion implantation is performed on the semiconductor substrate 1, point defects are also generated in the region of the semiconductor substrate 1 doped with impurity ions, but the point defects are easily diffused. For this reason, the point defects generated by the respective ion implantations when forming the extension regions 7a and 7b, the halo regions 8a and 8b, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b are caused by various subsequent heating processes. Thus, there is a possibility of diffusing up to the channel region of MISFET (region immediately below gate electrodes GE1 and GE2). In particular, since the extension regions 7a and 7b and the halo regions 8a and 8b are close to the channel region (the region immediately below the gate electrodes GE1 and GE2), they are generated in the extension regions 7a and 7b and the halo regions 8a and 8b by ion implantation. Point defects are likely to diffuse into the channel region. When point defects diffuse into the channel region, the density of point defects in the channel region increases. However, the larger the density of point defects, the easier the impurities introduced into the channel region by channel doping ion implantation move (diffuse). This is because when there are many point defects, impurities easily move (diffuse) through the point defects.

For this reason, in order to suppress as much as possible the impurities introduced by channel dope ion implantation from being rearranged (diffused) during various subsequent heating steps, the extension regions 7a and 7b, the halo regions 8a and 8b, Point defects generated by each ion implantation when forming the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b are prevented from diffusing into the channel region as much as possible, and the density of point defects in the channel region is reduced. It is effective to suppress.

  According to the study of the present inventor, a region in which at least one of carbon (C), nitrogen (N), and fluorine (F) is introduced into a substrate region (semiconductor substrate 1) made of single crystal silicon (this embodiment) It was found that the diffusion preventing regions 10a and 10b in the form of (1) have a function of preventing the point defects from being diffused (moved) and preventing the point defects from being diffused (moved).

  Therefore, in the present embodiment, as described above, one or more of carbon (C), nitrogen (N), and fluorine (F) is applied to the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A ( That is, the first element) is ion-implanted to form the diffusion prevention region 10a. Further, as described above, one or more of carbon (C), nitrogen (N), and fluorine (F) (that is, the first element) is applied to the semiconductor substrate 1 (n-type well NW) in the pMIS formation region 1B. Ion implantation is performed to form the diffusion prevention region 10b.

The diffusion prevention region 10a, which is a region into which one or more of carbon (C), nitrogen (N), or fluorine (F) is introduced, forms an extension region 7a, a halo region 8a, and an n ⁺ type semiconductor region 11a. It has a function of preventing the point defects generated by the respective ion implantations from being diffused to the channel region of the n-channel type MISFET Qn (the region immediately below the gate electrode GE1). The diffusion prevention region 10b, which is a region into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced, includes an extension region 7b, a halo region 8b, and a p ⁺ type semiconductor region 11b. Has a function of preventing the point defects generated by the respective ion implantations during the formation of the diffusion into the channel region of the p-channel type MISFET Qp (region immediately below the gate electrode GE2).

In order for the diffusion prevention region 10a to have the above-described function, at least a part of the diffusion prevention region 10a includes an extension region 7a, a halo region 8a, an n ⁺ type semiconductor region 11a, and a channel region (gate electrode) of the n channel MISFET Qn. It is necessary to be located between the region immediately below GE1). Of the extension region 7a, the halo region 8a, and the n ⁺ type semiconductor region 11a, the halo region 8a is closest to the channel region of the n-channel type MISFET Qn. Therefore, when the halo region 8a is formed, at least a part of the diffusion prevention region 10a May be positioned between the halo region 8a and the channel region of the n-channel MISFET Qn. In order to do this, it is preferable to form the diffusion preventing region 10a so as to wrap (cover) the halo region 8a. When the formation of the halo region 8a is omitted, since the extension region 7a is close to the channel region, at least a part of the diffusion prevention region 10a only needs to be located between the extension region 7a and the channel region of the n-channel type MISFET Qn. In order to do this, it is preferable to form the diffusion prevention region 10a so as to wrap (cover) the extension region 7a.

  When at least a part of the diffusion prevention region 10a is located between the halo region 8a and the channel region of the n-channel type MISFET Qn, the extension region 7a and the channel region of the n-channel type MISFET Qn are necessarily formed. At least a part of the diffusion prevention region 10a is located between them. Therefore, regardless of whether the halo region 8a is formed or not, the halo region 8a is formed by positioning at least a part of the diffusion prevention region 10a between the extension region 7a and the channel region of the n-channel type MISFET Qn. In other words, at least a part of the diffusion prevention region 10a may be positioned between the halo region 8a and the channel region of the n-channel type MISFET Qn.

Further, in order for the diffusion prevention region 10b to have the above-described function, at least a part of the diffusion prevention region 10b includes the extension region 7b, the halo region 8b, the p ⁺ type semiconductor region 11b, and the channel region of the p channel MISFET Qp ( It is necessary to be located between the region immediately below the gate electrode GE2. Of the extension region 7b, the halo region 8b, and the p ⁺ type semiconductor region 11b, the halo region 8b is closest to the channel region of the p-channel type MISFET Qp. Therefore, when the halo region 8b is formed, at least a part of the diffusion prevention region 10b May be positioned between the halo region 8b and the channel region of the p-channel type MISFET Qp. In order to do this, it is preferable to form the diffusion preventing region 10b so as to wrap (cover) the halo region 8b. When the formation of the halo region 8b is omitted, since the extension region 7b is close to the channel region, at least a part of the diffusion prevention region 10b may be located between the extension region 7b and the channel region of the p-channel type MISFET Qp. In order to do this, it is preferable to form the diffusion preventing region 10b so as to wrap (cover) the extension region 7b.

  When at least a part of the diffusion prevention region 10b is located between the halo region 8b and the channel region of the p-channel type MISFET Qp, the extension region 7b and the channel region of the p-channel type MISFET Qp are necessarily formed. At least a part of the diffusion preventing region 10b is located between them. Therefore, regardless of whether or not the halo region 8b is formed, when the halo region 8b is formed by positioning at least a part of the diffusion prevention region 10b between the extension region 7b and the channel region of the p-channel type MISFET Qp. In other words, at least a part of the diffusion prevention region 10b may be positioned between the halo region 8b and the channel region of the p-channel type MISFET Qp.

In the present embodiment, since the diffusion prevention regions 10a and 10b are formed, each ion when forming the extension regions 7a and 7b, the halo regions 8a and 8b, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b is formed. Point defects generated by implantation can be prevented from diffusing into the channel regions of the n-channel MISFET Qn and the p-channel MISFET Qp, and the density of point defects in the channel region can be suppressed. As a result, it is possible to suppress or prevent the impurities introduced into the channel region by the channel doping ion implantation from being rearranged (diffused) during the subsequent heating step. (Arrangement with high randomness) can be maintained. Therefore, variations in channel region states (impurity distribution) for each MISFET can be suppressed, variations in threshold voltage for each MISFET can be suppressed, and the performance of the semiconductor device can be improved.

  In addition, one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced into the diffusion prevention regions 10a and 10b, but carbon (C), nitrogen (N), and fluorine ( Among F), carbon (C) is most effective for preventing the diffusion of point defects. For this reason, it is more preferable that at least carbon (C) of carbon (C), nitrogen (N), or fluorine (F) is introduced into the diffusion prevention regions 10a and 10b. Thereby, the above-mentioned effect by providing the diffusion prevention regions 10a and 10b can be obtained more accurately.

  In this embodiment, diffusion prevention regions 10a and 10b are formed by ion implantation of one or more of carbon (C), nitrogen (N), and fluorine (F) only in a necessary region in a semiconductor substrate. can do. For this reason, carbon (C), nitrogen (N) or fluorine (F) can be prevented from being introduced into unnecessary areas, and carbon (C), nitrogen (N) or fluorine (F) is introduced into unnecessary areas. The negative effect by being done can be eliminated.

  In addition, the variation in threshold voltage for each MISFET due to the rearrangement (diffusion) of impurities introduced by channel doping ion implantation is larger in the n-channel MISFET than in the p-channel MISFET. In general, n-channel MISFETs are implanted with p-type impurities by channel dope ion implantation, and p-channel MISFETs are implanted with n-type impurities by channel dope ion implantation. This is because a p-type impurity such as boron (B) is more easily thermally diffused than an n-type impurity. For this reason, the present embodiment (forming those corresponding to the diffusion prevention regions 10a and 10b) is not only a semiconductor device having a CMISFET, but also a semiconductor device having only one of a p-channel MISFET and an n-channel MISFET. However, if applied to a semiconductor device having at least an n-channel MISFET, the effect is great. The same applies to the following second to sixth embodiments.

(Embodiment 2)
A manufacturing process of the semiconductor device according to the second embodiment will be described with reference to the drawings. 16 to 22 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

  In the present embodiment, first, as shown in FIG. 16, a semiconductor substrate (semiconductor wafer) 1a made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example, is prepared, and the semiconductor substrate 1a ( A semiconductor layer (semiconductor region) 1b is formed on the entire main surface of the substrate.

  The semiconductor layer 1b is a semiconductor layer (single crystal silicon layer) into which one or more of carbon (C), nitrogen (N), or fluorine (F) (ie, the first element) is introduced. , Carbon (C), nitrogen (N), or fluorine (F) is made of single crystal silicon (Si) into which one or more (that is, the first element) are introduced (doped).

The semiconductor layer 1b is preferably formed by epitaxially growing the semiconductor layer 1b on the semiconductor substrate 1a. A combination of the semiconductor substrate 1a and the semiconductor layer 1b thereon is referred to as a semiconductor substrate SUB1, and the semiconductor substrate SUB1 can also be regarded as a so-called epitaxial wafer. The main surface (front surface) of the semiconductor substrate SUB1 corresponds to the main surface (front surface) of the semiconductor layer 1b. The concentration of the first element in the semiconductor layer 1b can be, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . The thickness of the semiconductor layer 1b is formed such that a p-type well PW and an n-type well NW to be formed later can be included in the semiconductor layer 1b, and has a thickness of, for example, about 1 to 10 μm. ing.

  As another form, a semiconductor layer (semiconductor region) 1b into which one or more of carbon (C), nitrogen (N), or fluorine (F) are introduced is formed on the upper layer portion of the semiconductor substrate 1a with carbon (C), It can also be formed by ion implantation of one or more of nitrogen (N) or fluorine (F).

  Next, as shown in FIG. 17, the element isolation region 2 is formed on the main surface of the semiconductor substrate SUB1. Since the method for forming the element isolation region 2 is the same as that in the first embodiment, the description thereof is omitted here. The element isolation region 2 defines an nMIS formation region 1A and a pMIS formation region 1B.

  Next, an insulating film 3 similar to that of the first embodiment is formed on the surface of the semiconductor substrate SUB1 (that is, the surface of the semiconductor layer 1b).

  Next, as shown in FIG. 18, in the nMIS formation region 1A, channel doping ion implantation similar to the channel doping ion implantation IM1a of the first embodiment (threshold adjustment of the n channel MISFET Qn formed later) (Ion implantation) IM1a is performed to form a channel dope layer 4a in the upper layer portion of the semiconductor layer 1b. Then, in the nMIS formation region 1A, a p-type well PW is formed in the semiconductor layer 1b by ion implantation. Further, in the pMIS formation region 1B, channel doping ion implantation (ion implantation for adjusting the threshold value of a p-channel type MISFET Qp formed later) IM1b similar to the channel doping ion implantation IM1b of the first embodiment is performed. The channel dope layer 4b is formed in the upper layer portion of the semiconductor layer 1b. Then, in the pMIS formation region 1B, an n-type well NW is formed in the semiconductor layer 1b by ion implantation.

  In FIG. 18, channel dope ion implantation IM1a and IM1b are schematically indicated by arrows, but channel dope ion implantation IM1a and channel dope ion implantation IM1b are performed in separate steps. That is, in the present embodiment as in the first embodiment, the channel dope ion implantation IM1a for forming the channel dope layer 4a and the ion implantation for forming the p-type well PW are the same as those in the photoresist. The pMIS formation region 1B is covered with a photoresist film (not shown) similar to the film RP1a so that ions are not implanted into the semiconductor layer 1b in the pMIS formation region 1B. On the other hand, the channel dope ion implantation IM1b for forming the channel dope layer 4b and the ion implantation for forming the n-type well NW are performed by a photoresist film (not shown) similar to the photoresist film RP1b in the nMIS. The process is performed while covering the formation region 1A so that ions are not implanted into the semiconductor layer 1b in the nMIS formation region 1A.

  In the first embodiment, channel dope ion implantation IM1a and IM1b are performed on the semiconductor substrate 1 to form the channel dope layers 4a and 4b. In contrast, in this embodiment, channel dope ion implantation IM1a and IM1b are performed in the semiconductor layer 1b to form channel dope layers 4a and 4b. Otherwise, the channel dope ions in the present embodiment are used. The configurations of the implantations IM1a and IM1b and the channel dope layers 4a and 4b are the same as those in the first embodiment. In the first embodiment, the p-type well PW and the n-type well NW are formed in the semiconductor substrate 1, whereas in the present embodiment, the p-type well PW and the n-type well are formed in the semiconductor layer 1b. The NW is formed, but other than that, the formation method and configuration of the p-type well PW and the n-type well NW in the present embodiment are the same as those in the first embodiment.

  Next, after removing the insulating film 3 to clean the surface of the semiconductor layer 1b, the surface of the semiconductor layer 1b in the nMIS formation region 1A and the pMIS formation region 1B (surfaces of the p-type well PW and the n-type well NW). An insulating film 5 for a gate insulating film is formed thereon. In the first embodiment, the insulating film 5 is formed on the surface of the insulating film on the semiconductor substrate 1, whereas in the present embodiment, the insulating film 5 is formed on the semiconductor layer 1b. Except for the above, the formation method and configuration of the insulating film 5 in the present embodiment are the same as those in the first embodiment.

  Next, gate electrodes GE1 and GE2 are formed. In the first embodiment, the gate electrodes GE1 and GE2 are formed on the semiconductor substrate 1 via the insulating film 5 (gate insulating films 5a and 5b), whereas in the present embodiment, the semiconductor layer 1b is formed. Gate electrodes GE1 and GE2 are formed thereon via an insulating film 5 (gate insulating films 5a and 5b). Other than that, the formation method and configuration of the gate electrodes GE1 and GE2 in the present embodiment are the same as those in the first embodiment. Thereby, the structure of FIG. 19 is obtained.

  Next, as shown in FIG. 20, n-type impurities such as phosphorus (P) or arsenic (As) are formed in the regions on both sides of the gate electrode GE1 of the semiconductor layer 1b (p-type well PW) in the nMIS formation region 1A. Then, the extension region 7a is formed. Then, ion implantation (halo ion implantation) is performed on the semiconductor layer 1b (p-type well PW) in the nMIS formation region 1A to form the halo region 8a. Also, a p-type impurity such as boron (B) is ion-implanted into the regions on both sides of the gate electrode GE2 of the semiconductor layer 1b (n-type well NW) in the pMIS formation region 1B, as in the first embodiment. Thus, the extension region 7b is formed. Then, ion implantation (halo ion implantation) is performed on the semiconductor layer 1b (n-type well NW) in the pMIS formation region 1B to form the halo region 8b.

  As in the first embodiment, also in the second embodiment and the following third and fourth embodiments, ion implantation for forming the extension region 7a and ion implantation for forming the halo region 8a Is performed in a state where the pMIS formation region 1B is covered with a photoresist film (not shown) similar to the photoresist film RP2a so that ions are not implanted into the semiconductor layer 1b in the pMIS formation region 1B. On the other hand, in the second embodiment and the following third and fourth embodiments as in the first embodiment, the ion implantation for forming the extension region 7b and the ion implantation for forming the halo region 8b The nMIS formation region 1A is covered with a photoresist film (not shown) similar to the photoresist film RP2b so that ions are not implanted into the semiconductor layer 1b in the nMIS formation region 1A.

  In the first embodiment, the extension regions 7a and 7b and the halo regions 8a and 8b are formed in the semiconductor substrate 1, whereas in the present embodiment, the extension regions 7a and 7b and the halo region are formed in the semiconductor layer 1b. 8a and 8b are formed. Otherwise, the formation method and configuration of the extension regions 7a and 7b and the halo regions 8a and 8b in the present embodiment are the same as those in the first embodiment.

  Next, as shown in FIG. 21, as in the first embodiment, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE1 and GE2.

Next, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the regions on both sides of the gate electrode GE1 and the sidewall SW of the semiconductor layer 1b (p-type well PW) in the nMIS formation region 1A. Thus, the n ⁺ type semiconductor region 11a (source, drain) is formed. Further, p ⁺ type impurities such as boron (B) are ion-implanted into regions on both sides of the gate electrode GE2 and the sidewall SW of the semiconductor layer 1b (n-type well NW) in the pMIS formation region 1B. A semiconductor region 11b (source, drain) is formed.

As in the first embodiment, also in the second embodiment and the following third and fourth embodiments, the ion implantation for forming the n ⁺ type semiconductor region 11a is the same as that in the photoresist film RP3a. The pMIS formation region 1B is covered with a photoresist film (not shown) so that ions are not implanted into the semiconductor layer 1b in the pMIS formation region 1B. On the other hand, in the second embodiment and the following third and fourth embodiments as in the first embodiment, the ion implantation for forming the p ⁺ type semiconductor region 11b is the same as that in the photoresist film RP3b. The nMIS formation region 1A is covered with a photoresist film (not shown) so that ions are not implanted into the semiconductor layer 1b in the nMIS formation region 1A.

In the first embodiment, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b are formed in the semiconductor substrate 1, whereas in the present embodiment, the n ⁺ type semiconductor region 11a is formed in the semiconductor layer 1b. The p ⁺ -type semiconductor region 11b is formed. Otherwise, the formation method and configuration of the n ⁺ -type semiconductor region 11a and the p ⁺ -type semiconductor region 11b in the present embodiment are described in the first embodiment. It is the same.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

The subsequent steps are the same as those in the first embodiment. That is, as shown in FIG. 22, the metal silicide layers 12 are formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b, respectively, and the main surface of the semiconductor substrate SUB1 (that is, the semiconductor) An insulating film 21 is formed on the main surface of the layer 1b so as to cover the gate electrodes GE1 and GE2, and an insulating film 22 is formed on the insulating film 21. Then, contact holes 23 are formed in the insulating films 22 and 21, and plugs 24 are formed in the contact holes 23. Thereafter, a stopper insulating film 25 and an insulating film 26 are sequentially formed on the insulating film 22 in which the plug 24 is embedded, a wiring groove 27 is formed in the insulating film 26 and the stopper insulating film 25, and the bottom and side walls of the wiring groove 27 are formed. A barrier conductor film 28 is formed on the insulating film 26 including the upper portion, and the wiring groove 27 is filled with a copper main conductor film 29 to form a wiring M1.

  Next, the effect of this embodiment will be described in more detail.

  In the first embodiment, by forming the diffusion prevention regions 10a and 10b into which at least one of carbon (C), nitrogen (N), and fluorine (F) is introduced, the point defects in the channel region are reduced. Diffusion was prevented, thereby suppressing the density of point defects in the channel region, and relocation (diffusion) of impurities introduced into the channel region by channel doping ion implantation was suppressed.

On the other hand, in the present embodiment, a semiconductor substrate SUB1 having a semiconductor layer 1b into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced is prepared. An n-channel MISFET Qn and a p-channel MISFET Qp are formed in the layer 1b. That is, in the present embodiment, the channel region, extension regions 7a and 7b, halo regions 8a and 8b, n ⁺ type semiconductor region 11a and p ⁺ type semiconductor region 11b of the n channel MISFET Qn and p channel MISFET Qp are made of carbon ( C), formed in the semiconductor layer 1b into which one or more of nitrogen (N) and fluorine (F) are introduced.

As described above, a region where one or more of carbon (C), nitrogen (N), and fluorine (F) is introduced into single crystal silicon (corresponding to the semiconductor layer 1b in this embodiment) is a point defect. Is difficult to diffuse (move) and has a function of preventing the diffusion (movement) of point defects. For this reason, in this embodiment, point defects hardly diffuse (move) over the entire semiconductor layer 1b into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced. . For this reason, the point defects generated by the respective ion implantations when forming the extension regions 7a and 7b, the halo regions 8a and 8b, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b are converted into n channel type MISFETs Qn and p. Diffusion to the channel region of the channel type MISFET Qp (region immediately below the gate electrodes GE1 and GE2) can be prevented, and the density of point defects in the channel region can be suppressed. As a result, it is possible to suppress or prevent the impurities introduced into the channel region by the channel doping ion implantation from being rearranged (diffused) during the subsequent heating step. (Arrangement with high randomness) can be maintained. Therefore, variations in channel region states (impurity distribution) for each MISFET can be suppressed, variations in threshold voltage for each MISFET can be suppressed, and the performance of the semiconductor device can be improved.

  In addition, one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced into the semiconductor layer 1b, but carbon (C), nitrogen (N), and fluorine (F) Of these, carbon (C) is most effective in preventing the diffusion of point defects. For this reason, it is more preferable that at least carbon (C) is introduced into the semiconductor layer 1b among carbon (C), nitrogen (N), or fluorine (F).

In the present embodiment, the semiconductor layer 1b is formed on the main surface of the semiconductor substrate 1a by epitaxial growth or the like. However, as another form, carbon (C), nitrogen (N) or fluorine is formed on the upper layer portion of the semiconductor substrate 1. A region corresponding to the semiconductor layer 1b can be formed in the upper layer portion of the semiconductor substrate 1 by ion-implanting one or more of (F). In this case, the entire semiconductor substrate SUB1 corresponds to the semiconductor substrate 1, and the semiconductor layer 1b of the semiconductor substrate SUB1 is carbon (C), nitrogen (N) or fluorine by ion implantation in the semiconductor substrate 1. This corresponds to a semiconductor region (semiconductor layer) into which one or more of (F) are introduced. That is, a semiconductor region (semiconductor layer) corresponding to the semiconductor layer 1b is formed by ion-implanting one or more of carbon (C), nitrogen (N), or fluorine (F) into the upper layer portion of the semiconductor substrate 1. Then, the p-type well PW, the n-type well NW, the extension regions 7a and 7b, the halo regions 8a and 8b, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b are formed in the semiconductor region (semiconductor layer). It is. Also in this case, the point defects generated by the ion implantation when forming the extension regions 7a and 7b, the halo regions 8a and 8b, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b are the n channel type MISFETs Qn and p. Diffusion into the channel region of the channel type MISFET Qp can be prevented, and the density of point defects in the channel region can be suppressed. Therefore, it is possible to suppress or prevent the impurities introduced into the channel region by channel doping ion implantation from being rearranged (diffused) during the subsequent heating process, and the state of the channel region (impurity distribution) for each MISFET. ) Can be suppressed, and variations in threshold voltage for each MISFET can be suppressed.

In the present embodiment, at least one of carbon (C), nitrogen (N), and fluorine (F) is introduced into the entire semiconductor layer 1b, and p-type well PW, n-type well NW, Extension regions 7a and 7b, halo regions 8a and 8b, an n ⁺ type semiconductor region 11a and a p ⁺ type semiconductor region 11b are formed. For this reason, the effect which suppresses the spreading | diffusion of the point defect produced | generated at the time of ion implantation by introduce | transducing 1 or more types of carbon (C), nitrogen (N), or fluorine (F) is very large.

(Embodiment 3)
A manufacturing process of the semiconductor device according to the third embodiment will be described with reference to the drawings. 23 to 32 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

  In the present embodiment, as in the first embodiment, as shown in FIG. 23, first, a semiconductor substrate (semiconductor wafer) 1 is prepared, and an element isolation region 2 is formed on the main surface of the semiconductor substrate 1. .

  Next, an insulating film 3 similar to that of the first embodiment is formed on the surface of the semiconductor substrate 1.

  Next, in the nMIS formation region 1A, a p-type well PW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth in the same manner as in the first embodiment. In the pMIS formation region 1B, In the same manner as in the first embodiment, an n-type well NW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth. The formation method and configuration of the p-type well PW and the n-type well NW in the present embodiment are the same as those in the first embodiment.

  In this embodiment, before forming an insulating film 5 for a gate insulating film, which will be described later, the threshold value of the channel dope ion implantation IM1a for adjusting the threshold value of the n-channel type MISFET Qn and the threshold value of the p-channel type MISFET Qp. Since channel doping ion implantation IM1b for adjustment is not performed, channel doped layers 4a and 4b are not formed at this stage.

  Next, as shown in FIG. 24, after removing the insulating film 3 and cleaning the surface of the semiconductor substrate 1 as in the first embodiment, the semiconductor substrates in the nMIS formation region 1A and the pMIS formation region 1B An insulating film 5 for a gate insulating film is formed on the surface of 1 (the surfaces of the p-type well PW and the n-type well NW). The formation method and configuration of the insulating film 5 in the present embodiment are the same as those in the first embodiment.

  Next, as shown in FIG. 25, as a conductor film (conductor layer) on the entire main surface of the semiconductor substrate 1 (that is, on the insulating film 5 of the nMIS formation region 1A and the pMIS formation region 1B), A silicon film (first conductor layer) 6a such as a polycrystalline silicon film is formed. Further, the silicon film 6a, which was an amorphous silicon film at the time of film formation, can be changed to a polycrystalline silicon film by heat treatment after the film formation. The thickness (deposited film thickness) t1 of the silicon film 6a can be set to, for example, about 20 to 100 nm.

  Next, as shown in FIG. 26, a photoresist film (photoresist pattern) RP4a covering the pMIS formation region 1B is formed by using a photolithography technique. The nMIS formation region 1A is exposed without being covered with the photoresist film RP4a. The photoresist film RP4a can function as an ion implantation blocking mask for the pMIS formation region 1B.

  Next, in the nMIS formation region 1A, channel doping ion implantation (ion implantation for adjusting the threshold value of an n-channel MISFET Qn to be formed later) IM1a similar to that in the first embodiment is performed, and the semiconductor substrate 1 ( A channel dope layer 4a is formed in the upper layer portion of the p-type well PW). In FIG. 26, the channel dope ion implantation IM1a is schematically indicated by an arrow.

  In the first embodiment, the channel dope ion implantation IM1a is performed on the semiconductor substrate 1 before forming the insulating film 5 for the gate insulating film to form the channel dope layer 4a. On the other hand, in this embodiment, the channel dope ion implantation IM1a is performed after the formation of the insulating film 5 for the gate insulating film and the silicon film 6a to form the channel dope layer 4a. The configurations of the channel dope ion implantation IM1a and the channel dope layer 4a in the embodiment are the same as those in the first embodiment.

  Next, as shown in FIG. 27, after the photoresist film RP4a is removed, a photoresist film (photoresist pattern) RP4b covering the nMIS formation region 1A is formed by using a photolithography technique. The pMIS formation region 1B is exposed without being covered with the photoresist film RP4b. The photoresist film RP4b can function as an ion implantation blocking mask for the nMIS formation region 1A.

  Next, in the pMIS formation region 1B, channel doping ion implantation (ion implantation for adjusting the threshold voltage of a p-channel type MISFET Qp to be formed later) IM1b similar to that in the first embodiment is performed, and the semiconductor substrate 1 ( A channel dope layer 4b is formed in the upper layer portion of the n-type well NW). In FIG. 27, the channel dope ion implantation IM1b is schematically indicated by an arrow.

  In the first embodiment, the channel dope ion implantation IM1b is performed on the semiconductor substrate 1 to form the channel dope layer 4b before the formation of the insulating film 5 for the gate insulating film. On the other hand, in this embodiment, the channel dope ion implantation IM1b is performed after the formation of the insulating film 5 for the gate insulating film and the silicon film 6a to form the channel dope layer 4b. The configurations of channel dope ion implantation IM1b and channel dope layer 4b in the embodiment are the same as those in the first embodiment. As another form, after the channel dope layer 4b is formed in the pMIS formation region 1B by the channel dope ion implantation IM1b, the channel dope layer 4a can be formed in the nMIS formation region 1A by the channel dope ion implantation IM1a.

  Next, as shown in FIG. 28, after removing the photoresist film RP4a, a silicon film (second conductive film) such as a polycrystalline silicon film is formed on the silicon film 6a as a conductor film (conductor layer). Body layer) 6b is formed. The thickness (deposited film thickness) t2 of the silicon film 6b is preferably thicker than the thickness t1 of the silicon film 6a (that is, t2> t1), and can be, for example, about 80 to 150 nm. A laminated film of the silicon film 6 a and the silicon film 6 b corresponds to the silicon film 6.

  Next, as shown in FIG. 29, gate electrodes GE1 and GE2 are formed by patterning the laminated film of the silicon film 6a and the silicon film 6b using a photolithography method and a dry etching method. That is, the gate electrode GE1 is formed on the insulating film 5 (ie, the gate insulating film 5a) in the nMIS formation region 1A, and the gate electrode GE2 is formed on the insulating film 5 (ie, the gate insulating film 5b) in the pMIS formation region 1B.

  For this reason, in the present embodiment, the gate electrodes GE1 and GE2 are formed of a laminated film of the silicon film 6a and the silicon film 6b on the silicon film 6a. The insulating film 5 remaining under the gate electrode GE1 becomes the gate insulating film 5a of the n-channel type MISFET Qn, and the insulating film 5 remaining under the gate electrode GE2 becomes the gate insulating film 5b of the p-channel type MISFET Qp.

  Subsequent steps are the same as those in the first embodiment except that the step of forming diffusion prevention regions 10a and 10b (ion implantation IM5a and IM5b) is omitted.

  That is, as shown in FIG. 30, the extension region 7a and the halo region 8a are formed in the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A, and the semiconductor substrate 1 (n-type in the pMIS formation region 1B). An extension region 7b and a halo region 8b are formed in the well NW). The formation method and configuration of the extension regions 7a and 7b and the halo regions 8a and 8b in the present embodiment are the same as those in the first embodiment.

Next, as shown in FIG. 31, after sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE1 and GE2, n are formed on the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. ^{A +} type semiconductor region 11a (source, drain) is formed, and a p ⁺ type semiconductor region 11b (source, drain) is formed in the semiconductor substrate 1 (n type well NW) in the pMIS formation region 1B. The formation method and configuration of the sidewall SW, the n ⁺ type semiconductor region 11a, and the p ⁺ type semiconductor region 11b in the present embodiment are the same as those in the first embodiment.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Thereafter, as shown in FIG. 32, similarly to the first embodiment, metal silicide layers 12 are formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b, An insulating film 21 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2, an insulating film 22 is formed on the insulating film 21, contact holes 23 are formed in the insulating films 22 and 21, and contacts are formed. A plug 24 is formed in the hole 23. Then, similarly to the first embodiment, a stopper insulating film 25 and an insulating film 26 are formed in order on the insulating film 22 in which the plug 24 is embedded, and a wiring groove 27 is formed in the insulating film 26 and the stopper insulating film 25. Then, a barrier conductor film 28 is formed on the insulating film 26 including the bottom and side walls of the wiring groove 27, and the wiring groove 27 is filled with a copper main conductor film 29 to form the wiring M1.

  Next, the effect of this embodiment will be described in more detail.

  In the first and second embodiments, the channel is formed by forming the diffusion prevention regions 10a and 10b or the semiconductor layer 1b into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced. The diffusion of point defects to the region is prevented, thereby suppressing the density of point defects in the channel region, and the rearrangement (diffusion) of impurities introduced into the channel region by channel doping ion implantation is suppressed.

  On the other hand, in the present embodiment, the rearrangement (diffusion) of impurities introduced into the channel region by channel doping ion implantation is suppressed by devising the process order of channel doping ion implantation.

  When the insulating film 5 for the gate insulating film is formed by thermal oxidation, the heating temperature at the time of the thermal oxidation is as high as about 700 to 900 ° C., for example, unlike the present embodiment, before the insulating film 5 for the gate insulating film is formed. When channel dope ion implantation is performed, impurities introduced into the channel region by channel dope ion implantation are rearranged (diffusion) by heating at the time of forming the insulating film 5 for the gate insulating film (heating at the time of gate oxidation). )It's easy to do.

  Therefore, in this embodiment, after forming the insulating film 5 for the gate insulating film, channel doping ion implantation IM1a into the nMIS formation region 1A and channel doping ion implantation IM1b into the pMIS formation region 1B are performed to perform channel doping. Layers 4a and 4b are formed. By performing channel dope ion implantation IM1a and IM1b after forming the insulating film 5 for the gate insulating film, impurities introduced into the channel region by the channel doped ion implantation IM1a and IM1b are formed in the insulating film 5 for the gate insulating film. There is no rearrangement (diffusion) due to heating during heating (heating during gate oxidation). That is, even if the semiconductor substrate 1 is heated to a high temperature by forming the insulating film 5 for the gate insulating film by thermal oxidation, the channel dope ion implantation IM1a, IM1b is not performed at that stage, so that the subsequent channel Impurities introduced into the channel region by doped ion implantation IM1a and IM1b are not rearranged (diffused) by heating during thermal oxidation (gate oxidation). As a result, it is possible to suppress the impurities introduced into the channel region by the channel doping ion implantation from being rearranged (diffused) during the subsequent heating step, so the state of the channel region (impurity distribution) for each MISFET. ) Can be suppressed, and variations in threshold voltage for each MISFET can be suppressed. Therefore, the performance of the semiconductor device can be improved.

  In the present embodiment, after forming the insulating film 5 for the gate insulating film and further forming the silicon film 6a, channel doped ion implantation IM1a into the nMIS formation region 1A and channel doping ion implantation into the pMIS formation region 1B. IM1b is performed to form channel dope layers 4a and 4b. Channel doping ion implantation IM1a and IM1b is performed in a state where the insulating film 5 for gate insulating film is covered with the silicon film 6a (that is, the insulating film 5 is not exposed). It is possible to prevent the insulating film 5 from being damaged. Thereby, the reliability of the gate insulating films 5a and 5b can be improved, and the reliability of the semiconductor device can be improved.

  In addition, when channel doping ion implantation is performed in a state where a thick conductor film (gate electrode conductor film) corresponding to the height of the gate electrode is formed on the entire surface of the semiconductor substrate, the gate electrode conductor film is thick. There is a possibility that channel doping to the semiconductor substrate cannot be performed accurately. On the other hand, in this embodiment, channel dope ion implantation IM1a and IM1b is performed in a state where the silicon film 6a is formed, and then a silicon film 6b is formed on the silicon film 6a, and this laminated film is patterned. Thus, the gate electrodes GE1 and GE2 are formed. For this reason, the thickness t1 of the silicon film 6a can be made thinner than the height of the gate electrodes GE1 and GE2. Therefore, the thickness t1 of the silicon film 6a when performing channel dope ion implantation IM1a and IM1b can be reduced, and channel doping into the semiconductor substrate can be performed accurately.

  The thickness (deposited film thickness) t1 of the silicon film 6a is preferably smaller than the thickness (deposited film thickness) t2 of the silicon film 6b (that is, t1 <t2). That is, the height of the gate electrodes GE1 and GE2 corresponds to the sum of the thickness t1 of the silicon film 6a and the thickness t2 of the silicon film 6b (ie, t1 + t2), but the thickness (deposited film thickness) t1 of the silicon film 6a. Is preferably less than half the height of the gate electrodes GE1 and GE2. Thereby, since the thickness t1 of the silicon film 6a when performing channel dope ion implantation IM1a and IM1b can be reduced, channel dope ion implantation IM1a and IM1b can be performed more accurately.

  Further, in the present embodiment, channel doping ion implantation is performed after the formation of the insulating film 5 for the gate insulating film, thereby preventing the influence of heating when forming the insulating film 5 on the impurities in the channel region. If applied when the temperature when forming the insulating film 5 for the insulating film is high, the effect is great. For this reason, this embodiment is very effective when applied to the case where the insulating film 5 for the gate insulating film is formed by the thermal oxidation method.

Further, the third embodiment can be combined with the first and second embodiments. That is, in the third embodiment, the diffusion prevention regions 10a and 10b can be formed in the same manner as in the first embodiment. Also in this case, the configuration and the formation method of the diffusion prevention regions 10a and 10b are described above. This is the same as the first embodiment. In the third embodiment, the same semiconductor substrate SUB1 as in the second embodiment (that is, the semiconductor layer 1b formed on the semiconductor substrate 1a) can be used. In this case, in this embodiment, the channel region of the n-channel MISFET Qn and the p-channel MISFET Qp, the p-type well PW, the n-type well NW, the extension regions 7a and 7b, the halo regions 8a and 8b, and the n ⁺ -type semiconductor region 11a. The p ⁺ type semiconductor region 11b is formed in the semiconductor layer 1b into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced. Thereby, the effect of suppressing the rearrangement (diffusion) of channel dope impurities by performing channel dope ion implantation after the formation of the insulating film 5 for the gate insulating film, and the provision of the diffusion prevention regions 10a and 10b or the semiconductor layer 1b. It is possible to obtain both the effect of suppressing the rearrangement (diffusion) of channel doped impurities by preventing the diffusion of point defects into the channel region. Therefore, it is possible to more accurately suppress the variation in the state (impurity distribution) of the channel region for each MISFET, to more accurately suppress the variation in the threshold voltage for each MISFET, and to further improve the performance of the semiconductor device. be able to.

(Embodiment 4)
A manufacturing process of the semiconductor device according to the fourth embodiment will be described with reference to the drawings. 33 to 39 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

  In the present embodiment, as shown in FIG. 33, as in the first embodiment, first, a semiconductor substrate (semiconductor wafer) 1 is prepared, and an element isolation region 2 is formed on the main surface of the semiconductor substrate 1. .

  Next, as in the first embodiment, after the insulating film 3 is formed on the surface of the semiconductor substrate 1, a photoresist film RP1a covering the pMIS formation region 1B is formed.

  Next, in the nMIS formation region 1A, ion implantation for adjusting a threshold value of an n channel MISFET Qn (that is, channel dope ion implantation) IM1a is performed on the upper layer portion of the semiconductor substrate 1 later. In FIG. 34, this channel dope ion implantation IM1a is schematically indicated by an arrow. In the ion implantation IM1a for adjusting the threshold, that is, the channel dope ion implantation IM1a, impurities (impurity ions) are introduced (ion implantation) into a region including the channel region of the n-channel MISFET Qn to form the channel dope layer 4a. Therefore, the channel dope layer 4a includes a region that later becomes the channel region of the n-channel type MISFET Qn.

  In the present embodiment, one or both of indium (In) and gallium (Ga) is used as an element (impurity) introduced into the channel dope layer 4a by the channel dope ion implantation IM1a into the nMIS formation region 1A. Further, boron (B) can be combined. That is, whether the element (impurity) to be ion-implanted in the channel doping ion implantation step into the nMIS formation region 1A in this embodiment is indium (In), gallium (Ga), indium (In), and gallium (Ga). Boron (B) and indium (In), boron (B) and gallium (Ga), or boron (B), indium (In), and gallium (Ga). Note that in the channel dope ion implantation IM1a into the nMIS formation region 1A, the photoresist film RP1a covering the pMIS formation region 1B functions as an ion implantation blocking mask, so that ions are not implanted into the semiconductor substrate 1 in the pMIS formation region 1B. .

  Next, in the nMIS formation region 1A, a p-type well PW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth in the same manner as in the first embodiment. The formation method and configuration of the p-type well PW in the present embodiment are the same as those in the first embodiment.

  Next, as shown in FIG. 35, after the photoresist film RP1a is removed by ashing or the like, a photoresist film RP1b covering the nMIS formation region 1A is formed as in the first embodiment.

  Next, in the pMIS formation region 1B, ion implantation for adjusting a threshold value of a p-channel type MISFET Qp to be formed later (that is, channel dope ion implantation) IM1b is performed on the upper layer portion of the semiconductor substrate 1. In FIG. 35, this channel dope ion implantation IM1b is schematically indicated by an arrow. In this threshold adjustment ion implantation IM1b, that is, channel-doped ion implantation IM1b, impurities (impurity ions) are introduced (ion-implanted) into a region including the channel region of the p-channel MISFET Qp, and the channel-doped layer 4b is formed. Since it is formed, the channel dope layer 4b includes a region that will later become a channel region of the p-channel type MISFET Qp.

  In the present embodiment, the element (impurity) introduced into the channel dope layer 4b by the channel dope ion implantation IM1b into the pMIS formation region 1B uses one or both of arsenic (As) and antimony (Sb). Further, phosphorus (P) can be combined. That is, whether the element (impurity) to be ion-implanted in the channel doping ion implantation step into the pMIS formation region 1B in this embodiment is arsenic (As), antimony (Sb), arsenic (As), and antimony (Sb). Phosphorus (P) and arsenic (As), phosphorus (P) and antimony (Sb), or phosphorus (P), arsenic (As) and antimony (Sb). In the channel dope ion implantation IM1b into the pMIS formation region 1B, the photoresist film RP1a covering the nMIS formation region 1A functions as an ion implantation blocking mask, so that the ion implantation is not performed on the semiconductor substrate 1 in the nMIS formation region 1A. .

  Next, in the pMIS formation region 1B, an n-type well NW is formed from the main surface of the semiconductor substrate 1 to a predetermined depth in the same manner as in the first embodiment. The formation method and configuration of the n-type well NW in the present embodiment are the same as those in the first embodiment.

  Subsequent steps are the same as those in the first embodiment except that the step of forming diffusion prevention regions 10a and 10b (ion implantation IM5a and IM5b) is omitted.

  That is, as shown in FIG. 36, after removing the photoresist film RP1b, the insulating film 3 is removed to clean the surface of the semiconductor substrate 1, and then the semiconductors in the nMIS formation region 1A and the pMIS formation region 1B are obtained. An insulating film 5 for a gate insulating film is formed on the surface of the substrate 1 (surfaces of the p-type well PW and the n-type well NW), and gate electrodes GE1 and GE2 are formed on the insulating film 5. Then, as shown in FIG. 37, the extension region 7a and the halo region 8a are formed in the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A, and the semiconductor substrate 1 (n-type in the pMIS formation region 1B). An extension region 7b and a halo region 8b are formed in the well NW). The formation method and configuration of the insulating film 5, the gate electrodes GE1 and GE2, the extension regions 7a and 7b, and the halo regions 8a and 8b in the present embodiment are the same as those in the first embodiment.

Next, as shown in FIG. 38, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE1 and GE2, and then n is formed on the semiconductor substrate 1 (p-type well PW) in the nMIS formation region 1A. ^{A +} type semiconductor region 11a (source, drain) is formed, and a p ⁺ type semiconductor region 11b (source, drain) is formed in the semiconductor substrate 1 (n type well NW) in the pMIS formation region 1B. The formation method and configuration of the sidewall SW, the n ⁺ type semiconductor region 11a, and the p ⁺ type semiconductor region 11b in the present embodiment are the same as those in the first embodiment.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Thereafter, as shown in FIG. 39, similarly to the first embodiment, metal silicide layers 12 are formed on the surfaces of the gate electrodes GE1, GE2, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b, An insulating film 21 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2, an insulating film 22 is formed on the insulating film 21, contact holes 23 are formed in the insulating films 22 and 21, and contacts are formed. A plug 24 is formed in the hole 23. Then, similarly to the first embodiment, a stopper insulating film 25 and an insulating film 26 are formed in order on the insulating film 22 in which the plug 24 is embedded, and a wiring groove 27 is formed in the insulating film 26 and the stopper insulating film 25. Then, a barrier conductor film 28 is formed on the insulating film 26 including the bottom and side walls of the wiring groove 27, and the wiring groove 27 is filled with a copper main conductor film 29 to form the wiring M1.

  Next, the effect of this embodiment will be described in more detail.

  In the first to third embodiments, the impurities introduced by the channel dope ion implantation IM1a and IM1b are devised so that they are not easily diffused after the ion implantation. In contrast, in the present embodiment, elements (impurities) that are difficult to diffuse after channel doping ion implantation are implanted by channel doping ion implantation IM1a and IM1b.

  That is, an ion-implanted element (impurity) is more difficult to move (diffusion) by heating after ion implantation as the element with a larger atomic number (that is, heavier element) and stays at the position where ion implantation is performed. For this reason, when a light impurity element having a small atomic number is ion-implanted, the impurity element diffuses (moves) in various subsequent heating steps even if the implanted impurity element is randomly arranged in the stage immediately after the implantation. When the impurity element having a large atomic number is ion-implanted compared to the random arrangement of the impurity element, the random arrangement of the impurity element immediately after the implantation is performed in various subsequent heating steps. It is easy to maintain even after passing.

  Therefore, in this embodiment, an element having a large atomic number (that is, a heavy element) is used for channel dope ion implantation IM1a and IM1b.

  The nMIS formation region 1A (n-channel type MISFET Qn) will be described in detail. Elements used for the channel dope ion implantation IM1a into the nMIS formation region 1A (that is, impurity elements introduced into the channel dope layer 4a by the channel dope ion implantation IM1a) One or both of indium (In) and gallium (Ga) is used. Indium (In) and gallium (Ga) can function as p-type impurities like boron (B), but have a larger atomic number than boron (B) and are therefore heavier than boron (B). It is difficult to move (diffuse) by heating. For this reason, the impurity introduced into the channel dope layer 4a by the channel dope ion implantation IM1a (here, one or both of indium (In) and gallium (Ga)) is a random arrangement of the impurity element immediately after the implantation. It is easy to maintain even through various heating processes. Thereby, impurities (here, one or both of indium (In) and gallium (Ga)) introduced into the channel region (channel dope layer 4a) of the n-channel type MISFET Qn by the channel dope ion implantation IM1a are subjected to a subsequent heating step. In this case, rearrangement (diffusion) can be suppressed or prevented, so that variation in the state (impurity distribution) of the channel region for each n-channel MISFET can be suppressed. Therefore, variations in threshold voltage for each n-channel MISFET can be suppressed, and the performance of the semiconductor device can be improved.

  Further, as an element used for the channel dope ion implantation IM1a to the nMIS formation region 1A (that is, an impurity element introduced into the channel dope layer 4a by the channel dope ion implantation IM1a), one of indium (In) and gallium (Ga) or Although it is more preferable to use both, boron (B) can be further combined with this. In this case, even if the implanted boron (B) is diffused (moved) by the heating after the implantation and the random arrangement is destroyed, one or both of the implanted indium (In) and gallium (Ga) is heated after the implantation. Since it is easy to maintain a random arrangement even after passing through, it is possible to suppress variations in the state (impurity distribution) of the channel region for each n-channel type MISFET as compared with the case where only boron (B) is used for channel doping ion implantation. it can. For this reason, it is possible to suppress variations in threshold voltage for each n-channel type MISFET as compared with the case where only boron (B) is used for channel doping ion implantation.

  The pMIS formation region 1B (p channel type MISFET Qp) will be described in detail. Elements used for the channel dope ion implantation IM1b into the pMIS formation region 1B (that is, impurities introduced into the channel dope layer 4b by the channel dope ion implantation IM1b). As the element, one or both of arsenic (As) and antimony (Sb) is used. Arsenic (As) and antimony (Sb) can function as n-type impurities like phosphorus (P), but have a larger atomic number than phosphorus (P) and are therefore heavier than phosphorus (P). It is difficult to move (diffuse) by heating. For this reason, the impurity introduced into the channel dope layer 4b by the channel dope ion implantation IM1b (here, one or both of arsenic (As) and antimony (Sb)) is a random arrangement of the impurity element immediately after the implantation. It is easy to maintain even through various heating processes. Thereby, impurities (here, one or both of arsenic (As) and antimony (Sb)) introduced into the channel region (channel doped layer 4b) of the p-channel type MISFET Qp by the channel-doped ion implantation IM1b are heated in the subsequent heating step. In this case, rearrangement (diffusion) can be suppressed or prevented, so that variation in the state (impurity distribution) of the channel region for each p-channel MISFET can be suppressed. Therefore, variation in threshold voltage for each p-channel MISFET can be suppressed, and the performance of the semiconductor device can be improved.

  In addition, as an element used for channel dope ion implantation IM1b into pMIS formation region 1B (that is, an impurity element introduced into channel dope layer 4b by channel dope ion implantation IM1b), one of arsenic (As) and antimony (Sb) or Although it is more preferable to use both, phosphorus (P) can also be combined with this. In this case, even if the injected phosphorus (P) is diffused (moved) by the heating after the injection and the random arrangement is destroyed, one or both of the injected arsenic (As) and antimony (Sb) are heated after the injection. Since it is easy to maintain a random arrangement even after passing through, it is possible to suppress variations in the state (impurity distribution) of the channel region for each p-channel type MISFET as compared with the case where only phosphorus (P) is used for channel doping ion implantation. it can. For this reason, it is possible to suppress variation in threshold voltage for each p-channel type MISFET as compared with the case where only phosphorus (P) is used for channel dope ion implantation.

  In each of the first, second, and third embodiments, or a combination thereof, the types of impurity elements used for channel dope ion implantation IM1a and IM1b can be the same as those in the fourth embodiment.

  For example, in the first embodiment, one or both of indium (In) and gallium (Ga), or a combination of boron (B) with the channel doped ion implantation IM1a into the nMIS formation region 1A is used. In addition, one or both of arsenic (As) and antimony (Sb), or a combination of phosphorus and phosphorus (P) can be used for the channel dope ion implantation IM1b into the pMIS formation region 1B. As a result, the same impurity element as in the fourth embodiment is implanted by the channel dope ion implantation IM1a and IM1b, so that the implanted impurity element itself is less likely to move (diffusion) by the heating after the implantation. By forming the diffusion prevention regions 10a and 10b as in the first embodiment, the density of point defects in the channel region is suppressed, and the impurity element is less likely to move (diffuse) through the point defects in the channel region. it can.

  In the second embodiment, the channel dope ion implantation IM1a into the nMIS formation region 1A includes one or both of indium (In) and gallium (Ga), or a combination of boron and (B). In addition, one or both of arsenic (As) and antimony (Sb), or a combination of phosphorus and phosphorus (P) can be used for the channel dope ion implantation IM1b into the pMIS formation region 1B. As a result, the same impurity element as in the fourth embodiment is implanted by channel dope ion implantation, so that the implanted impurity element itself is less likely to move (diffusion) by heating after implantation. Further, the n-channel MISFET Qn and the p-channel MISFET Qp are formed in the semiconductor layer 1b into which one or more of carbon (C), nitrogen (N), or fluorine (F) is introduced as in the second embodiment. Accordingly, it is possible to suppress the density of point defects in the channel region and to make it difficult for the impurity element to move (diffuse) through the point defect in the channel region.

  Further, in the third embodiment, one or both of indium (In) and gallium (Ga), or a combination of boron (B) with the channel dope ion implantation IM1a into the nMIS formation region 1A is used. In addition, one or both of arsenic (As) and antimony (Sb), or a combination of phosphorus and phosphorus (P) can be used for the channel dope ion implantation IM1b into the pMIS formation region 1B. As a result, the same impurity element as in the fourth embodiment is implanted by channel dope ion implantation, so that the implanted impurity element itself is less likely to move (diffusion) by the heating after the implantation, and further the above-described embodiment. As shown in FIG. 3, the channel doping ion implantation is performed after the insulating film 5 for the gate insulating film is formed, so that the heating process (gate oxidation process) after the channel doping ion implantation can be reduced.

  Further, for example, in the combination of the first embodiment and the third embodiment, the types of impurity elements used for the channel dope ion implantation IM1a and IM1b can be the same as those in the fourth embodiment. Further, in the combination of the second embodiment and the third embodiment, the types of impurity elements used for the channel dope ion implantation IM1a and IM1b can be the same as those in the fourth embodiment.

  As described above, in each of the first, second, and third embodiments, or a combination thereof, the types of impurity elements used for the channel dope ion implantation IM1a and IM1b are the same as those in the fourth embodiment. Thus, the random arrangement immediately after the implantation of the impurities introduced into the channel region by the channel dope ion implantation can be maintained more accurately after the implantation. For this reason, it is possible to more accurately suppress the variation in the state (impurity distribution) of the channel region for each MISFET, to more accurately suppress the variation in the threshold voltage for each MISFET, and to improve the performance of the semiconductor device more accurately. Can be improved.

(Embodiment 5)
FIG. 40 is a plan view showing an example of the semiconductor device (semiconductor chip) SM1 manufactured through the manufacturing steps according to the first to fourth embodiments or a combination thereof.

  The semiconductor device SM1 of the present embodiment includes a memory region (memory circuit region, memory cell array region, SRAM region) 31 in which a memory cell array such as SRAM (Static Random Access Memory) is formed, and a circuit (peripheral circuit) other than the memory. And a peripheral circuit region 32 in which is formed. The peripheral circuit area 32 includes, for example, an analog circuit area in which an analog circuit is formed, a CPU area in which a control circuit is formed, and the like. The memory region 31 and the peripheral circuit region 32 or between the peripheral circuit regions 32 are electrically connected as necessary via an internal wiring layer of the semiconductor device SM1. In addition, a plurality of pad electrodes PD are formed along the four sides of the main surface of the semiconductor device SM1 at the periphery of the main surface (front surface) of the semiconductor device SM1. Each pad electrode PD is electrically connected to the memory region 31 and the peripheral circuit region 32 through the internal wiring layer of the semiconductor device SM1.

  In the present embodiment, when manufacturing the semiconductor device SM1, any one of the manufacturing techniques of the first to fourth embodiments or a combination thereof can be used. Here, the manufacturing technique of the first embodiment corresponds to providing the diffusion prevention regions 10a and 10b. The manufacturing technique of the second embodiment corresponds to providing the semiconductor layer 1b and forming a MISFET there. The manufacturing technique of the third embodiment is that the channel doped ion implantation IM1a, IM1b is performed after the formation of the insulating film 5 for the gate insulating film and the silicon film 6a, and then the silicon film 6b is formed on the silicon film 6a. This corresponds to forming a gate electrode by patterning the laminated film (silicon films 6a and 6b). The manufacturing technique of the fourth embodiment corresponds to selecting the type of element to be implanted by channel dope ion implantation IM1a and IM1b as in the fourth embodiment.

  In manufacturing the semiconductor device SM1, when the manufacturing technique of the third embodiment is applied, the MISFETs in all regions (the memory region 31 and the peripheral circuit region 32) in the semiconductor device SM1 (semiconductor substrate 1) are applied. The semiconductor device manufacturing process can be simplified.

  On the other hand, in manufacturing the semiconductor device SM1, when the manufacturing techniques (single or combined) of the first, second, and fourth embodiments are applied, all the regions (the memory region 31 and the peripheral circuit region 32 of the semiconductor device SM1) are applied. However, the peripheral circuit area 32 is mixed with the peripheral circuit area 32a to be applied and the peripheral circuit area 32b not to be applied. The peripheral circuit area 32b that is not applied is, for example, the analog circuit area or the CPU area. 40 is a plan view, but in order to facilitate understanding, hatching is applied to the memory region 31 and the peripheral circuit region 32a to which the manufacturing techniques (single or combined) of the first, second, and fourth embodiments are applied. It is attached.

  First, the case where the manufacturing technique of the first embodiment is applied in manufacturing the semiconductor device SM1 will be described. In this case, in the memory region 31 and the peripheral circuit region 32a, those corresponding to the diffusion preventing regions 10a and 10b are formed when the n-channel MISFET and the p-channel MISFET are formed. On the other hand, in the peripheral circuit region 32b, when the n-channel MISFET and the p-channel MISFET are formed, those corresponding to the diffusion preventing regions 10a and 10b are not formed.

  Next, a case where the manufacturing technique of the second embodiment is applied when manufacturing the semiconductor device SM1 will be described. In this case, in the memory region 31 and the peripheral circuit region 32a, a region corresponding to the semiconductor layer 1b (a semiconductor layer into which one or more of carbon, nitrogen, and fluorine are introduced) is formed by ion implantation. An n-channel MISFET and a p-channel MISFET are formed there. On the other hand, in the peripheral circuit region 32b, the region corresponding to the semiconductor layer 1b is not formed, and the n-channel MISFET and the p-channel are formed in the substrate region (semiconductor substrate region into which carbon, nitrogen, or fluorine is not introduced). A type MISFET is formed.

  Next, a case where the manufacturing technique of the fourth embodiment is applied when manufacturing the semiconductor device SM1 will be described. In this case, in the memory region 31 and the peripheral circuit region 32a, the same kind of element as the channel dope ion implantation IM1a performed for the nMIS formation region 1A in the fourth embodiment is used for the channel dope ion implantation of the n channel MISFET. In the channel dope ion implantation of the p-channel type MISFET, the same element as the channel dope ion implantation IM1b performed for the pMIS formation region 1B in the fourth embodiment is used. On the other hand, in the peripheral circuit region 32a, only boron (B) is used for channel doping ion implantation of the n-channel MISFET, and only phosphorus (P) is used for channel doping ion implantation of the p-channel MISFET. .

  As an example, a case where the semiconductor device SM1 is manufactured by applying the manufacturing technique of the first embodiment and the manufacturing technique of the fourth embodiment will be specifically described below with reference to FIGS. . In this case, the manufacturing technique of the first embodiment and the manufacturing technique of the fourth embodiment are applied to the memory area 31 and the peripheral circuit area 32a, but the peripheral circuit area 32b is the same as that of the first embodiment. The manufacturing technique and the manufacturing technique of the fourth embodiment are not applied.

  41 to 47 are principal part cross-sectional views during the manufacturing process of the semiconductor device SM1 of the present embodiment, in the case of manufacturing the semiconductor device SM1 by applying the first embodiment and the fourth embodiment. A cross-sectional view of the main part is shown.

  In the present embodiment, as in the first embodiment, first, a semiconductor substrate (semiconductor wafer) 1 is prepared. FIG. 41 shows a part of the memory region 31, a part of the peripheral circuit region 32a, and a part of the peripheral circuit region 32b in the semiconductor substrate 1.

  Among the memory regions 31, FIG. 41 shows a memory nMIS formation region 1C, which is a region where an n-channel MISFET constituting the memory (memory cell) is formed, and a p-channel MISFET constituting the memory (memory cell). A memory pMIS formation region 1D, which is a region to be formed, is shown.

  In the peripheral circuit region 32, MISFETs having different breakdown voltages are formed. Therefore, FIG. 41 shows a low breakdown voltage nMIS formation region 1L1, which is a region where a low breakdown voltage n-channel MISFET is formed in the peripheral circuit region 32a. Also, FIG. 41 shows a low breakdown voltage nMIS formation region 1L2, which is a region where a low breakdown voltage n-channel MISFET is formed in the peripheral circuit region 32b, and a high breakdown voltage nMIS, which is a region where a high breakdown voltage n-channel MISFET is formed. A formation region 1H is shown.

  In order to manufacture the semiconductor device SM1, as shown in FIG. 41, first, a semiconductor substrate (semiconductor wafer) 1 is prepared as in the first embodiment. Then, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1.

  Next, after the insulating film 3 similar to that of the first embodiment is formed on the surface of the semiconductor substrate 1, as shown in FIG. 42, the p-type well PW1 is formed in the memory nMIS formation region 1C, and the memory pMIS formation region. An n-type well NW1 is formed in 1D, a p-type well PW2 is formed in the low breakdown voltage nMIS formation region 1L1, a p-type well PW3 is formed in the low breakdown voltage nMIS formation region 1L2, and a p-type well PW4 is formed in the high breakdown voltage nMIS formation region 1H. . The p-type wells PW1, PW2, PW3, PW4 and the n-type well NW1 can be formed by ion implantation using a photoresist film (not shown) as an ion implantation blocking mask, respectively. Ion implantation for forming the p-type well PW1, ion implantation for forming the p-type well PW2, ion implantation for forming the p-type well PW3, and ion implantation for forming the p-type well PW4, Although the number of steps can be reduced if the same ion implantation step is performed, the steps may be performed as different ion implantation steps.

  Next, channel dope ion implantation (for the MISFET formed therein) is performed in each of the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L1, the low breakdown voltage nMIS formation region 1L2, and the high breakdown voltage nMIS formation region 1H. (Ion implantation for threshold adjustment) IM1c, IM1d, IM1e, IM1f, IM1g are performed. In FIG. 42, channel dope ion implantation IM1c, IM1d, IM1e, IM1f, IM1g is schematically shown by arrows.

  The channel dope ion implantation IM1c forms a channel dope layer 4c in the upper layer portion of the semiconductor substrate 1 (p-type well PW1) in the memory nMIS formation region 1C. Further, the channel dope ion implantation IM1d forms the channel dope layer 4d in the upper layer portion of the semiconductor substrate 1 (n-type well NW1) in the memory pMIS formation region 1D. Further, the channel dope ion implantation IM1e forms the channel dope layer 4e in the upper layer portion of the semiconductor substrate 1 (p-type well PW2) in the low breakdown voltage nMIS formation region 1L1. Further, the channel dope ion implantation IM1f forms the channel dope layer 4f in the upper layer portion of the semiconductor substrate 1 (p-type well PW3) in the low breakdown voltage nMIS formation region 1L2. Further, the channel dope ion implantation IM1g forms a channel dope layer 4g in the upper layer portion of the semiconductor substrate 1 (p-type well PW4) in the high breakdown voltage nMIS formation region 1H. The channel dope layers 4c, 4d, 4e, 4f, and 4g are formed in the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L1, the low breakdown voltage nMIS formation region 1L2, and the high breakdown voltage nMIS formation region 1H. A region to be a channel region of each MISFET is included.

  In the present embodiment, the channel dope ion implantation IM1c into the memory nMIS formation region 1C and the channel dope ion implantation IM1e into the low breakdown voltage nMIS formation region 1L1 are performed on the nMIS formation region 1A in the fourth embodiment. The same kind of element (impurity element) as channel doped ion implantation IM1a is implanted. That is, one or both of indium (In) and gallium (Ga) as an element (impurity element) implanted by channel dope ion implantation IM1c and IM1e into the memory nMIS formation region 1C and the low breakdown voltage nMIS formation region 1L1, or this Further, a combination of boron (B) is used.

  In addition, in the channel dope ion implantation IM1d into the memory pMIS formation region 1D, the same type of element (impurity element) as the channel dope ion implantation IM1b performed in the pMIS formation region 1B in the fourth embodiment is ion-implanted. That is, one or both of arsenic (As) and antimony (Sb) as an element (impurity element) implanted by channel doping ion implantation IM1d into the memory pMIS formation region 1D, or further combined with phosphorus (P) Use things.

  On the other hand, in the channel dope ion implantation IM1f into the low breakdown voltage nMIS formation region 1L2 and the channel dope ion implantation IM1g into the high breakdown voltage nMIS formation region 1H, unlike the fourth embodiment, only boron (B) is ion-implanted. To do. That is, only boron (B) is used as an element (impurity element) implanted by channel dope ion implantation IM1f and IM1g into the low breakdown voltage nMIS formation region 1L2 and the high breakdown voltage nMIS formation region 1H. Although not shown in FIG. 42, in the peripheral circuit region 32b, when channel-doped ions are implanted into a region where a p-channel MISFET is formed, phosphorus (impurity element) is used as an implanted element (impurity element). Only P) is used.

  Note that when performing channel doped ion implantation IM1c into the memory nMIS formation region 1C, a photoresist film (not shown) covering the memory pMIS formation region 1D, the low breakdown voltage nMIS formation regions 1L1, 1L2, and the high breakdown voltage nMIS formation region 1H. ) May be used as an ion implantation blocking mask. Further, when performing channel dope ion implantation IM1d to the memory pMIS formation region 1D, a photoresist film (not shown) covering the memory nMIS formation region 1C, the low breakdown voltage nMIS formation regions 1L1, 1L2, and the high breakdown voltage nMIS formation region 1H. ) May be used as an ion implantation blocking mask. Further, when performing channel dope ion implantation IM1e to the low breakdown voltage nMIS formation region 1L1, a photoresist covering the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L2, and the high breakdown voltage nMIS formation region 1H. A film (not shown) may be used as an ion implantation blocking mask. Further, when performing channel dope ion implantation IM1f into the low breakdown voltage nMIS formation region 1L2, a photoresist covering the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L1, and the high breakdown voltage nMIS formation region 1H. A film (not shown) may be used as an ion implantation blocking mask. Further, when performing channel dope ion implantation IM1g into the high breakdown voltage nMIS formation region 1H, a photoresist film (not shown) covering the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation regions 1L1, 1L2. ) May be used as an ion implantation blocking mask.

  When the doping amount of the channel dope ion implantation IM1c in the memory nMIS formation region 1C and the doping amount of the channel dope ion implantation IM1e in the low breakdown voltage nMIS formation region 1L1 may be the same, the channel doping ion implantation IM1c in the memory nMIS formation region 1C And channel doping ion implantation IM1e for the low breakdown voltage nMIS formation region 1L1 can be performed in the same ion implantation step. Further, when the doping amount of the channel dope ion implantation IM1f in the low breakdown voltage nMIS formation region 1L2 and the doping amount of the channel dope ion implantation IM1g in the high breakdown voltage nMIS formation region 1H may be the same, channel doping ions for the low breakdown voltage nMIS formation region 1L2 Implantation IM1f and channel dope ion implantation IM1g for high breakdown voltage nMIS formation region 1H can also be performed in the same ion implantation step.

  Next, after the insulating film 3 is removed and the surface of the semiconductor substrate 1 is cleaned, a memory gate is formed on the semiconductor substrate 1 in the memory nMIS formation region 1C and the memory pMIS formation region 1D, as shown in FIG. An insulating film 5c is formed by applying a low breakdown voltage gate insulating film 5d on the semiconductor substrate 1 in the low breakdown voltage nMIS formation regions 1L1 and 1L2, and forming a high breakdown voltage gate insulating film 5e on the semiconductor substrate 1 in the high breakdown voltage nMIS formation region 1H. , Form each. The high breakdown voltage gate insulating film 5e is thicker and has a higher breakdown voltage than the memory gate insulating film 5c and the low breakdown voltage gate insulating film 5d.

  The gate insulating films 5c, 5d, and 5e having different thicknesses can be formed as follows, for example.

  That is, after an insulating film for the gate insulating film 5e is formed on the entire main surface of the semiconductor substrate 1 by thermal oxidation, CVD, or the like, the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation region 1L1 are etched. , 1L2, this insulating film is removed, and this insulating film is left in the high breakdown voltage nMIS formation region 1H. Then, a silicon oxide film is formed on the main surface of the semiconductor substrate by thermal oxidation. Thereby, gate insulating films 5c and 5d made of a thin silicon oxide film (thermal oxide film) are formed on the semiconductor substrate 1 in the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation regions 1L1 and 1L2. At the same time, the thickness of the insulating film for the gate insulating film 5e is increased in the high breakdown voltage nMIS formation region 1H, resulting in a thick gate insulating film 5e. When it is necessary to make the gate insulating film 5c thinner than the gate insulating film 5d, the silicon oxide film on the surface of the semiconductor substrate 1 in the memory nMIS formation region 1C and the memory pMIS formation region 1D is removed by etching, and then heat is applied again. A silicon oxide film may be formed on the main surface of the semiconductor substrate by oxidation.

  Since the high breakdown voltage gate insulating film 5e is thicker than the memory gate insulating film 5c and the low breakdown voltage gate insulating film 5d, the breakdown voltage of the MISFET formed in the high breakdown voltage nMIS formation region 1H is the memory nMIS formation region. 1C, higher than the breakdown voltage of the MISFET formed in the memory pMIS formation region 1D and the low breakdown voltage nMIS formation regions 1L1, 1L2.

  Next, a silicon film such as a polycrystalline silicon film is formed over the entire main surface of the semiconductor substrate 1 as a conductive film for forming a gate electrode, and this silicon film is formed using a photolithography method and a dry etching method. By patterning, gate electrodes GE3, GE4, GE5, GE6, and GE7 are formed as shown in FIG. In FIG. 44 and later-described FIGS. 45 to 47, the channel dope layers 4c, 4d, 4e, 4f, and 4g are omitted for easy understanding of the drawings.

  The gate electrode GE3 is formed on the p-type well PW1 via the gate insulating film 5c in the memory nMIS formation region 1C. The gate electrode GE4 is formed on the n-type well NW1 via the gate insulating film 5c in the memory pMIS formation region 1D. The gate electrode GE5 is formed on the p-type well PW2 via the gate insulating film 5d in the low breakdown voltage nMIS formation region 1L1. The gate electrode GE6 is formed on the p-type well PW3 through the gate insulating film 5d in the low breakdown voltage nMIS formation region 1L2. The gate electrode GE7 is formed on the p-type well PW4 via the gate insulating film 5e in the high breakdown voltage nMIS formation region 1H.

  Next, as shown in FIG. 45, as in the first embodiment, extension is performed on the semiconductor substrate 1 (p-type wells PW1, PW2) in the memory nMIS formation region 1C and the low breakdown voltage nMIS formation region 1L1 by ion implantation. Region 7a, halo region 8a and diffusion preventing region 10a are formed. Similarly to the first embodiment, the extension region 7b, the halo region 8b, and the diffusion prevention region 10b are formed by ion implantation in the semiconductor substrate 1 (n-type well NW1) in the memory pMIS formation region 1D. Further, an extension region 7a and a halo region 8a are formed by ion implantation in the semiconductor substrate 1 (p-type well PW3) in the low breakdown voltage nMIS formation region 1L2, and the region corresponding to the diffusion prevention region 10a corresponds to the low breakdown voltage nMIS formation region. It is not formed on 1L2. For simplification of the drawing, the halo regions 8a and 8b are not shown in FIG.

  In the present embodiment, the memory nMIS formation region 1C and the low breakdown voltage nMIS formation region 1L1 except that the gate electrode GE1 becomes the gate electrodes GE3 and GE5 and the p-type well PW becomes the p-type wells PW1 and PW2. The formation method and configuration of the extension region 7a, the halo region 8a, and the diffusion prevention region 10a are the same as those in the first embodiment, and a description thereof is omitted here. In the present embodiment, the extension region 7b, the halo region 8b, and the halo region 8b in the memory pMIS formation region 1D, except that the gate electrode GE2 is the gate electrode GE4 and the n-type well NW is the n-type well NW1. Since the formation method and configuration of the diffusion preventing region 10b are the same as those in the first embodiment, the description thereof is omitted here. In addition, the low breakdown voltage nMIS formation region 1L2 is not formed in the low breakdown voltage nMIS formation region 1L2 except for the formation corresponding to the diffusion prevention region 10a. The formation and configuration of the extension region 7a and the halo region 8a in the low breakdown voltage nMIS formation region 1L2 are as follows. This is the same as the extension region 7a and the halo region 8a in the formation region 1L1.

  When the extension region 7a, the halo region 8a, and the diffusion prevention region 10a are formed in the memory nMIS formation region 1C and the low breakdown voltage nMIS formation region 1L1, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L2, and the high breakdown voltage nMIS are formed. A photoresist film (not shown) that covers the formation region 1H may be used as an ion implantation blocking mask. When the extension region 7b, the halo region 8b, and the diffusion prevention region 10b are formed in the memory pMIS formation region 1D, the memory nMIS formation region 1C, the low breakdown voltage nMIS formation regions 1L1, 1L2, and the high breakdown voltage nMIS formation region 1H are covered. A photoresist film (not shown) may be used as an ion implantation blocking mask. Further, when the extension region 7a and the halo region 8a are formed in the low breakdown voltage nMIS formation region 1L2, a photoresist film covering the memory nMIS formation region 1C, the memory pMIS formation region 1D, and the low breakdown voltage nMIS formation regions 1L1, 1L2 (FIG. (Not shown) may be used as an ion implantation blocking mask.

  Next, as shown in FIG. 46, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE3, GE4, GE5, GE6, and GE7 as in the first embodiment.

Next, in the same manner as in the first embodiment, the semiconductor substrate 1 (p-type wells PW1, PW2, PW3, PW4) in the memory nMIS formation region 1C, the low breakdown voltage nMIS formation regions 1L1, 1L2, and the high breakdown voltage nMIS formation region 1H is used. An n ⁺ type semiconductor region 11a (source, drain) is formed by ion implantation. Also, ap ⁺ type semiconductor region 11b (source, drain) is formed in the semiconductor substrate 1 (n-type well NW1) in the memory pMIS formation region 1D by ion implantation in the same manner as in the first embodiment. The formation method and configuration of the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b in the present embodiment are the same as those in the first embodiment.

When the n ⁺ type semiconductor region 11a is formed in the memory nMIS formation region 1C, the low breakdown voltage nMIS formation regions 1L1 and 1L2, and the high breakdown voltage nMIS formation region 1H, a photoresist film (not shown) covering the memory pMIS formation region 1D. May be used as an ion implantation blocking mask. Further, when the p ⁺ type semiconductor region 11b is formed in the memory pMIS formation region 1D, a photoresist film (not shown) covering the memory nMIS formation region 1C, the low breakdown voltage nMIS formation regions 1L1, 1L2, and the high breakdown voltage nMIS formation region 1H. May be used as an ion implantation blocking mask.

  Next, similarly to the first embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Subsequent steps are substantially the same as those in the first embodiment. That is, as shown in FIG. 47, similarly to the first embodiment, the metal silicide layers 12 are formed on the surfaces of the gate electrodes GE3 to GE7, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b, An insulating film 21 is formed on the main surface of the semiconductor substrate 1 so as to cover the gate electrodes GE <b> 3 to GE <b> 7, and an insulating film 22 is formed on the insulating film 21. In FIG. 47, for the sake of simplification of the drawing, the illustration of the insulating film 21 is omitted, and the insulating film 21 is included in the insulating film 22 for illustration. Then, contact holes 23 are formed in the insulating films 22 and 21, and plugs 24 are formed in the contact holes 23. Then, similarly to the first embodiment, a stopper insulating film 25 and an insulating film 26 are formed in order on the insulating film 22 in which the plug 24 is embedded, and a wiring groove 27 is formed in the insulating film 26 and the stopper insulating film 25. Then, the wiring M 1 is formed in the wiring groove 27. In FIG. 47, for the sake of simplification, the illustration of the stopper insulating film 25 is omitted, and the stopper insulating film 25 is included in the insulating film 26 for illustration.

  Next, the manufacturing techniques of the first, second, and fourth embodiments are applied to the memory area 31 and the peripheral circuit area 32a, and the manufacturing techniques of the first, second, and fourth embodiments are not applied to the peripheral circuit area 32b. The reason will be explained.

  In the memory region 31, since many MISFETs constituting the memory cell are arranged, it is desired to reduce the size of each MISFET. However, the influence (threshold voltage fluctuation) caused by the rearrangement (diffusion) of the impurities implanted by the channel adjustment ion implantation for threshold adjustment described above is caused by miniaturizing the MISFET. As the gate length (channel length) becomes shorter, it becomes larger. This is because the ratio of the channel doping impurity diffusion amount (movement amount from the position immediately after implantation) to the channel length increases as the gate length (channel length) decreases even if the diffusion amount is the same. This is because the amount of variation (variation) of the region state (impurity distribution) is increased. For this reason, in the MISFET that has been miniaturized and the gate length is shortened, the influence (impact on the threshold voltage) caused by the rearrangement (diffusion) of the impurities implanted by the channel dope ion implantation is caused in the subsequent heating process. It is very important to suppress it. Also in the peripheral circuit region 32 other than the memory region 31, in the peripheral circuit region 32a in which the MISFET having been miniaturized and the gate length shortened is formed, the impurities implanted by the channel dope ion implantation are caused in the subsequent heating process. It is extremely important to suppress the influence (the influence on the threshold voltage) due to the rearrangement (diffusion). In addition, it is extremely important to reduce the variation in the threshold voltage of each MISFET (MISFET constituting the memory cell) in the memory region 31 in order to operate the memory.

  Therefore, in the present embodiment, the manufacturing technique of the fourth embodiment is applied to the memory region 31 and the peripheral circuit region 32a where the MISFET having a short gate length is formed. That is, in the memory region 31 and the peripheral circuit region 32a, when channel-doped ions are implanted with p-type impurities, one or both of indium (In) and gallium (Ga), or boron (B) is further combined with this. When n-type impurities are channel-doped ion-implanted, one or both of arsenic (As) and antimony (Sb), or a combination of phosphorus (P) is further used. In the present embodiment, the manufacturing technique of the first embodiment is applied to the memory region 31 and the peripheral circuit region 32a where the MISFET having a short gate length is formed, and carbon (C), nitrogen (N) or One or more kinds of fluorine (F) are ion-implanted to form the diffusion prevention regions 10a and 10b.

  As a result, in the memory region 31 and the peripheral circuit region 32a where the MISFET having a short gate length is formed, the same impurity element as in the fourth embodiment is channel-doped ion implanted, so that the implanted impurity itself moves ( In addition, since the diffusion prevention regions 10a and 10b are formed as in the first embodiment, the density of point defects in the channel region is suppressed, and impurities move through the point defects in the channel region ( Difficult to diffuse). Accordingly, in the memory region 31 and the peripheral circuit region 32a that are easily affected by the rearrangement (diffusion) of the channel-doped impurities in the subsequent heating step, the channel-doped impurities are randomly arranged immediately after the implantation. Since it can be accurately maintained even after implantation, variation in channel region state (impurity distribution) for each MISFET can be suppressed, and variation in threshold voltage for each MISFET can be suppressed. For this reason, the performance of the semiconductor device SM1 can be improved.

  On the other hand, in the peripheral circuit region 32b where a MISFET having a gate length longer than that of the MISFET in the memory region 31 and the peripheral circuit region 32a is formed, the channel-doped impurities are rearranged (diffused) in the subsequent heating process. The influence of the above (the influence on the threshold voltage) is smaller than that of the memory area 31 and the peripheral circuit area 32b.

  Therefore, in the present embodiment, in the peripheral circuit region 32b where the MISFET having a long gate length is formed, when the p-type impurity is channel-doped ion-implanted without applying the manufacturing technique of the fourth embodiment, When only boron (B) is used and n-type impurities are channel-doped ion-implanted, only phosphorus (P) is used. In the present embodiment, the manufacturing technique of the first embodiment is not applied to the peripheral circuit region 32b where the MISFET having a long gate length is formed, and carbon (C), nitrogen (N), or fluorine (F ) Are not formed in the diffusion prevention regions 10a and 10b.

  Compared to boron (B), indium (In) and gallium (Ga) have a small diffusion coefficient and are difficult to move (diffusion) by heating after ion implantation, but the activation rate is indium (In) and gallium ( Boron (B) is larger than Ga). In addition, arsenic (As) and antimony (Sb) have a small diffusion coefficient and are less likely to move (diffusion) by heating after ion implantation compared to phosphorus (P), but the activation rate is arsenic (As) and Phosphorus (P) is larger than antimony (Sb).

  Therefore, in this embodiment, in the peripheral circuit region 32b, when the p-type impurity is channel-doped ion-implanted without applying the manufacturing technique of the fourth embodiment, only boron (B) is used, and n When channel-doped impurities are implanted with channel-doped ions, the activation rate of the impurities implanted with channel-doped ions in the peripheral circuit region 32b can be increased by using only phosphorus (P). By increasing the impurity activation rate, the resistance component of the MISFET can be reduced.

  In addition, carbon (C), nitrogen (N), and fluorine (F) are introduced as compared with a substrate region into which one or more of carbon (C), nitrogen (N), and fluorine (F) are ion-implanted. The activation rate of the n-type impurity (for example, phosphorus) or the p-type impurity (for example, boron) can be increased in the non-substrate region. For this reason, in this embodiment, the n-type impurity introduced into the peripheral circuit region 32b is not applied to the peripheral circuit region 32b by not applying the manufacturing technique of the first embodiment and forming the diffusion prevention regions 10a and 10b. Since the activation rate of (for example, phosphorus) or p-type impurities (for example, boron) can be increased, the resistance component of the MISFET can be easily lowered.

  In FIGS. 41 to 47, the case where the manufacturing techniques of the first and fourth embodiments are applied to manufacture the semiconductor device SM1, but FIG. 48 illustrates the above-described case of manufacturing the semiconductor device SM1. FIG. 44 is a main-portion cross-sectional view of the semiconductor device SM1 during the manufacturing process when the manufacturing technology of Embodiment 2 is applied, and corresponds to FIG. 41 described above.

When manufacturing the semiconductor device SM1, when the manufacturing technique of the second embodiment is applied, as shown in FIG. 48, the memory region 31 and the peripheral circuit region 32a (the region hatched in FIG. 40). ), A region corresponding to the semiconductor layer 1b, that is, a semiconductor region 1b1 into which one or more of carbon (C), nitrogen (N), and fluorine (F) are introduced is formed by ion implantation. Ion implantation (implantation of one or more of carbon, nitrogen, or fluorine) for forming the semiconductor region 1b1 is performed only in the memory region 31 and the peripheral circuit region 32a, and other regions (particularly the peripheral circuit region 32b). ) So that carbon, nitrogen and fluorine are not ion-implanted. Thus, in the peripheral circuit region 32b, the semiconductor region 1b1 corresponding to the semiconductor layer 1b is not formed, and carbon (C), nitrogen (N) and fluorine (F) are all introduced into the entire peripheral circuit region 32b. A semiconductor substrate region that is not formed can be formed. Since the other steps are the same as those described in FIGS. 41 to 47, detailed description thereof is omitted here, but by providing the semiconductor region 1b1 in the memory region 31 and the peripheral circuit region 32a, The formation of the diffusion preventing regions 10a and 10b in the memory region 31 and the peripheral circuit region 32a can be omitted. The p-type wells PW1 and PW2, the n-type well NW1, the extension regions 7a and 7b, the halo regions 8a and 8b, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b in the memory region 31 and the peripheral circuit region 32a are Thus, it is formed in the semiconductor region 1b1. The p-type wells PW3 and PW4, the extension regions 7a and 7b, the halo regions 8a and 8b, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b in the peripheral circuit region 32b are not the semiconductor region 1b1, but the semiconductor substrate. 1, it is formed in a substrate region into which any of carbon, nitrogen, and fluorine is not introduced.

  As described above, when the manufacturing technique of the second embodiment is applied to manufacture the semiconductor device SM1, the memory region 31 and the peripheral circuit region 32a are made of carbon, nitrogen, or fluorine corresponding to the semiconductor layer 1b. A semiconductor region 1b1 into which one or more of them are introduced is formed by ion implantation, and an n-channel MISFET and a p-channel MISFET are formed in the semiconductor region 1b1. On the other hand, in the peripheral circuit region 32b, the n-channel MISFET and the p-channel MISFET are not formed in the semiconductor substrate region into which any of carbon, nitrogen, and fluorine is not introduced without forming the semiconductor region 1b1 corresponding to the semiconductor layer 1b. Form. Thereby, variations in threshold voltage for each MISFET can be suppressed in the memory region 31 and the peripheral circuit region 32a, and the activation rate of the ion-implanted impurity can be increased in the peripheral circuit region 32b. .

(Embodiment 6)
FIG. 49 is a plan view showing an example of the semiconductor device (semiconductor chip) SM1a manufactured through the manufacturing steps according to the first to fourth embodiments or a combination thereof.

  The semiconductor device SM1a of the present embodiment has a memory region 31 in which a memory cell array such as an SRAM is formed, and a peripheral circuit region 32 in which a circuit (peripheral circuit) other than the memory is formed. The semiconductor device SM1a is mainly formed with a memory region 31. The semiconductor device SM1a is a so-called memory chip, and does not have an analog circuit region or a CPU region unlike the semiconductor device SM1 of the fifth embodiment. . The memory region 31 and the peripheral circuit region 32 are electrically connected as necessary via an internal wiring layer of the semiconductor device SM1a. In addition, a plurality of pad electrodes PD are formed along the two sides of the main surface of the semiconductor device SM1a at the periphery of the main surface (front surface) of the semiconductor device SM1a. Each pad electrode PD is electrically connected to the memory region 31 and the peripheral circuit region 32 through the internal wiring layer of the semiconductor device SM1a.

  In the present embodiment, when manufacturing the semiconductor device SM1a, any of the manufacturing techniques of the first to fourth embodiments or a combination thereof can be used.

  Similar to the fifth embodiment, also in the present embodiment, when the manufacturing technique of the third embodiment is applied in manufacturing the semiconductor device SM1a, all the regions (the memory region 31 and the peripheral region) in the semiconductor device SM1a are applied. The present invention is preferably applied to the MISFETs in all of the circuit regions 32, whereby the manufacturing process of the semiconductor device can be simplified.

  On the other hand, in manufacturing the semiconductor device SM1a, when the manufacturing techniques (single or combined) of the first, second, and fourth embodiments are applied, all the regions (the memory region 31 and the peripheral circuit region 32) in the semiconductor device SM1a are applied. This is not applied to all), but applied to the memory area 31, but not applied to the peripheral circuit area 32. 49 is a plan view, but in order to facilitate understanding, the memory region 31 to which the manufacturing technique (single or combination) of the first, second, and fourth embodiments is applied is hatched.

  In the fifth embodiment, in the peripheral circuit region 32, the peripheral circuit region 32a to which the manufacturing technique (single or combination) of the first, second, and fourth embodiments is applied and the peripheral circuit region 32b to which the manufacturing technology is not applied are mixed. On the other hand, the present embodiment is different in that the manufacturing technique (single or combination) of the first, second, and fourth embodiments is not applied to the peripheral circuit region 32.

  First, a case where the manufacturing technique of the first embodiment is applied when manufacturing the semiconductor device SM1a will be described. In this case, in the memory region 31, when the n-channel MISFET and the p-channel MISFET are formed, those corresponding to the diffusion preventing regions 10a and 10b are formed. On the other hand, in the peripheral circuit region 32, when the n-channel MISFET and the p-channel MISFET are formed, those corresponding to the diffusion preventing regions 10a and 10b are not formed.

  Next, a case where the manufacturing technique of the second embodiment is applied when manufacturing the semiconductor device SM1a will be described. In this case, in the memory region 31, a region corresponding to the semiconductor layer 1b (a semiconductor layer into which one or more of carbon, nitrogen, and fluorine is introduced) is formed by ion implantation, and an n-channel type is formed therein. A MISFET and a p-channel type MISFET are formed. On the other hand, in the peripheral circuit region 32, a region corresponding to the semiconductor layer 1b is not formed, and an n-channel MISFET and a p-channel type are formed in a substrate region (a substrate region into which carbon, nitrogen, or fluorine is not introduced). A MISFET is formed.

  Next, a description will be given of a case where the manufacturing technique of the fourth embodiment is applied in manufacturing the semiconductor device SM1a. In this case, in the memory region 31, for the channel dope ion implantation of the n channel type MISFET, the same kind of element as the channel dope ion implantation IM1a performed for the nMIS formation region 1A in the fourth embodiment is used, and the p channel is used. For the channel dope ion implantation of the type MISFET, the same element as the channel dope ion implantation IM1b performed for the pMIS formation region 1B in the fourth embodiment is used. On the other hand, in the peripheral circuit region 32, only boron (B) is used for channel doping ion implantation of the n-channel type MISFET, and only phosphorus (P) is used for channel doping ion implantation of the p-channel type MISFET. .

  As an example, a case where the semiconductor device SM1a is manufactured by applying the manufacturing technique of the first embodiment and the manufacturing technique of the fourth embodiment will be specifically described below with reference to FIGS. . In this case, the manufacturing technique according to the first embodiment and the manufacturing technique according to the fourth embodiment are applied to the memory area 31, but the manufacturing technique according to the first embodiment and the above-described embodiment are applied to the peripheral circuit area 32. The manufacturing technique of Form 4 is not applied.

  50 to 55 are fragmentary cross-sectional views of the semiconductor device SM1a according to the present embodiment during the manufacturing process.

  In the present embodiment, as in the first embodiment, first, a semiconductor substrate (semiconductor wafer) 1 is prepared. FIG. 50 shows a part of the memory region 31 and a part of the peripheral circuit region 32 in the semiconductor substrate 1.

  Of the memory region 31, FIG. 50 shows a memory nMIS formation region 1C, which is a region where an n-channel MISFET constituting the memory (memory cell) is formed, and a p-channel MISFET constituting the memory (memory cell). A memory pMIS formation region 1D, which is a region to be formed, is shown.

  In the peripheral circuit region 32, MISFETs having different breakdown voltages are formed. Therefore, in FIG. 50, a low breakdown voltage nMIS formation region 1L2 that is a region where a low breakdown voltage n-channel MISFET is formed in the peripheral circuit region 32 and a high breakdown voltage n-channel MISFET are formed in the peripheral circuit region 32. A high breakdown voltage nMIS formation region 1H, which is a region to be connected, is shown. That is, in the present embodiment, there is no region corresponding to the low breakdown voltage nMIS formation region 1L1.

  To manufacture the semiconductor device SM1a, first, as in the fifth embodiment, after preparing the semiconductor substrate (semiconductor wafer) 1, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1.

  Next, as in the fifth embodiment, after the insulating film 3 is formed on the surface of the semiconductor substrate 1, as shown in FIG. 51, the p-type well PW1 is formed in the memory nMIS formation region 1C and the memory pMIS is formed. An n-type well NW1 is formed in the region 1D, a p-type well PW3 is formed in the low breakdown voltage nMIS formation region 1L2, and a p-type well PW4 is formed in the high breakdown voltage nMIS formation region 1H.

  Next, channel dope ion implantation (ion for adjusting the threshold voltage of the MISFET formed therein) is performed in each of the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L2, and the high breakdown voltage nMIS formation region 1H. Implantation) IM1c, IM1d, IM1f, and IM1g are performed to form channel doped layers 4c, 4d, 4f, and 4g. In FIG. 51, channel dope ion implantation IM1c, IM1d, IM1f, IM1g is schematically shown by arrows.

  Channel doped ion implantation IM1c, IM1d, IM1f, IM1g and channel doped layers 4c, 4d, 4f, 4g formed thereby are the same as in the fifth embodiment.

  That is, in the channel dope ion implantation IM1c into the memory nMIS formation region 1C, the same kind of element (impurity element) as the channel dope ion implantation IM1a performed in the nMIS formation region 1A in the fourth embodiment is used. For this, one or both of indium (In) and gallium (Ga), or a combination of boron and (B) is used. In addition, in the channel dope ion implantation IM1d into the memory pMIS formation region 1D, the same kind of element (impurity element) as the channel dope ion implantation IM1b performed in the pMIS formation region 1B in the fourth embodiment is used. In this case, one or both of arsenic (As) and antimony (Sb), or a combination of phosphorus (P) and this is used. On the other hand, in the channel dope ion implantation IM1f and IM1g into the low breakdown voltage nMIS formation region 1L2 and the high breakdown voltage nMIS formation region 1H, unlike the fourth embodiment, only boron (B) is used. In addition, although not shown in FIG. 51, when channel-doped ions are implanted into a region for forming a p-channel MISFET in the peripheral circuit region 32, phosphorus (impurity element) is used as an implanted element (impurity element). Only P) is used.

  In addition, in the channel doping ion implantation IM1c, IM1d, IM1f, IM1g into each of the memory nMIS formation region 1C, the memory pMIS formation region 1D, the low breakdown voltage nMIS formation region 1L2, and the high breakdown voltage nMIS formation region 1H, A photoresist film (not shown) covering the region may be used as an ion implantation blocking mask.

  Next, after removing the insulating film 3 and cleaning the surface of the semiconductor substrate 1, as shown in FIG. 52, the gate insulating film 5c is formed on the semiconductor substrate 1 in the memory nMIS formation region 1C and the memory pMIS formation region 1D. After forming the gate insulating film 5d on the semiconductor substrate 1 in the low breakdown voltage nMIS formation region 1L2 and the gate insulating film 5e on the semiconductor substrate 1 in the high breakdown voltage nMIS formation region 1H, respectively, the gate electrodes GE3, GE4 GE6 and GE7 are formed. The relationship between the thickness of the gate insulating films 5c, 5d, and 5e and the withstand voltage is as described in the fifth embodiment. Further, the formation method and configuration of the gate insulating films 5c, 5d, and 5e having different thicknesses and the formation method and configuration of the gate electrodes GE3, GE4, GE6, and GE7 are the same as those in the fifth embodiment. Description is omitted. In FIG. 52 and FIGS. 53 to 55 described later, the channel dope layers 4c, 4d, 4f, and 4g are not shown in order to make the drawings easy to see.

  Next, as shown in FIG. 53, in the semiconductor substrate 1 (p-type well PW1) in the memory nMIS formation region 1C, the extension region 7a, the halo region 8a, and the diffusion prevention are performed by ion implantation as in the fifth embodiment. Region 10a is formed. Similarly to the fifth embodiment, the extension region 7b, the halo region 8b, and the diffusion prevention region 10b are formed by ion implantation in the semiconductor substrate 1 (n-type well NW1) in the memory pMIS formation region 1D. Similarly to the fifth embodiment, the extension region 7a and the halo region 8a are formed by ion implantation in the semiconductor substrate 1 (p-type well PW3) in the low breakdown voltage nMIS formation region 1L2 to correspond to the diffusion prevention region 10a. What is to be formed is not formed in the low breakdown voltage nMIS formation region 1L2. For simplification of the drawing, the halo regions 8a and 8b are not shown in FIG.

  Next, as shown in FIG. 54, sidewalls (sidewall insulating films) SW are formed on the sidewalls of the gate electrodes GE3, GE4, GE6, and GE7 as in the fifth embodiment.

Next, as in the fifth embodiment, ion implantation is performed on the semiconductor substrate 1 (p-type wells PW1, PW3, and PW4) in the memory nMIS formation region 1C, the low breakdown voltage nMIS formation region 1L2, and the high breakdown voltage nMIS formation region 1H. The n ⁺ type semiconductor region 11a (source, drain) is formed. Similarly to the fifth embodiment, ap ⁺ type semiconductor region 11b (source, drain) is formed by ion implantation in the semiconductor substrate 1 (n-type well NW1) in the memory pMIS formation region 1D.

  Next, similarly to the fifth embodiment, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed.

Thereafter, as shown in FIG. 55, similarly to the fifth embodiment, the metal silicide layers 12 are respectively formed on the surfaces of the gate electrodes GE3, GE4, GE6, GE7, the n ⁺ type semiconductor region 11a and the p ⁺ type semiconductor region 11b. Insulating films 21 and 22 are formed, contact holes 23 are formed in the insulating films 22 and 21, and plugs 24 are formed in the contact holes 23. As in FIG. 47, FIG. 55 also omits the illustration of the insulating film 21 and includes the insulating film 21 in the insulating film 22 for simplification of the drawing. Then, similarly to the fifth embodiment, a stopper insulating film 25 and an insulating film 26 are formed in order on the insulating film 22 in which the plug 24 is embedded, and a wiring groove 27 is formed in the insulating film 26 and the stopper insulating film 25. Then, the wiring M 1 is formed in the wiring groove 27. Similarly to FIG. 47, FIG. 55 also omits the illustration of the stopper insulating film 25 and includes the stopper insulating film 25 in the insulating film 26 in order to simplify the drawing.

  50 to 55, the case where the manufacturing technique of the first embodiment is applied in manufacturing the semiconductor device SM1a has been described. However, the manufacturing of the second embodiment is described in manufacturing the semiconductor device SM1a. Technology can also be applied. In this case, in the memory region 31, the semiconductor region 1b1 corresponding to the semiconductor layer 1b is formed by ion implantation, and an n-channel MISFET and a p-channel MISFET are formed there. On the other hand, in the peripheral circuit region 32, the semiconductor region 1b1 corresponding to the semiconductor layer 1b is not formed, and an n-channel MISFET and a p-channel type are formed in a semiconductor substrate region into which any of carbon, nitrogen, and fluorine is not introduced. A MISFET may be formed.

  In the fifth embodiment, when the manufacturing technology of the first, second, and fourth embodiments is applied in manufacturing the semiconductor device SM1, the memory region 31 and the peripheral circuit region 32a are the same as the first embodiment. The manufacturing techniques 2 and 4 are applied, and the manufacturing techniques of the first, second, and fourth embodiments are not applied to the peripheral circuit region 32b. On the other hand, in the present embodiment, when the manufacturing technology of the first, second, and fourth embodiments is applied to manufacture the semiconductor device SM1a, the memory region 31 has the first, second, and second embodiments. The manufacturing technique of the first, second, and fourth embodiments is not applied to the entire peripheral circuit region 32. The reason is as follows.

  In the fifth embodiment, in the peripheral circuit region 32, in the region where the MISFET that is miniaturized (short gate length) comparable to the MISFET in the memory region 31 is formed (that is, the peripheral circuit region 32a), the memory By applying the manufacturing techniques of the first, second, and fourth embodiments as in the region 31, variations in threshold voltage for each MISFET are suppressed.

  However, as in the semiconductor device SM1a of the present embodiment, a MISFET having a gate length longer than the gate length of the MISFET in the memory region 31 is formed in the entire peripheral circuit region 32, or In the MISFET formed in the circuit region 32, there is a case where it is not necessary to pay much attention to variations in threshold voltage. In such a case, as in the present embodiment, the manufacturing technique of the first, second, and fourth embodiments is applied to the memory area 31, while the above-described embodiment is applied to the entire peripheral circuit area 32. It is also possible not to apply the manufacturing techniques of 1, 2, and 4. Thereby, in the memory region 31, variation in threshold voltage for each MISFET can be suppressed, and in the peripheral circuit region 32, the activation rate of the ion-implanted impurity can be increased.

  According to the experiment by the present inventor, in the fifth embodiment and the sixth embodiment, the variation in the threshold voltage of the MISFET constituting the SRAM memory cell in the memory region 31 can be suppressed. The SRAM lower limit voltage (the minimum voltage at which all memory cells of the SRAM in the memory area 31 can be rewritten) can be improved by about 20% (down by about 20%).

  As described above, in the fifth embodiment and the sixth embodiment, the semiconductor devices SM1 and SM1a having the memory region 31 where the memory is formed and the peripheral circuit region 32 where the memory other than the memory is formed are manufactured. In the memory region 31, the manufacturing techniques of the first, second, and fourth embodiments (single or combined) are applied when forming the MISFET. On the other hand, a MISFET is formed in at least a part of the peripheral circuit region 32 (only the peripheral circuit region 32b in the peripheral circuit region 32 in the fifth embodiment and the entire region of the peripheral circuit region 32 in the sixth embodiment). However, the manufacturing techniques of the first, second, and fourth embodiments (single or combined) are not applied. As described above, the areas to which the first, second, and fourth embodiments (single or combined) are applied can be selectively used according to the characteristics of the circuit areas of the semiconductor devices SM1 and SM1a.

  Specifically, when the manufacturing technique of the first embodiment is applied, in the memory region 31, when forming the MISFET, one or more of carbon, nitrogen, and fluorine are ion-implanted (that is, the ion Implantation IM4a, IM4b) is performed to form diffusion prevention regions 10a, 10b. On the other hand, in at least a part of the peripheral circuit region 32 (only the peripheral circuit region 32b in the fifth embodiment, and the entire peripheral circuit region 32 in the sixth embodiment), when the MISFET is formed, the ion implantation IM4a , IM4b is not performed.

  When the manufacturing technique of the second embodiment is applied, in the memory region 31, the MISFET is formed in a semiconductor layer (semiconductor region 1b1) into which one or more of carbon, nitrogen, and fluorine are introduced. On the other hand, in at least a part of the peripheral circuit region 32 (only the peripheral circuit region 32b in the fifth embodiment and the entire peripheral circuit region 32 in the sixth embodiment), the MISFET is made of carbon, nitrogen, or fluorine. The semiconductor layer (semiconductor region 1b1) into which one or more kinds are introduced is formed in a semiconductor substrate in a region (that is, a semiconductor substrate region into which any of carbon, nitrogen, and fluorine is not introduced or doped).

  In addition, when the manufacturing technique of the fourth embodiment is applied, in the memory region 31, when performing ion implantation for adjusting the threshold value of the MISFET, a region of indium or gallium is implanted into the region into which the p-type impurity is ion implanted. One or both of them, or boron added thereto is ion-implanted, and n-type impurity ions are implanted into one or both of arsenic and antimony, or phosphorus added thereto. On the other hand, at least a part of the peripheral circuit region 32 (only the peripheral circuit region 32b in the fifth embodiment and the entire peripheral circuit region 32 in the sixth embodiment) is subjected to ion implantation for adjusting the threshold of the MISFET. When performing, only boron is ion-implanted into a region where p-type impurities are ion-implanted, and only phosphorus is ion-implanted into a region where n-type impurities are ion-implanted.

  In the fifth embodiment and the sixth embodiment, the case where the SRAM memory cell array is formed in the memory region 31 has been described. However, the memory formed in the memory region 31 may be other than the SRAM, and other memory such as a flash memory may be used. The present invention can also be applied when a type of memory cell array is formed in the memory region 31.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a manufacturing technique of a semiconductor device having a MISFET.

It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36; FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38; It is a top view of the semiconductor device which is other embodiments of the present invention. FIG. 41 is an essential part cross sectional view of the semiconductor device of FIG. 40 during a manufacturing step. FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41; FIG. 43 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42; FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45; FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is a top view of the semiconductor device which is other embodiments of the present invention. FIG. 50 is an essential part cross sectional view of the semiconductor device of FIG. 49 during a manufacturing step; FIG. 51 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 50; FIG. 52 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 51; FIG. 53 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 52; FIG. 54 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 53; FIG. 55 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 54;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Semiconductor substrate 1b Semiconductor layer 1b1 Semiconductor region 1A nMIS formation region 1B pMIS formation region 1C Memory nMIS formation region 1D Memory pMIS formation region 1H High breakdown voltage nMIS formation region 1L1, 1L2 Low breakdown voltage nMIS formation region 2 Element isolation region 3 Insulating film 4a, 4b, 4c, 4d, 4e, 4f, 4g Channel dope layer 5 Insulating film 5a, 5b, 5c, 5d, 5e Gate insulating film 6, 6a, 6b Silicon film 7a, 7b Extension region 8a, 8b Hello region 10a, 10b Diffusion prevention region 11a n ⁺ type semiconductor region 11b p ⁺ type semiconductor region 12 Metal silicide layers 21, 22 Insulating film 23 Contact hole 24 Plug 24a Barrier conductor film 24b Main conductor film 25 Stopper insulating film 26 Insulating film 27 Wiring groove 28 Barrier Conductor film 29 Main conductor film 31 Memory region 32, 32a, 32b Peripheral circuit region GE1, GE2, GE3, GE4, GE5, GE6, GE7 Gate electrodes IM1a, IM1b, IM1c, IM1d, IM1e, IM1f, IM1g Channel doping ion implantation (for threshold adjustment) Ion implantation)
IM2a, IM2b, IM3a, IM3b, IM4a, IM4b, IM5a, IM5b Ion implantation M1 wiring NW, NW1 n-type well PD pad electrodes PW, PW1, PW2, PW3, PW4 p-type well Qn n-channel type MISFET
Qp p-channel MISFET
SM1, SM1a Semiconductor device SUB1 Semiconductor substrate SW Side wall

Claims (24)

A method of manufacturing a semiconductor device having a first MISFET of a first conductivity type,
(A) a step of preparing a semiconductor substrate;
(B) performing ion implantation for adjusting the threshold value of the first MISFET in the semiconductor substrate;
(C) forming a first insulating film for the gate insulating film of the first MISFET on the main surface of the semiconductor substrate;
(D) forming a first gate electrode of the first MISFET on the first insulating film;
(E) After the step (d), ion implantation is performed on the semiconductor substrate using the first gate electrode as a mask to form a first conductive type first semiconductor region in the semiconductor substrate;
(F) After the step (d), a step of ion-implanting a first element into the semiconductor substrate;
(G) a step of forming a sidewall insulating film on the sidewall of the first gate electrode after the step (e) and the step (f);
(H) Ion implantation is performed on the semiconductor substrate using the first gate electrode and the sidewall insulating film as a mask, and a second semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region is formed on the semiconductor substrate. Forming step,
Have
The first and second semiconductor regions function as a semiconductor region for the source or drain of the first MISFET,
The first element ion-implanted in the step (f) is composed of one or more of carbon, nitrogen, and fluorine,
At least a part of the region into which the first element is introduced in the step (f) is located between the channel region of the first MISFET and the first semiconductor region. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), an impurity is introduced into the channel region of the first MISFET. The method of manufacturing a semiconductor device according to claim 2.
In the step (f),
A method of manufacturing a semiconductor device, wherein the first element is introduced into the semiconductor substrate by oblique ion implantation. In the manufacturing method of the semiconductor device according to claim 3,
In the step (f),
A method of manufacturing a semiconductor device, wherein the first element is ion-implanted into the semiconductor substrate so that the region into which the first element is introduced surrounds the first semiconductor region. In the manufacturing method of the semiconductor device according to claim 4,
After the step (d) and before the step (g),
(E1) performing ion implantation using the first gate electrode as a mask to form a second conductivity type first halo region that encloses the first semiconductor region;
Further comprising
At least a part of the region into which the first element is introduced in the step (f) is located between the channel region of the first MISFET and the first halo region. In the manufacturing method of the semiconductor device according to claim 5,
In the step (f),
A method of manufacturing a semiconductor device, wherein the first element is ion-implanted into the semiconductor substrate so that the region into which the first element is introduced surrounds the first halo region. The method of manufacturing a semiconductor device according to claim 6.
An element to be ion-implanted in the step (b) is one or both of indium and gallium, or boron added thereto. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a memory region in which a memory is formed and a peripheral circuit region in which a circuit other than the memory is formed,
In the memory region, when the MISFET is formed, the step (f) is performed.
A method of manufacturing a semiconductor device, wherein the step (f) is not performed when forming a MISFET in at least a part of the peripheral circuit region. A method of manufacturing a semiconductor device having a first MISFET,
(A) a step of preparing a semiconductor substrate having an upper portion of a semiconductor layer into which one or more of carbon, nitrogen, and fluorine are introduced;
(B) performing ion implantation for adjusting the threshold value of the first MISFET in the semiconductor layer;
(C) forming a first insulating film for a gate insulating film of the first MISFET on the main surface of the semiconductor layer;
(D) forming a first gate electrode of the first MISFET on the first insulating film;
(E) forming a semiconductor region for the source or drain of the first MISFET in the semiconductor layer;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 9,
The method for manufacturing a semiconductor device, wherein the semiconductor layer is formed by epitaxial growth or ion implantation. The method of manufacturing a semiconductor device according to claim 10.
The method for manufacturing a semiconductor device, wherein the semiconductor layer is made of single crystal silicon into which one or more of carbon, nitrogen, and fluorine are introduced. The method of manufacturing a semiconductor device according to claim 11.
In the step (b), an impurity is introduced into the channel region of the first MISFET. In the manufacturing method of the semiconductor device according to claim 12,
An element to be ion-implanted in the step (b) is one or both of indium and gallium, or boron added thereto. In the manufacturing method of the semiconductor device according to claim 12,
The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a memory region in which a memory is formed and a peripheral circuit region in which a circuit other than the memory is formed,
In the memory region, a MISFET is formed in the semiconductor layer,
In at least a part of the peripheral circuit region, a MISFET is formed on the semiconductor substrate in a region where the semiconductor layer is not formed. A method of manufacturing a semiconductor device having a first MISFET,
(A) a step of preparing a semiconductor substrate;
(B) after the step (a), forming a first insulating film for the gate insulating film of the first MISFET on the main surface of the semiconductor substrate;
(C) a step of forming a first conductor layer on the first insulating film after the step (b);
(D) a step of performing ion implantation for adjusting a threshold value of the first MISFET in the semiconductor substrate after the step (c);
(E) after the step (d), forming a second conductor layer on the first conductor layer;
(F) patterning the second conductor layer and the first conductor layer to form a first gate electrode of the first MISFET;
(G) After the step (f), forming a semiconductor region for the source or drain of the first MISFET on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 15,
The method for manufacturing a semiconductor device, wherein the first conductor layer and the second conductor layer are made of polycrystalline silicon. In the manufacturing method of the semiconductor device according to claim 16,
In the step (b), the first insulating film is formed by a thermal oxidation method. The method of manufacturing a semiconductor device according to claim 17.
The method of manufacturing a semiconductor device, wherein the thickness of the first conductor layer formed in the step (c) is thinner than the thickness of the second conductor layer formed in the step (e). The method of manufacturing a semiconductor device according to claim 18.
In the step (d), an impurity is introduced into the channel region of the first MISFET. In the manufacturing method of the semiconductor device according to claim 19,
An element to be ion-implanted in the step (d) is one or both of indium and gallium, or boron added thereto. A method of manufacturing a semiconductor device having a first MISFET of a first conductivity type,
(A) a step of preparing a semiconductor substrate;
(B) performing ion implantation for adjusting the threshold value of the first MISFET in the semiconductor substrate;
(C) forming a first insulating film for the gate insulating film of the first MISFET on the main surface of the semiconductor substrate;
(D) forming a first gate electrode of the first MISFET on the first insulating film;
(E) forming a semiconductor region for the source or drain of the first MISFET on the semiconductor substrate;
Have
An element to be ion-implanted in the step (b) is one or both of indium and gallium, or boron added thereto. In the manufacturing method of the semiconductor device according to claim 21,
In the step (b), one or both of indium and gallium, or a material obtained by adding boron to the channel region of the first MISFET is introduced. The method of manufacturing a semiconductor device according to claim 22,
The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having the first MISFET and a second MISFET of a second conductivity type,
In the step (c), a first insulating film for a gate insulating film of the first MISFET and the second MISFET is formed on a main surface of the semiconductor substrate,
Furthermore,
(B1) performing ion implantation for adjusting the threshold value of the second MISFET in the semiconductor substrate;
(D1) forming a second gate electrode of the second MISFET on the first insulating film;
(E1) forming a semiconductor region for the source or drain of the second MISFET on the semiconductor substrate;
Have
The element for ion implantation in the step (b1) is one or both of arsenic and antimony, or a material obtained by adding phosphorus thereto. 24. The method of manufacturing a semiconductor device according to claim 23.
The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a memory region in which a memory is formed and a peripheral circuit region in which a circuit other than the memory is formed,
In the memory region, when performing ion implantation for adjusting the threshold value of the MISFET, one or both of indium and gallium, or boron added thereto is implanted into the region into which p-type impurities are ion-implanted. In the region where the n-type impurity is ion-implanted, one or both of arsenic and antimony, or phosphorus added thereto is ion-implanted,
In at least a part of the peripheral circuit region, when ion implantation for adjusting the threshold value of the MISFET is performed, only boron is ion-implanted and n-type impurity is ion-implanted into the region into which p-type impurities are ion-implanted. A method for manufacturing a semiconductor device, wherein only phosphorus is ion-implanted into a region.

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