CN102891076A - Structure of MOS (metal oxide semiconductor) transistor and formation method thereof - Google Patents
Structure of MOS (metal oxide semiconductor) transistor and formation method thereof Download PDFInfo
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- CN102891076A CN102891076A CN2011102077269A CN201110207726A CN102891076A CN 102891076 A CN102891076 A CN 102891076A CN 2011102077269 A CN2011102077269 A CN 2011102077269A CN 201110207726 A CN201110207726 A CN 201110207726A CN 102891076 A CN102891076 A CN 102891076A
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Abstract
The embodiment of the invention provides an MOS (metal oxide semiconductor) transistor. The MOS transistor comprises a semiconductor substrate, a gate insulation layer positioned on the surface of the semiconductor substrate, a gate electrode layer positioned on the surface of the gate insulation layer, side walls positioned on the two sides of the gate insulation layer and the gate electrode layer as well as the surface of the semiconductor substrate, a source/a drain positioned on the two sides of the gate insulation layer and the gate electrode layer and in the semiconductor substrate, and a doped layer positioned at the bottom of the gate insulation layer and in the semiconductor substrate. Correspondingly, the embodiment of the invention further provides a formation method of the MOS transistor. The MOS transistor provided by the embodiment of the invention has the advantages of high migration rate of a current carrier and good stability of a gate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to structure of a kind of MOS transistor and forming method thereof.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach higher arithmetic speed, larger memory data output and more function, and semiconductor device is towards higher component density, higher integrated level future development.
Please refer to Fig. 1, MOS transistor in the prior art comprises:
Be positioned at the gate insulation layer 107 on described Semiconductor substrate 100 surfaces; And be positioned at the gate electrode layer 109 on described gate insulation layer 107 surfaces; Be positioned at described gate insulation layer 107 and gate electrode layer 109 both sides and be positioned at the side wall 111 on described Semiconductor substrate 100 surfaces;
Be positioned at described gate insulation layer 107 and gate electrode layer 109 both sides and be positioned at the source electrode 106 of described Semiconductor substrate 100 and drain 105;
Along with MOS transistor towards higher integrated level future development, the grid length of MOS transistor reduces gradually, be that gate insulation layer 107 and gate electrode layer 109 diminish gradually along the size of Semiconductor substrate 100 surface direction among Fig. 1, the mobility of the charge carrier of the channel region of the MOS transistor of prior art is lower.The more patent application document that please refer to United States Patent (USP) " US20080043588 " about formation method and the structure of MOS transistor.
Summary of the invention
The problem that the present invention solves provides a kind of structure and forming method thereof of MOS transistor of mobility of the charge carrier that increases channel region.
For addressing the above problem, the invention provides a kind of formation method of MOS transistor, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with gate insulation layer, be positioned at the pseudo-gate electrode layer of described gate electrode insulation surface, be positioned at described gate insulation layer and pseudo-gate electrode layer both sides semiconductor substrate surface side wall and be positioned at described gate insulation layer and the source of the Semiconductor substrate of pseudo-gate electrode layer both sides/drain electrode;
Form the dielectric layer that covers described Semiconductor substrate and described side wall, the flush of described dielectric layer and described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer, form the opening that exposes described gate insulation layer;
Form doped layer in the Semiconductor substrate under described opening;
In described opening, form the gate electrode layer that is positioned at described gate electrode insulation surface;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Alternatively, the formation technique of described doped layer is ion implantation technology; The ion that injects in the described ion implantation technology comprises N
+, C
+, F
+In one or more combinations.
Alternatively, the parameter area of described ion implantation technology is: energy is 5kev～30kev; Dosage is 1E13/cm
2～1E15/cm
2
Alternatively, described ion implantation technology is magnetic plasma sputter injection technology.
Alternatively, the normal direction of the injection direction of the ion in the described ion implantation technology and described semiconductor substrate surface is 0～15 ° of angle.
Alternatively, comprise N in the described gate insulation layer
+, C
+, F
+In one or more combinations.
Alternatively, the formation technique of described gate insulation layer is situ steam oxide deposition technique.
A kind of formation method of MOS transistor comprises:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with pseudo-gate insulation layer, be positioned at the pseudo-gate electrode layer of described pseudo-gate electrode insulation surface, be positioned at described pseudo-gate insulation layer and pseudo-gate electrode layer both sides semiconductor substrate surface side wall and be positioned at described pseudo-gate insulation layer and the source of the Semiconductor substrate of pseudo-gate electrode layer both sides/drain electrode;
Form the dielectric layer that covers described Semiconductor substrate and described side wall, the flush of described dielectric layer and described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer and pseudo-gate insulation layer, form the opening that exposes described Semiconductor substrate;
Form doped layer in the Semiconductor substrate under described opening;
In described opening, form the gate insulation layer that is positioned at described semiconductor substrate surface, the gate electrode layer that is positioned at described gate electrode insulation surface;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Alternatively, the formation technique of described doped layer is ion implantation technology; The ion that injects in the described ion implantation technology comprises N
+, C
+, F
+In one or more combinations.
Alternatively, the parameter area of described ion implantation technology is: energy is 5kev～30kev; Dosage is 1E13/cm
2～1E15/cm
2
Alternatively, described ion implantation technology is magnetic plasma sputter injection technology; The energy of described magnetic plasma sputter injection technology is 0.5kev～4kev, and dosage is 1E13/cm
2～1E15/cm
2
Alternatively, the normal direction of the injection direction of the ion in the described ion implantation technology and described semiconductor substrate surface is 0～15 ° of angle.
Alternatively, the formation technique of described gate insulation layer is situ steam oxide deposition technique.
A kind of structure of MOS transistor comprises:
Semiconductor substrate; Be positioned at the gate insulation layer of described semiconductor substrate surface; Be positioned at the gate electrode layer of described gate electrode insulation surface; Be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the source of described Semiconductor substrate/drain electrode;
Be positioned at the doped layer of the Semiconductor substrate of described gate insulation layer bottom.
Alternatively, the ion that comprises in the described doped layer is N
+, C
+, F
+In one or more combinations.
Alternatively, the ion concentration of described doped layer is 1E17/cm
3～1E21/cm
3
Alternatively, comprise N in the described gate insulation layer
+, C
+, F
+In one or more combinations.
Compared with prior art, the present invention has the following advantages:
Embodiments of the invention are to form doped layer in the channel region in the Semiconductor substrate of gate insulation layer bottom, establishment the diffusion of impurity in the channel region, improved the mobility of charge carrier.
Further, the embodiment of the invention adopts ion implantation technology to inject N in gate electrode insulation surface
+, C
+, F
+In one or more be combined to and form doped layer in the Semiconductor substrate, the shape of the gate insulation layer of described ion implantation technology in the middle of edge thickness is higher than is originally revised, and has avoided beak effect; And, also comprise N in the described gate insulation layer
+, C
+, F
+In one or more combinations, effectively reduce the leakage current of grid, the good stability of grid.
Description of drawings
Fig. 1 is the cross-sectional view of the MOS transistor of prior art;
Fig. 2 is the schematic flow sheet of formation method of the MOS transistor of first embodiment of the invention;
Fig. 3～Fig. 6 is the cross-sectional view of forming process of the MOS transistor of first embodiment of the invention;
Fig. 7 is the schematic flow sheet of formation method of the MOS transistor of second embodiment of the invention;
Fig. 8～Figure 10 is the cross-sectional view of forming process of the MOS transistor of second embodiment of the invention.
Embodiment
By background technology as can be known, along with existing MOS transistor grid length continue dwindle, the carrier mobility of transistorized channel region reduces.
The inventor of the embodiment of the invention finds through after studying, along with transistor gate length continue dwindle, oxidation-enhanced diffusion (Oxidation-Enhanced Diffusion, OED) become the key factor that affects the boron of channel region ion and phosphonium ion diffusion, because OED effect, caused Transient enhancement diffusion (Transistent-Enhanced Diffusion, TED), and the transient state enhancement effect not only causes transistorized short-channel effect, and has affected the carrier mobility of transistorized channel region.
The inventor of the embodiment of the invention finds after further research, the doping ion forms doped layer in channel region, the impurity that can suppress channel region is the diffusion of boron ion and phosphonium ion for example, has suppressed the transient state enhancement effect, can improve the carrier mobility of channel region.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and the degree of depth.
The first embodiment
Please refer to Fig. 2, the formation method of the MOS transistor of first embodiment of the invention comprises:
Step S201 provides Semiconductor substrate; Described semiconductor substrate surface is formed with gate insulation layer; Be positioned at the pseudo-gate electrode layer of described gate electrode insulation surface; Be positioned at described gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source of described Semiconductor substrate/drain electrode;
Step S203 forms the dielectric layer that covers described Semiconductor substrate and described side wall, the flush of described dielectric layer and described pseudo-gate electrode layer;
Step S205 removes described pseudo-gate electrode layer, forms the opening that exposes described gate insulation layer;
Step S207 forms doped layer in the Semiconductor substrate under described opening;
Step S209 forms the gate electrode layer that is positioned at described gate electrode insulation surface in described opening; Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Execution in step S201 please refer to Fig. 3, and Semiconductor substrate 300 is provided; Described Semiconductor substrate 300 surfaces are formed with gate insulation layer 307; Be positioned at the pseudo-gate electrode layer 309 on described gate insulation layer 307 surfaces; Be positioned at described gate insulation layer 307 and pseudo-gate electrode layer 309 both sides and be positioned at the side wall 311 on described Semiconductor substrate 300 surfaces; And be positioned at described gate insulation layer 307 and pseudo-gate electrode layer 309 both sides and be positioned at the source electrode 306 of described Semiconductor substrate 300 and drain 305.
The platform that provides of follow-up formation MOS transistor is provided described Semiconductor substrate 300.The material of described Semiconductor substrate 300 can be silicon substrate or silicon-on-insulator substrate (SOI substrate).
Described gate insulation layer 307 is used for the gate electrode layer of source electrode 306 in the isolation of semiconductor substrate 300 and follow-up formation and drains 305 and the gate electrode layer of follow-up formation, and the material of described gate insulation layer 307 is silica or high K dielectric.
In an embodiment of the present invention, the formation technique of described gate insulation layer 307 is situ steam oxide deposition technique.
Described pseudo-gate electrode layer 309 is used to formation side wall 311 to support.Consider that described pseudo-gate electrode layer 309 rear extended meetings are removed, for not destroying and described pseudo-gate electrode layer 309 contacted gate insulation layer 307 and side walls 311, the material of described pseudo-gate electrode layer 309 is different from the material of described gate insulation layer 307 and described side wall 311.The inventor of the embodiment of the invention finds after through research, when the etching selection ratio between described pseudo-gate electrode layer 309 and the gate insulation layer 307 greater than 1 the time, can not destroy described gate insulation layer 307 and described side wall 311 during the described pseudo-gate electrode layer 309 of follow-up removal.In an embodiment of the present invention, the material of described pseudo-gate electrode layer 309 is polysilicon.
In addition, the material of described side wall 311 is silicon nitride; Described source electrode 306 and drain electrode 305 adopt the mode of Implantation to form.Also be formed with fleet plough groove isolation structure 303 in the described Semiconductor substrate, the active area that described fleet plough groove isolation structure 303 is used in the isolation of semiconductor substrate 300.
Execution in step S203 please continue with reference to figure 3, forms the dielectric layer 313 that covers described Semiconductor substrate 300 and described side wall 311, the flush of described dielectric layer 313 and described pseudo-gate electrode layer 309.
Described dielectric layer 313 is for the protection of source electrode 306, drain electrode 305 and side wall 311, so that described source electrode 306, drain electrode 305 and side wall 311 can be not destroyed in subsequent process steps.Consider that dielectric layer 313 rear extended meetings are removed, in order not destroy and described dielectric layer 313 contacted side wall 311 and Semiconductor substrate 300 when the follow-up removal, the material of described dielectric layer 313 is different from the material of described side wall 311, Semiconductor substrate 300.In an embodiment of the present invention, choose between described dielectric layer 313 and the side wall 311, the etching selection ratio between described dielectric layer 313 and the described Semiconductor substrate 300 is greater than 1 material, silica for example is as the material of dielectric layer 313.
The formation technique of described dielectric layer 313 is depositing operation, for example physics or chemical vapour deposition (CVD).Because the technique of the described dielectric layer 313 of deposition is well known to those skilled in the art, does not repeat them here.
Execution in step S205 please refer to Fig. 4, removes described pseudo-gate electrode layer, forms the opening 315 that exposes described gate insulation layer 307.
The technique of removing described pseudo-gate electrode layer is dry etching, because the technique that adopts dry etching to remove described pseudo-gate electrode layer is known by those skilled in the art, does not repeat them here.
Described opening 315 is used for follow-up Implantation window as forming doped layer.Described opening 315 exposes described gate insulation layer 307.
Execution in step S207 please refer to Fig. 5, the Semiconductor substrate 300 interior formation doped layers 317 under described opening 315.
The impurity that described doped layer 317 is used for suppressing channel region is the diffusion of boron ion and phosphonium ion for example, has suppressed the transient state enhancement effect, can improve the carrier mobility of channel region.
The inventor of the embodiment of the invention is through discovery after studying, and N mixes in channel region
+, C
+, F
+In one or more combinations, form and to comprise N
+, C
+, F
+In the doped layer 317 of one or more combinations, can effectively suppress the diffusion of the impurity of channel region.In an embodiment of the present invention, comprise N in the described doped layer 317
+Ion.
The formation technique of described doped layer 317 is Implantation.In the ion implantation technology process, when the direction of described Implantation and Semiconductor substrate 300 normal to a surface directions were 0～15 degree angle, the position of the doped layer 317 of formation was better, the diffusion of impurity that can the establishment channel region.
To comprise N in the described doped layer 317
+Ion is that example is carried out exemplary illustrated.In an embodiment of the present invention, adopt the energy of 5kev～30kev, the Semiconductor substrate 300 interior implantation dosages under described opening 315 are 1E13/cm
2～1E15/cm
2N
+Ion, because the ion that described ion implantation technology is injected is darker, most described N
+Ion rests on after by gate insulation layer 307 in the Semiconductor substrate 300 under the described gate insulation layer 307, is 1E17/cm in described Semiconductor substrate 300 interior formation concentration
3～1E21/cm
3Doped layer 317.When the ion concentration of described doped layer 317 is 1E18/cm
3～1E20/cm
3The time, described doped layer 317 can effectively suppress the diffusion of the impurity of channel region, improves the mobility of charge carrier.
In addition, in an embodiment of the present invention, also has the N of fraction
+Rested in the gate insulation layer 307, effectively reduced the drain electrode of grid, improved the stability of grid.
Need to prove, if need most N
+Rest in the gate insulation layer 307, reach and improve the electric leakage of the grid utmost point, improve the purpose of grid stability, can adopt the more shallow magnetic plasma sputter injection technology of the Implantation degree of depth.Particularly, the inventor is by the energy of the described Implantation of adjusting and the dosage of ion, so that the concentration of the ion in the concentration of the ion in the doped layer 317 and/or the gate insulation layer 307 reaches desired value, suppress the diffusion of the impurity of channel region with realization, improve the purpose of the mobility of charge carrier, and the drain electrode that reduces grid, the purpose of the stability of raising grid.
Need to prove in addition, comprise N in the described gate insulation layer
+, C
+, F
+In one or more combinations, all can play the drain electrode that reduces grid, improve the effect of the stability of grid.
In addition, the inventor also finds, along with the size of grid becomes more next little, in the technique that forms gate insulation layer 307, easily forms the structure (beak effect) that edge thickness is higher than interior thickness, and this kind structure is unfavorable for the stability of grid.And in an embodiment of the present invention, in the position of described opening 315 towards described Semiconductor substrate 300 interior injection N
+, C
+, F
+In one or more when being combined to form doped layer 317, described N
+, C
+, F
+In one or more combinations the defective of described gate insulation layer 307 is revised the uniformity so that the thickness of described gate insulation layer 307 becomes has reduced beak effect, so that the stability of grid strengthens.
Execution in step S209 please refer to Fig. 6, forms the gate electrode layer 319 that is positioned at described gate insulation layer 307 surfaces in described opening; Remove described dielectric layer, expose described Semiconductor substrate 300 and side wall 311.
Described gate electrode layer 319 is used to form grid.When the material of described gate insulation layer 307 was silica, the material of described gate electrode layer 319 was polysilicon; When the material of described gate insulation layer 307 was high K dielectric, the material of described gate electrode layer 319 was metal.
The formation technique of described gate electrode layer 319 is depositing operation, for example physics or chemical deposition.The formation technique of described gate electrode layer 319 is well known to those skilled in the art, does not repeat them here.
The technique of removing described dielectric layer is etching technics, for example dry etching.After removing described dielectric layer, expose described Semiconductor substrate 300 and side wall 311.
Please continue with reference to figure 6, the structure of the MOS transistor that the formation method of employing first embodiment of the invention forms comprises:
Be positioned at the doped layer 317 of the Semiconductor substrate 300 of described gate insulation layer 307 bottoms.
Wherein, the ion that comprises in the described doped layer 317 is N
+, C
+, F
+In one or more combinations; Ion concentration in the described doped layer 317 is 1E17/cm
3～1E21/cm
3Comprise N in the described gate insulation layer 307
+, C
+, F
+In one or more combinations.
It is to be formed with in the channel region to comprise N that the MOS transistor that forms in the first embodiment of the present invention, the semiconductor of described gate insulation layer 307 bottoms sink to the bottom in 300
+, C
+, F
+In the doped layer 317 of one or more combinations, establishment the diffusion of impurity in the channel region, improved the mobility of charge carrier; And, owing to being to inject N on gate insulation layer 307 surfaces
+, C
+, F
+In one or more combinations, the shape of the described ion implantation technology gate insulation layer 307 in the middle of edge thickness is higher than is originally revised, and has avoided beak effect; And also comprise N in the described gate insulation layer 307
+, C
+, F
+In one or more combinations, effectively reduce the leakage current of grid, the good stability of grid.
The second embodiment
Please refer to Fig. 7, the formation method of the MOS transistor of second embodiment of the invention comprises:
Step S401 provides Semiconductor substrate; Described semiconductor substrate surface is formed with pseudo-gate insulation layer; Be positioned at the pseudo-gate electrode layer of described pseudo-gate electrode insulation surface; Be positioned at described pseudo-gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described pseudo-gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source of described Semiconductor substrate/drain electrode;
Step S403 forms the dielectric layer that covers described Semiconductor substrate and described side wall, the flush of described dielectric layer and described pseudo-gate electrode layer;
Step S405 removes described pseudo-gate electrode layer and pseudo-gate insulation layer, forms the opening that exposes described Semiconductor substrate;
Step S407 forms doped layer in the Semiconductor substrate under described opening;
Step S409 forms the gate insulation layer that is positioned at described semiconductor substrate surface, the gate electrode layer that is positioned at described gate electrode insulation surface in described opening; Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Execution in step S401 please refer to Fig. 8, and the Semiconductor substrate 500 with fleet plough groove isolation structure 503 is provided; Described Semiconductor substrate 500 surfaces are formed with pseudo-gate insulation layer 507; Be positioned at the pseudo-gate electrode layer 509 on described pseudo-gate insulation layer 507 surfaces; Be positioned at described pseudo-gate insulation layer 507 and pseudo-gate electrode layer 509 both sides and be positioned at the side wall 511 of described semiconductor substrate surface 500; And be positioned at described pseudo-gate insulation layer 507 and pseudo-gate electrode layer 509 both sides and be positioned at the source electrode 506 of described Semiconductor substrate 500 and drain 505.
Execution in step S403 please continue with reference to figure 8, forms the dielectric layer 513 that covers described Semiconductor substrate 500 and described side wall 511, the flush of described dielectric layer 513 and described pseudo-gate electrode layer 509.
The material of described pseudo-gate insulation layer 507 and pseudo-gate electrode layer 509 is different from the material of side wall 511 and Semiconductor substrate 500.In the second embodiment of the present invention, the material of described pseudo-gate insulation layer 507 is silica, and the material of described pseudo-gate electrode layer 509 is polysilicon.
More formation methods about step S401 and step S403 please refer to step S201 and the step S203 of first embodiment of the invention.
Execution in step S405 please refer to Fig. 9, removes described pseudo-gate electrode layer and pseudo-gate insulation layer, forms the opening 515 that exposes described Semiconductor substrate 500.
Remove described pseudo-gate electrode layer and pseudo-gate insulation layer technique is dry etching; Described opening 515 is used for follow-up Implantation window as forming doped layer, and described opening 515 exposes described Semiconductor substrate 500.
Afterwards, execution in step S407 please continue with reference to figure 9, the Semiconductor substrate 500 interior formation doped layers 517 under described opening 515;
The impurity that described doped layer 517 is used for suppressing channel region is the diffusion of boron ion and phosphonium ion for example, has suppressed the transient state enhancement effect, can improve the carrier mobility of channel region.
In an example of the present invention, the formation technique of described doped layer 517 is ion implantation technology, and the parameter area of described ion implantation technology is: energy is 5kev～30kev, and implantation dosage is 1E13/cm
2～1E15/cm
2
In another example of the present invention, described doped layer 517 adopts the more shallow magnetic plasma sputter injection technology of ion of injecting to form.The technological parameter of described magnetic plasma sputter injection technology is specially: energy is 0.5kev～4kev, and implantation dosage is 1E13/cm
2～1E15/cm
2, the N in the described doped layer 517 of formation
+Concentration is 1E17/cm
3～1E21/cm
3Described doped layer 517 can the establishment channel region the diffusion of impurity, improve the mobility of charge carrier.
Need to prove, in other embodiments of the invention, comprise N in the described doped layer 517
+, C
+, F
+In one or more combinations.
Execution in step S409 please refer to Figure 10, forms the gate insulation layer 519 that is positioned at described Semiconductor substrate 500 surfaces, the gate electrode layer 521 that is positioned at described gate insulation layer 519 surfaces in described opening; Remove described dielectric layer (not shown), expose described Semiconductor substrate 500 and side wall 511.
Described gate insulation layer 519 is used for isolate gate electrode layer 521 and source electrode 506, reaches gate electrode layer 521 and drains 505; Described gate electrode layer 521 is used to form grid.In the second embodiment of the present invention, when the material of described gate insulation layer 519 was silica, the material of described gate electrode layer 521 was polysilicon; When the material of described gate insulation layer 519 was high K dielectric, the material of described gate electrode layer 521 was metal.
Adopt the MOS transistor of the formation method formation of second embodiment of the invention, please continue with reference to Figure 10, comprising:
Be positioned at the doped layer 517 of the Semiconductor substrate 500 of described gate insulation layer 519 bottoms.
Wherein, the formation technique of described doped layer 517 is Implantation, for example magnetic plasma sputter injection technology; Ion concentration in the described doped layer 517 is 1E17/cm
3～1E21/cm
3Comprise N in the described doped layer 517
+, C
+, F
+In one or more combinations.
MOS transistor in the second embodiment of the invention is to inject N in the channel region in the Semiconductor substrate of gate insulation layer bottom
+, C
+, F
+In one or more be combined to form doped layer, establishment the diffusion of impurity in the channel region, improved the mobility of charge carrier.
To sum up, embodiments of the invention are to form doped layer in the channel region in the Semiconductor substrate of gate insulation layer bottom, establishment the diffusion of impurity in the channel region, improved the mobility of charge carrier.
Further, the embodiment of the invention adopts ion implantation technology to inject N in gate electrode insulation surface
+, C
+, F
+In one or more be combined to and form doped layer in the Semiconductor substrate, the shape of the gate insulation layer of described ion implantation technology in the middle of edge thickness is higher than is originally revised, and has avoided beak effect; And, also comprise N in the described gate insulation layer
+, C
+, F
+In one or more combinations, effectively reduce the leakage current of grid, the good stability of grid.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (17)
1. the formation method of a MOS transistor comprises:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with gate insulation layer, be positioned at the pseudo-gate electrode layer of described gate electrode insulation surface, be positioned at described gate insulation layer and pseudo-gate electrode layer both sides semiconductor substrate surface side wall and be positioned at described gate insulation layer and the source of the Semiconductor substrate of pseudo-gate electrode layer both sides/drain electrode;
It is characterized in that, also comprise:
Form the dielectric layer that covers described Semiconductor substrate and described side wall, the flush of described dielectric layer and described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer, form the opening that exposes described gate insulation layer;
Form doped layer in the Semiconductor substrate under described opening;
In described opening, form the gate electrode layer that is positioned at described gate electrode insulation surface;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
2. the formation method of MOS transistor as claimed in claim 1 is characterized in that, the formation technique of described doped layer is ion implantation technology; The ion that injects in the described ion implantation technology comprises N
+, C
+, F
+In one or more combinations.
3. the formation method of MOS transistor as claimed in claim 2 is characterized in that, the parameter area of described ion implantation technology is: energy is 5kev～15kev; Dosage is 1E13/cm
2～1E15/cm
2
4. the formation method of MOS transistor as claimed in claim 2 is characterized in that, described ion implantation technology is magnetic plasma sputter injection technology.
5. such as the formation method of claim 3 or 4 described MOS transistor, it is characterized in that, the injection direction of described ion implantation technology intermediate ion and the normal direction of described semiconductor substrate surface are 0～15 ° of angle.
6. the formation method of MOS transistor as claimed in claim 2 is characterized in that, comprises N in the described gate insulation layer
+, C
+, F
+In one or more combinations.
7. the formation method of MOS transistor as claimed in claim 1 is characterized in that, the formation technique of described gate insulation layer is situ steam oxide deposition technique.
8. the formation method of a MOS transistor comprises:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with pseudo-gate insulation layer, be positioned at the pseudo-gate electrode layer of described pseudo-gate electrode insulation surface, be positioned at described pseudo-gate insulation layer and pseudo-gate electrode layer both sides semiconductor substrate surface side wall and be positioned at described pseudo-gate insulation layer and the source of the Semiconductor substrate of pseudo-gate electrode layer both sides/drain electrode;
It is characterized in that, also comprise:
Form the dielectric layer that covers described Semiconductor substrate and described side wall, the flush of described dielectric layer and described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer and pseudo-gate insulation layer, form the opening that exposes described Semiconductor substrate;
Form doped layer in the Semiconductor substrate under described opening;
In described opening, form the gate insulation layer that is positioned at described semiconductor substrate surface, the gate electrode layer that is positioned at described gate electrode insulation surface;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
9. the formation method of MOS transistor as claimed in claim 8 is characterized in that, the formation technique of described doped layer is ion implantation technology; The ion that injects in the described ion implantation technology comprises N
+, C
+, F
+In one or more combinations.
10. the formation method of MOS transistor as claimed in claim 9 is characterized in that, the parameter area of described ion implantation technology is: energy is 5kev～15kev; Dosage is 1E13/cm
2～1E15/cm
2
11. the formation method of MOS transistor as claimed in claim 9 is characterized in that, described ion implantation technology is magnetic plasma sputter injection technology; The energy of described magnetic plasma sputter injection technology is 0.5kev～4kev, and dosage is 1E13/cm
2～1E15/cm
2
12. the formation method such as claim 10 or 11 described MOS transistor is characterized in that, the injection direction of described ion implantation technology intermediate ion and the normal direction of described semiconductor substrate surface are 0～15 ° of angle.
13. the formation method of MOS transistor as claimed in claim 7 is characterized in that, the formation technique of described gate insulation layer is situ steam oxide deposition technique.
14. the structure of a MOS transistor comprises:
Semiconductor substrate; Be positioned at the gate insulation layer of described semiconductor substrate surface; Be positioned at the gate electrode layer of described gate electrode insulation surface; Be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the source of described Semiconductor substrate/drain electrode;
It is characterized in that, also comprise:
Be positioned at the doped layer of the Semiconductor substrate of described gate insulation layer bottom.
15. the structure of MOS transistor as claimed in claim 14 is characterized in that, the ion that comprises in the described doped layer is N
+, C
+, F
+In one or more combinations.
16. the structure of MOS transistor as claimed in claim 14 is characterized in that, the ion concentration of described doped layer is 1E17/cm
3～1E21/cm
3
17. the structure of MOS transistor as claimed in claim 14 is characterized in that, comprises N in the described gate insulation layer
+, C
+, F
+In one or more combinations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110207726.9A CN102891076B (en) | 2011-07-22 | 2011-07-22 | Structure of MOS transistor and forming method thereof |
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