CN102891076B - Structure of MOS transistor and forming method thereof - Google Patents
Structure of MOS transistor and forming method thereof Download PDFInfo
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- CN102891076B CN102891076B CN201110207726.9A CN201110207726A CN102891076B CN 102891076 B CN102891076 B CN 102891076B CN 201110207726 A CN201110207726 A CN 201110207726A CN 102891076 B CN102891076 B CN 102891076B
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Abstract
The embodiment provides a kind of MOS transistor, comprising: Semiconductor substrate; Be positioned at the gate insulation layer of described semiconductor substrate surface; Be positioned at the gate electrode layer of described gate electrode insulation surface; Be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the source/drain of described Semiconductor substrate; Be positioned at the doped layer of the Semiconductor substrate bottom described gate insulation layer.Accordingly, embodiments of the invention additionally provide the formation method of above-mentioned MOS transistor, and the mobility of the MOS transistor charge carrier of the embodiment of the present invention is high, grid good stability.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to structure of a kind of MOS transistor and forming method thereof.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach higher arithmetic speed, larger memory data output and more function, and semiconductor device is towards higher component density, higher integrated level future development.
Please refer to Fig. 1, MOS transistor in prior art, comprising:
Semiconductor substrate 100; Be positioned at the fleet plough groove isolation structure 103 of described Semiconductor substrate 100;
Be positioned at the gate insulation layer 107 on described Semiconductor substrate 100 surface; And be positioned at the gate electrode layer 109 on described gate insulation layer 107 surface; Be positioned at described gate insulation layer 107 and gate electrode layer 109 both sides and be positioned at the side wall 111 on described Semiconductor substrate 100 surface;
Be positioned at described gate insulation layer 107 and gate electrode layer 109 both sides and be positioned at source electrode 106 and the drain electrode 105 of described Semiconductor substrate 100;
Along with MOS transistor is towards higher integrated level future development, the grid length of MOS transistor reduces gradually, namely in Fig. 1, gate insulation layer 107 and gate electrode layer 109 diminish gradually along the size of Semiconductor substrate 100 surface direction, and the mobility of the charge carrier of the channel region of the MOS transistor of prior art is lower.The more formation method about MOS transistor and structure please refer to the patent application document of United States Patent (USP) " US20080043588 ".
Summary of the invention
The problem that the present invention solves is to provide and a kind ofly increases structure of the MOS transistor of the mobility of the charge carrier of channel region and forming method thereof.
For solving the problem, the invention provides a kind of formation method of MOS transistor, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with gate insulation layer, be positioned at the pseudo-gate electrode layer of described gate electrode insulation surface, be positioned at the side wall of the semiconductor substrate surface of described gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source/drain of Semiconductor substrate of described gate insulation layer and pseudo-gate electrode layer both sides;
Form the dielectric layer covering described Semiconductor substrate and described side wall, described dielectric layer flushes with the surface of described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer, form the opening exposing described gate insulation layer;
Doped layer is formed in Semiconductor substrate immediately below described opening;
The gate electrode layer being positioned at described gate electrode insulation surface is formed in described opening;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Alternatively, the formation process of described doped layer is ion implantation technology; The ion injected in described ion implantation technology comprises N
+, C
+, F
-in one or more combination.
Alternatively, the parameter area of described ion implantation technology is: energy is 5kev ~ 30kev; Dosage is 1E13/cm
2~ 1E15/cm
2.
Alternatively, described ion implantation technology is magnetic plasma sputter injection technology.
Alternatively, the injection direction of the ion in described ion implantation technology and the normal direction of described semiconductor substrate surface are 0 ~ 15 ° of angle.
Alternatively, described gate insulation layer comprises N
+, C
+, F
-in one or more combination.
Alternatively, the formation process of described gate insulation layer is situ steam oxide deposition technique.
A formation method for MOS transistor, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with pseudo-gate insulation layer, be positioned at the pseudo-gate electrode layer of described pseudo-gate electrode insulation surface, be positioned at the side wall of the semiconductor substrate surface of described pseudo-gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source/drain of Semiconductor substrate of described pseudo-gate insulation layer and pseudo-gate electrode layer both sides;
Form the dielectric layer covering described Semiconductor substrate and described side wall, described dielectric layer flushes with the surface of described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer and pseudo-gate insulation layer, form the opening exposing described Semiconductor substrate;
Doped layer is formed in Semiconductor substrate immediately below described opening;
In described opening, formation is positioned at the gate insulation layer of described semiconductor substrate surface, is positioned at the gate electrode layer of described gate electrode insulation surface;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Alternatively, the formation process of described doped layer is ion implantation technology; The ion injected in described ion implantation technology comprises N
+, C
+, F
-in one or more combination.
Alternatively, the parameter area of described ion implantation technology is: energy is 5kev ~ 30kev; Dosage is 1E13/cm
2~ 1E15/cm
2.
Alternatively, described ion implantation technology is magnetic plasma sputter injection technology; The energy of described magnetic plasma sputter injection technology is 0.5kev ~ 4kev, and dosage is 1E13/cm
2~ 1E15/cm
2.
Alternatively, the injection direction of the ion in described ion implantation technology and the normal direction of described semiconductor substrate surface are 0 ~ 15 ° of angle.
Alternatively, the formation process of described gate insulation layer is situ steam oxide deposition technique.
A structure for MOS transistor, comprising:
Semiconductor substrate; Be positioned at the gate insulation layer of described semiconductor substrate surface; Be positioned at the gate electrode layer of described gate electrode insulation surface; Be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the source/drain of described Semiconductor substrate;
Be positioned at the doped layer of the Semiconductor substrate bottom described gate insulation layer.
Alternatively, the ion comprised in described doped layer is N
+, C
+, F
-in one or more combination.
Alternatively, the ion concentration of described doped layer is 1E17/cm
3~ 1E21/cm
3.
Alternatively, described gate insulation layer comprises N
+, C
+, F
-in one or more combination.
Compared with prior art, the present invention has the following advantages:
Be form doped layer in channel region in the Semiconductor substrate of embodiments of the invention bottom gate insulation layer, effectively inhibit the diffusion of impurity in channel region, improve the mobility of charge carrier.
Further, the embodiment of the present invention adopts ion implantation technology to inject N in gate electrode insulation surface
+, C
+, F
-in one or more be combined in Semiconductor substrate and form doped layer, the shape of script edge thickness higher than the gate insulation layer of centre is revised by described ion implantation technology, avoids beak effect; Further, also N is comprised in described gate insulation layer
+, C
+, F
-in one or more combination, effectively reduce the leakage current of grid, the good stability of grid.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the MOS transistor of prior art;
Fig. 2 is the schematic flow sheet of the formation method of the MOS transistor of first embodiment of the invention;
Fig. 3 ~ Fig. 6 is the cross-sectional view of the forming process of the MOS transistor of first embodiment of the invention;
Fig. 7 is the schematic flow sheet of the formation method of the MOS transistor of second embodiment of the invention;
Fig. 8 ~ Figure 10 is the cross-sectional view of the forming process of the MOS transistor of second embodiment of the invention.
Embodiment
From background technology, along with existing MOS transistor grid length continue reduce, the carrier mobility of the channel region of transistor reduces.
The inventor of the embodiment of the present invention finds after research, along with transistor gate length continue reduce, oxidation-enhanced diffusion (Oxidation-EnhancedDiffusion, OED) key factor of the boron ion affecting channel region and phosphonium ion diffusion is become, due to OED effect, cause Transient enhancement diffusion (Transistent-EnhancedDiffusion, TED), and transient state enhancement effect not only causes the short-channel effect of transistor, and have impact on the carrier mobility of channel region of transistor.
The inventor of the embodiment of the present invention finds after further research, in channel region, Doped ions forms doped layer, the diffusion of impurity such as boron ion and the phosphonium ion of channel region can be suppressed, inhibit transient state enhancement effect, the carrier mobility of channel region can be improved.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
First embodiment
Please refer to Fig. 2, the formation method of the MOS transistor of first embodiment of the invention, comprising:
Step S201, provides Semiconductor substrate; Described semiconductor substrate surface is formed with gate insulation layer; Be positioned at the pseudo-gate electrode layer of described gate electrode insulation surface; Be positioned at described gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source/drain of described Semiconductor substrate;
Step S203, form the dielectric layer covering described Semiconductor substrate and described side wall, described dielectric layer flushes with the surface of described pseudo-gate electrode layer;
Step S205, removes described pseudo-gate electrode layer, forms the opening exposing described gate insulation layer;
Step S207, forms doped layer in the Semiconductor substrate immediately below described opening;
Step S209, forms the gate electrode layer being positioned at described gate electrode insulation surface in described opening; Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Perform step S201, please refer to Fig. 3, Semiconductor substrate 300 is provided; Described Semiconductor substrate 300 surface is formed with gate insulation layer 307; Be positioned at the pseudo-gate electrode layer 309 on described gate insulation layer 307 surface; Be positioned at described gate insulation layer 307 and pseudo-gate electrode layer 309 both sides and be positioned at the side wall 311 on described Semiconductor substrate 300 surface; And be positioned at described gate insulation layer 307 and pseudo-gate electrode layer 309 both sides and be positioned at source electrode 306 and the drain electrode 305 of described Semiconductor substrate 300.
Described Semiconductor substrate 300 is for providing platform for follow-up formation MOS transistor.The material of described Semiconductor substrate 300 can be silicon substrate or silicon-on-insulator substrate (SOI substrate).
The gate electrode layer of described gate insulation layer 307 for the source electrode 306 in isolation of semiconductor substrate 300 and follow-up formation and the gate electrode layer of drain electrode 305 and follow-up formation, the material of described gate insulation layer 307 is silica or high K dielectric.
In an embodiment of the present invention, the formation process of described gate insulation layer 307 is situ steam oxide deposition technique.
Described pseudo-gate electrode layer 309 is for supporting for forming side wall 311.After considering described pseudo-gate electrode layer 309, extended meeting is removed, and for not destroying the gate insulation layer 307 and side wall 311 that contact with described pseudo-gate electrode layer 309, the material of described pseudo-gate electrode layer 309 is different from the material of described gate insulation layer 307 and described side wall 311.The inventor of the embodiment of the present invention finds after research, when the etching selection ratio between described pseudo-gate electrode layer 309 and gate insulation layer 307 is greater than 1, can not destroy described gate insulation layer 307 and described side wall 311 during the described pseudo-gate electrode layer 309 of follow-up removal.In an embodiment of the present invention, the material of described pseudo-gate electrode layer 309 is polysilicon.
In addition, the material of described side wall 311 is silicon nitride; Described source electrode 306 and drain electrode 305 adopt the mode of ion implantation to be formed.Also be formed with fleet plough groove isolation structure 303 in described Semiconductor substrate, described fleet plough groove isolation structure 303 is for the active area in isolation of semiconductor substrate 300.
Perform step S203, please continue to refer to Fig. 3, form the dielectric layer 313 covering described Semiconductor substrate 300 and described side wall 311, described dielectric layer 313 flushes with the surface of described pseudo-gate electrode layer 309.
Described dielectric layer 313, for the protection of source electrode 306, drain electrode 305 and side wall 311, makes described source electrode 306, drain electrode 305 and side wall 311 can not be destroyed in subsequent process steps.After considering dielectric layer 313, extended meeting is removed, and in order to not destroy when follow-up removal the side wall 311 and Semiconductor substrate 300 that contact with described dielectric layer 313, the material of described dielectric layer 313 is different from the material of described side wall 311, Semiconductor substrate 300.In an embodiment of the present invention, the material that the etching selection ratio between described dielectric layer 313 and side wall 311, between described dielectric layer 313 and described Semiconductor substrate 300 is greater than 1 is chosen, such as silica, as the material of dielectric layer 313.
The formation process of described dielectric layer 313 is depositing operation, such as physics or chemical vapour deposition (CVD).Because the technique depositing described dielectric layer 313 is well known to those skilled in the art, do not repeat them here.
Perform step S205, please refer to Fig. 4, remove described pseudo-gate electrode layer, form the opening 315 exposing described gate insulation layer 307.
The technique removing described pseudo-gate electrode layer is dry etching, owing to adopting dry etching to remove the technique of described pseudo-gate electrode layer known by those skilled in the art, does not repeat them here.
Described opening 315 is for the follow-up ion implantation window as forming doped layer.Described opening 315 exposes described gate insulation layer 307.
Perform step S207, please refer to Fig. 5, in the Semiconductor substrate 300 immediately below described opening 315, form doped layer 317.
Described doped layer 317, for suppressing the diffusion of impurity such as boron ion and the phosphonium ion of channel region, inhibits transient state enhancement effect, can improve the carrier mobility of channel region.
The inventor of the embodiment of the present invention finds after research, and adulterate N in channel region
+, C
+, F
-in one or more combination, formed comprise N
+, C
+, F
-in one or more combination doped layers 317, effectively can suppress the diffusion of the impurity of channel region.In an embodiment of the present invention, N is comprised in described doped layer 317
+ion.
The formation process of described doped layer 317 is ion implantation.In ion implantation technology process, when the direction of described ion implantation and Semiconductor substrate 300 normal to a surface direction are 0 ~ 15 degree of angle, the position of the doped layer 317 of formation is better, effectively can suppress the diffusion of the impurity of channel region.
To comprise N in described doped layer 317
+ion is that example carries out exemplary illustrated.In an embodiment of the present invention, adopt the energy of 5kev ~ 30kev, in the Semiconductor substrate 300 immediately below described opening 315, implantation dosage is 1E13/cm
2~ 1E15/cm
2n
+ion, the ion injected due to described ion implantation technology is comparatively dark, most described N
+ion is by resting in the Semiconductor substrate 300 immediately below described gate insulation layer 307 after gate insulation layer 307, in described Semiconductor substrate 300, form concentration is 1E17/cm
3~ 1E21/cm
3doped layer 317.When the ion concentration of described doped layer 317 is 1E18/cm
3~ 1E20/cm
3time, described doped layer 317 effectively can suppress the diffusion of the impurity of channel region, improves the mobility of charge carrier.
In addition, in an embodiment of the present invention, the N of fraction is also had
+rest in gate insulation layer 307, effectively reduced the drain electrode of grid, improved the stability of grid.
It should be noted that, if desired most N
+rest in gate insulation layer 307, reach and improve electric leakage of the grid pole, improve the object of grid stability, the magnetic plasma sputter injection technology that the ion implantation degree of depth can be adopted more shallow.Particularly, inventor is by regulating the energy of described ion implantation and the dosage of ion, the concentration of the ion in the concentration of the ion in doped layer 317 and/or gate insulation layer 307 is made to reach desired value, to realize the diffusion of the impurity suppressing channel region, improve the object of the mobility of charge carrier, and reduce the drain electrode of grid, improve the object of the stability of grid.
It should be noted that in addition, described gate insulation layer comprises N
+, C
+, F
-in one or more combinations, all can play and reduce the drain electrode of grid, improve the effect of the stability of grid.
In addition, inventor also finds, the size along with grid becomes more next little, and in the technique forming gate insulation layer 307, easily form the structure (beak effect) of edge thickness higher than interior thickness, this kind of structure is unfavorable for the stability of grid.And in an embodiment of the present invention, in described Semiconductor substrate 300, inject N in the position of described opening 315
+, C
+, F
-in one or more when being combined to form doped layer 317, described N
+, C
+, F
-in one or more combinations the defect of described gate insulation layer 307 is revised, make the thickness of described gate insulation layer 307 become uniformity, reduce beak effect, the stability of grid is strengthened.
Perform step S209, please refer to Fig. 6, in described opening, form the gate electrode layer 319 being positioned at described gate insulation layer 307 surface; Remove described dielectric layer, expose described Semiconductor substrate 300 and side wall 311.
Described gate electrode layer 319 is for the formation of grid.When the material of described gate insulation layer 307 is silica, the material of described gate electrode layer 319 is polysilicon; When the material of described gate insulation layer 307 is high K dielectric, the material of described gate electrode layer 319 is metal.
The formation process of described gate electrode layer 319 is depositing operation, such as physics or chemical deposition.The formation process of described gate electrode layer 319 is well known to those skilled in the art, does not repeat them here.
The technique removing described dielectric layer is etching technics, such as dry etching.After removing described dielectric layer, expose described Semiconductor substrate 300 and side wall 311.
Please continue to refer to Fig. 6, the structure of the MOS transistor adopting the formation method of first embodiment of the invention to be formed, comprising:
There is the Semiconductor substrate 300 of fleet plough groove isolation structure 303; Be positioned at the gate insulation layer 307 of described semiconductor substrate surface; Be positioned at the gate electrode layer 309 on described gate insulation layer 307 surface; Be positioned at described gate insulation layer 307 and gate electrode layer 309 both sides and be positioned at the side wall 311 on described Semiconductor substrate 300 surface; And be positioned at described gate insulation layer 307 and gate electrode layer 309 both sides and be positioned at source electrode 306 and the drain electrode 305 of described Semiconductor substrate 300;
Be positioned at the doped layer 317 of the Semiconductor substrate 300 bottom described gate insulation layer 307.
Wherein, the ion comprised in described doped layer 317 is N
+, C
+, F
-in one or more combination; Ion concentration in described doped layer 317 is 1E17/cm
3~ 1E21/cm
3; Described gate insulation layer 307 comprises N
+, C
+, F
-in one or more combination.
The MOS transistor formed in the first embodiment of the present invention, it is be formed in channel region to comprise N that the semiconductor bottom described gate insulation layer 307 sinks to the bottom in 300
+, C
+, F
-in one or more combination doped layers 317, effectively inhibit the diffusion of impurity in channel region, improve the mobility of charge carrier; Further, owing to being at gate insulation layer 307 surface imp lantation N
+, C
+, F
-in one or more combination, the shape of script edge thickness higher than the gate insulation layer 307 of centre is revised by described ion implantation technology, avoids beak effect; And also comprise N in described gate insulation layer 307
+, C
+, F
-in one or more combination, effectively reduce the leakage current of grid, the good stability of grid.
Second embodiment
Please refer to Fig. 7, the formation method of the MOS transistor of second embodiment of the invention, comprising:
Step S401, provides Semiconductor substrate; Described semiconductor substrate surface is formed with pseudo-gate insulation layer; Be positioned at the pseudo-gate electrode layer of described pseudo-gate electrode insulation surface; Be positioned at described pseudo-gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described pseudo-gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source/drain of described Semiconductor substrate;
Step S403, form the dielectric layer covering described Semiconductor substrate and described side wall, described dielectric layer flushes with the surface of described pseudo-gate electrode layer;
Step S405, removes described pseudo-gate electrode layer and pseudo-gate insulation layer, forms the opening exposing described Semiconductor substrate;
Step S407, forms doped layer in the Semiconductor substrate immediately below described opening;
Step S409, in described opening, formation is positioned at the gate insulation layer of described semiconductor substrate surface, is positioned at the gate electrode layer of described gate electrode insulation surface; Remove described dielectric layer, expose described Semiconductor substrate and side wall.
Perform step S401, please refer to Fig. 8, the Semiconductor substrate 500 with fleet plough groove isolation structure 503 is provided; Described Semiconductor substrate 500 surface is formed with pseudo-gate insulation layer 507; Be positioned at the pseudo-gate electrode layer 509 on described pseudo-gate insulation layer 507 surface; Be positioned at described pseudo-gate insulation layer 507 and pseudo-gate electrode layer 509 both sides and be positioned at the side wall 511 of described semiconductor substrate surface 500; And be positioned at described pseudo-gate insulation layer 507 and pseudo-gate electrode layer 509 both sides and be positioned at source electrode 506 and the drain electrode 505 of described Semiconductor substrate 500.
Perform step S403, please continue to refer to Fig. 8, form the dielectric layer 513 covering described Semiconductor substrate 500 and described side wall 511, described dielectric layer 513 flushes with the surface of described pseudo-gate electrode layer 509.
The material of described pseudo-gate insulation layer 507 and pseudo-gate electrode layer 509 is different from the material of side wall 511 and Semiconductor substrate 500.In the second embodiment of the present invention, the material of described pseudo-gate insulation layer 507 is silica, and the material of described pseudo-gate electrode layer 509 is polysilicon.
More formation methods about step S401 and step S403, please refer to step S201 and the step S203 of first embodiment of the invention.
Perform step S405, please refer to Fig. 9, remove described pseudo-gate electrode layer and pseudo-gate insulation layer, form the opening 515 exposing described Semiconductor substrate 500.
Remove described pseudo-gate electrode layer and pseudo-gate insulation layer technique is dry etching; Described opening 515 is for the follow-up ion implantation window as forming doped layer, and described opening 515 exposes described Semiconductor substrate 500.
Afterwards, perform step S407, please continue to refer to Fig. 9, in the Semiconductor substrate 500 immediately below described opening 515, form doped layer 517;
Described doped layer 517, for suppressing the diffusion of impurity such as boron ion and the phosphonium ion of channel region, inhibits transient state enhancement effect, can improve the carrier mobility of channel region.
In an example of the present invention, the formation process of described doped layer 517 is ion implantation technology, and the parameter area of described ion implantation technology is: energy is 5kev ~ 30kev, and implantation dosage is 1E13/cm
2~ 1E15/cm
2.
In another example of the present invention, described doped layer 517 adopts the magnetic plasma sputter injection technology that the ion of injection is more shallow to be formed.The technological parameter of described magnetic plasma sputter injection technology is specially: energy is 0.5kev ~ 4kev, and implantation dosage is 1E13/cm
2~ 1E15/cm
2, the N in the described doped layer 517 of formation
+concentration is 1E17/cm
3~ 1E21/cm
3.Described doped layer 517 effectively can suppress the diffusion of the impurity of channel region, improves the mobility of charge carrier.
It should be noted that, in other embodiments of the invention, described doped layer 517 comprises N
+, C
+, F
-in one or more combination.
Perform step S409, please refer to Figure 10, in described opening, formation is positioned at the gate insulation layer 519 on described Semiconductor substrate 500 surface, is positioned at the gate electrode layer 521 on described gate insulation layer 519 surface; Remove described dielectric layer (not shown), expose described Semiconductor substrate 500 and side wall 511.
Described gate insulation layer 519 is for isolate gate electrode layer 521 and source electrode 506 and gate electrode layer 521 and drain 505; Described gate electrode layer 521 is for the formation of grid.In the second embodiment of the present invention, when the material of described gate insulation layer 519 is silica, the material of described gate electrode layer 521 is polysilicon; When the material of described gate insulation layer 519 is high K dielectric, the material of described gate electrode layer 521 is metal.
The MOS transistor adopting the formation method of second embodiment of the invention to be formed, please continue to refer to Figure 10, comprising:
Semiconductor substrate 500, be positioned at the gate insulation layer 519 on described Semiconductor substrate 500 surface, be positioned at the gate electrode layer 521 on described gate insulation layer 519 surface, be positioned at the side wall 511 on Semiconductor substrate 500 surface of described gate insulation layer 519 and gate electrode layer 521 both sides and be positioned at described gate insulation layer 519 and gate electrode layer 521 both sides Semiconductor substrate 500 source electrode 506 and drain electrode 505;
Be positioned at the doped layer 517 of the Semiconductor substrate 500 bottom described gate insulation layer 519.
Wherein, the formation process of described doped layer 517 is ion implantation, such as magnetic plasma sputter injection technology; Ion concentration in described doped layer 517 is 1E17/cm
3~ 1E21/cm
3; Described doped layer 517 comprises N
+, C
+, F
-in one or more combination.
Be inject N in channel region in the Semiconductor substrate of MOS transistor in second embodiment of the invention bottom gate insulation layer
+, C
+, F
-in one or more be combined to form doped layer, effectively inhibit the diffusion of impurity in channel region, improve the mobility of charge carrier.
To sum up, be form doped layer in channel region in the Semiconductor substrate of embodiments of the invention bottom gate insulation layer, effectively inhibit the diffusion of impurity in channel region, improve the mobility of charge carrier.
Further, the embodiment of the present invention adopts ion implantation technology to inject N in gate electrode insulation surface
+, C
+, F
-in one or more be combined in Semiconductor substrate and form doped layer, the shape of script edge thickness higher than the gate insulation layer of centre is revised by described ion implantation technology, avoids beak effect; Further, also N is comprised in described gate insulation layer
+, C
+, F
-in one or more combination, effectively reduce the leakage current of grid, the good stability of grid.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (13)
1. a formation method for MOS transistor, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with gate insulation layer, be positioned at the pseudo-gate electrode layer of described gate electrode insulation surface, be positioned at the side wall of the semiconductor substrate surface of described gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source/drain of Semiconductor substrate of described gate insulation layer and pseudo-gate electrode layer both sides;
It is characterized in that, also comprise:
Form the dielectric layer covering described Semiconductor substrate and described side wall, described dielectric layer flushes with the surface of described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer, form the opening exposing described gate insulation layer;
Form doped layer in Semiconductor substrate immediately below described opening, the formation process of described doped layer is ion implantation technology; The ion injected in described ion implantation technology comprises N
+, F
-in one or N
+, C
+, F
-in multiple combination;
The gate electrode layer being positioned at described gate electrode insulation surface is formed in described opening;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
2. the formation method of MOS transistor as claimed in claim 1, it is characterized in that, the parameter area of described ion implantation technology is: energy is 5kev ~ 15kev; Dosage is 1E13/cm
2~ 1E15/cm
2.
3. the formation method of MOS transistor as claimed in claim 1, it is characterized in that, described ion implantation technology is magnetic plasma sputter injection technology.
4. the formation method of MOS transistor as claimed in claim 2 or claim 3, it is characterized in that, the injection direction of described ion implantation technology intermediate ion and the normal direction of described semiconductor substrate surface are 0 ~ 15 ° of angle.
5. the formation method of MOS transistor as claimed in claim 1, it is characterized in that, described gate insulation layer comprises N
+, F
-in one or N
+, C
+, F
-in multiple combination.
6. the formation method of MOS transistor as claimed in claim 1, it is characterized in that, the formation process of described gate insulation layer is situ steam oxide deposition technique.
7. a formation method for MOS transistor, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is formed with pseudo-gate insulation layer, be positioned at the pseudo-gate electrode layer of described pseudo-gate electrode insulation surface, be positioned at the side wall of the semiconductor substrate surface of described pseudo-gate insulation layer and pseudo-gate electrode layer both sides and be positioned at the source/drain of Semiconductor substrate of described pseudo-gate insulation layer and pseudo-gate electrode layer both sides;
It is characterized in that, also comprise:
Form the dielectric layer covering described Semiconductor substrate and described side wall, described dielectric layer flushes with the surface of described pseudo-gate electrode layer;
Remove described pseudo-gate electrode layer and pseudo-gate insulation layer, form the opening exposing described Semiconductor substrate;
Form doped layer in Semiconductor substrate immediately below described opening, the formation process of described doped layer is ion implantation technology; The ion injected in described ion implantation technology comprises N
+, F
-in one or N
+, C
+, F
-in multiple combination;
In described opening, formation is positioned at the gate insulation layer of described semiconductor substrate surface, is positioned at the gate electrode layer of described gate electrode insulation surface;
Remove described dielectric layer, expose described Semiconductor substrate and side wall.
8. the formation method of MOS transistor as claimed in claim 7, it is characterized in that, the parameter area of described ion implantation technology is: energy is 5kev ~ 15kev; Dosage is 1E13/cm
2~ 1E15/cm
2.
9. the formation method of MOS transistor as claimed in claim 7, it is characterized in that, described ion implantation technology is magnetic plasma sputter injection technology; The energy of described magnetic plasma sputter injection technology is 0.5kev ~ 4kev, and dosage is 1E13/cm
2~ 1E15/cm
2.
10. the formation method of MOS transistor as claimed in claim 8 or 9, it is characterized in that, the injection direction of described ion implantation technology intermediate ion and the normal direction of described semiconductor substrate surface are 0 ~ 15 ° of angle.
The formation method of 11. MOS transistor as claimed in claim 7, is characterized in that, the formation process of described gate insulation layer is situ steam oxide deposition technique.
The structure of 12. 1 kinds of MOS transistor, comprising:
Semiconductor substrate; Be positioned at the gate insulation layer of described semiconductor substrate surface; Be positioned at the gate electrode layer of described gate electrode insulation surface; Be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the side wall of described semiconductor substrate surface; And be positioned at described gate insulation layer and gate electrode layer both sides and be positioned at the source/drain of described Semiconductor substrate;
It is characterized in that, also comprise:
Be positioned at the doped layer of the Semiconductor substrate bottom described gate insulation layer, the formation process of described doped layer be to described gate insulation layer immediately below Semiconductor substrate carry out ion implantation, the ion injected in described ion implantation technology comprises N
+, F
-in one or N
+, C
+, F
-in multiple combination;
Described gate insulation layer comprises N
+, F
-in one or N
+, C
+, F
-in multiple combination.
The structure of 13. MOS transistor as claimed in claim 12, is characterized in that, the ion concentration of described doped layer is 1E17/cm
3~ 1E21/cm
3.
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