CN109003985B - Memory structure and forming method thereof - Google Patents
Memory structure and forming method thereof Download PDFInfo
- Publication number
- CN109003985B CN109003985B CN201810890862.4A CN201810890862A CN109003985B CN 109003985 B CN109003985 B CN 109003985B CN 201810890862 A CN201810890862 A CN 201810890862A CN 109003985 B CN109003985 B CN 109003985B
- Authority
- CN
- China
- Prior art keywords
- barrier layer
- dimensional
- layer
- barrier
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000004888 barrier function Effects 0.000 claims abstract description 149
- 238000009792 diffusion process Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000004020 conductor Substances 0.000 claims abstract description 25
- 238000003860 storage Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 22
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 10
- 229910021389 graphene Inorganic materials 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 158
- 230000000903 blocking effect Effects 0.000 description 8
- 239000002346 layers by function Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 2
- -1 tin alkene Chemical class 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention relates to a memory structure and a forming method thereof, wherein the memory structure comprises: a semiconductor substrate; a memory stack structure on the semiconductor substrate, including an insulating layer and a control gate layer stacked on each other; a channel structure extending through the storage stack structure to the semiconductor substrate; the control grid layer comprises a grid and a diffusion barrier layer positioned between the grid and the channel structure as well as between the grid and the insulating layer, and the diffusion barrier layer comprises at least one two-dimensional barrier layer made of a two-dimensional conductive material. The performance of the memory structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a memory structure and a method for forming the same.
Background
In recent years, flash (Memory) memories have been developed particularly rapidly. The flash memory has the main characteristics of long-term storage of stored information without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting, and the like, thereby being widely applied to various fields such as microcomputers, automatic control, and the like. In order to further increase the Bit Density (Bit Density) of the flash memory while reducing the Bit Cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been rapidly developed.
In a 3D NAND flash memory structure, the control gate includes a blocking layer for blocking out diffusion of metal atoms of the metal gate, and the metal gate. The control gate resistance of the prior art is larger, resulting in larger RC delay, affecting the performance of the 3D NAND flash memory.
Disclosure of Invention
The invention aims to solve the technical problem of providing a memory structure and a forming method thereof, which can improve the performance of a memory.
The present invention provides a memory structure comprising: a semiconductor substrate; a memory stack structure on the semiconductor substrate, including an insulating layer and a control gate layer stacked on each other; a channel structure extending through the storage stack structure to the semiconductor substrate; the control grid layer comprises a grid and a diffusion barrier layer positioned between the grid and the channel structure as well as between the grid and the insulating layer, and the diffusion barrier layer comprises at least one two-dimensional barrier layer made of a two-dimensional conductive material.
Optionally, the diffusion barrier layer further comprises at least one metal barrier layer.
Optionally, the two-dimensional barrier layer is located between the metal barrier layer and the gate electrode, or the metal barrier layer is located between the two-dimensional barrier layer and the gate electrode.
Optionally, the conductivity of the two-dimensional barrier layer is greater than the conductivity of the metal barrier layer.
Optionally, the material of the metal barrier layer includes at least one of Ti, ta, tiN, taN, co, coWP and TiW.
Optionally, the material of the two-dimensional barrier layer includes at least one of graphene and stannene.
Optionally, the thickness of the two-dimensional barrier layer is 0.3 nm to 3 nm.
In order to solve the above-mentioned problems, a specific embodiment of the present invention further provides a method for forming a memory structure, including: providing a semiconductor substrate, wherein an initial stacking structure and a channel structure are formed on the surface of the semiconductor substrate, the initial stacking structure comprises an insulating layer and a sacrificial layer which are sequentially stacked with each other, and the channel structure penetrates through the initial stacking structure; forming a grid line isolation groove penetrating through the initial stacking structure; removing the sacrificial layer along the grid line isolation groove to form an opening between adjacent insulating layers; forming a diffusion barrier layer covering the inner wall of the opening and a grid electrode positioned on the surface of the diffusion barrier layer; the diffusion barrier layer comprises at least one two-dimensional barrier layer made of a two-dimensional conductive material.
Optionally, the diffusion barrier layer further comprises at least one metal barrier layer.
Optionally, the two-dimensional barrier layer is located between the metal barrier layer and the gate electrode, or the metal barrier layer is located between the two-dimensional barrier layer and the gate electrode.
Optionally, the conductivity of the two-dimensional barrier layer is greater than the conductivity of the metal barrier layer.
Optionally, the material of the metal barrier layer includes at least one of Ti, ta, tiN, taN, co, coWP and TiW.
Optionally, the material of the two-dimensional barrier layer includes at least one of graphene and stannene.
Optionally, the two-dimensional barrier layer is formed by a chemical vapor deposition process, a silicon carbide epitaxial growth method, a metal-catalyzed epitaxial growth method or an atomic layer deposition process.
Optionally, the thickness of the two-dimensional barrier layer is 0.3 nm to 3 nm.
In the memory structure of the present invention, the control gate layer includes a diffusion barrier layer and a gate. The diffusion barrier layer at least comprises a two-dimensional barrier layer, the two-dimensional barrier layer is made of a two-dimensional conductive material, the resistance is low, RC delay can be reduced, programming time of the memory can be shortened, and performance of the memory is improved; and the thickness of the two-dimensional conductive material is low, so that a process window for forming the grid electrode can be increased, and the quality of the grid electrode is improved.
Drawings
Fig. 1 to 7 are schematic structural views of a memory structure forming process according to an embodiment of the present invention.
Detailed Description
The following describes in detail the memory structure and the forming method thereof provided by the present invention with reference to the accompanying drawings.
Referring to fig. 1 to 7, a schematic structure diagram of a memory structure forming process according to an embodiment of the invention is shown.
Referring to fig. 1, a semiconductor substrate 100 is provided, an initial stack structure 110 and a channel structure 120 are formed on a surface of the semiconductor substrate 100, the initial stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked sequentially on each other, and the channel structure 120 penetrates through the initial stack structure 110.
The semiconductor substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI, GOI, or the like; a suitable semiconductor substrate 100 may be selected according to the actual requirements of the device, and is not limited herein. In this embodiment, the semiconductor substrate 100 is a monocrystalline silicon wafer.
The initial stacked structure 110 includes an insulating layer 111 and a sacrificial layer 112. The sacrificial layer 112 of the initial stack structure 110 may be silicon nitride, and the insulating layer 111 may be silicon oxide.
The channel structure 120 includes a substrate epitaxial layer 123 formed at the bottom of the channel hole, a functional layer 121 covering the sidewall of the channel hole, and a channel dielectric layer 122 located on the surface of the functional layer 121 and filling the channel hole. The functional layer 121 further includes a blocking layer, a charge trapping layer, a tunneling layer, and a channel layer stacked 7 to 166 times from the sidewall surface of the channel hole. In this embodiment, the functional layer 121 has a composite layer structure of O-N-O-P (silicon oxide-silicon nitride-silicon oxide-polysilicon). The material of the channel dielectric layer 122 may be silicon oxide.
Referring to fig. 2, a gate line spacer 200 is formed through the initial stack structure 110.
A patterned mask layer is formed on the top surface of the initial stacked structure 110, the pattern of the patterned mask layer defines the position and the size of the gate line isolation groove to be formed, and the patterned mask layer is used as a mask to sequentially etch the initial stacked structure 110 to the semiconductor substrate 100, so as to form the gate line isolation groove 200. The sidewalls of the gate line isolation trench 200 expose the sacrificial layer 112.
Referring to fig. 3, the sacrificial layer 112 is removed along the gate line spacer 200 to form an opening 300 between adjacent insulating layers.
The sacrificial layer 112 may be removed by a wet etching process, and in particular, the etching solution used in the wet etching process may be a hot phosphoric acid solution.
After the sacrificial layer 112 is removed, forming a source doping region 201 in the semiconductor substrate 100 at the bottom of the gate line isolation trench 200; and forming an oxide layer 202 on the surface of the semiconductor substrate 100 at the bottom of the gate line isolation groove 200.
In this embodiment, ion implantation is performed on the bottom of the gate line isolation trench 200 to form the source doped region 201. The ion implantation adopts N-type doped ions P. In other embodiments, the ion implantation employs P-type dopant ions B, depending on the doping type requirements of the transistors in the memory structure. After the source doped region 201 is formed, an oxidation treatment is performed on the surface of the semiconductor substrate 100 at the bottom of the gate line isolation trench 200, so as to form an oxide layer 202. The oxidation treatment can be an in-situ water vapor generation process or an oxidation process such as thermal oxidation.
Referring to fig. 4, a diffusion barrier layer is formed to cover the inner wall of the opening 300.
In this embodiment, the diffusion barrier layer is a two-dimensional barrier layer 301 using a two-dimensional conductive material. Electrons of the two-dimensional conductive material conduct in a two-dimensional plane, so that the conductivity of the two-dimensional conductive material is generally higher than that of the three-dimensional conductive material, the resistance is lower, and the resistance of the control grid can be reduced, so that RC delay is reduced.
In this embodiment, the material of the two-dimensional barrier layer 301 is graphene. The graphene has high conductivity and diffusion blocking effect on metal atoms, so that the gate atoms formed later can be blocked from diffusing outwards, and the resistance of the control gate can be reduced.
The two-dimensional barrier layer 301 may be formed using a chemical vapor deposition process, a silicon carbide epitaxial growth process, a metal-catalyzed epitaxial growth process, or an atomic layer deposition process. Too large a thickness of the two-dimensional barrier 301 may result in a decrease in conductivity; the thickness of the two-dimensional barrier 301 should not be too small to avoid the problem of low deposition quality of the two-dimensional barrier 301. In this embodiment, the two-dimensional barrier layer 301 includes 1 to 10 two-dimensional graphene layers having a monoatomic layer structure. The thickness of the two-dimensional barrier layer 301 is 0.3 nm to 3 nm.
In other embodiments, the two-dimensional barrier 301 may also be other two-dimensional conductive materials, such as tin alkene. In other embodiments, the diffusion layer between the gate electrode 302 and the insulating layer 111 may further include two or more two-dimensional barrier layers 301.
Referring to fig. 5, a gate 302 is formed on the surface of the diffusion barrier 301 and fills the opening 300 (see fig. 4).
The material of the gate 302 is W, and an atomic layer deposition process may be used to deposit the gate 302, so as to ensure that the gate 302 in the opening 300 has higher deposition quality, and avoid the problem of voids in the control gate 302. In other embodiments, the material of the gate 302 may be polysilicon, al, cu, co, ag, metal silicide, or other conductive materials, and a chemical vapor deposition process may be used to form the gate 302.
The gate 302 and the two-dimensional diffusion barrier 301 form a control gate layer, the two-dimensional barrier 301 is located between the gate 302 and the channel structure 200 and between the two-dimensional barrier 301 and between the two-dimensional barrier and the insulating layer 111, and the control gate layer and the insulating layer 111 are alternately stacked to form a storage stack structure.
Referring to fig. 6, a schematic diagram of a memory structure according to another embodiment of the invention is shown.
In this embodiment, the diffusion barrier layer between the gate electrode 302 and the insulating layer 111 further includes a metal barrier layer 303. The metal barrier 303 is located between the two-dimensional barrier 301 and the gate 302. The material of the metal barrier layer 303 is TiN, which has a high capability of blocking metal diffusion, and can further prevent metal atoms of the gate 302 from diffusing outwards. In other specific embodiments, the material of the metal barrier layer 203 may further include at least one of Ti, ta, tiN, taN, co, coWP and TiW.
The metal barrier layer 203 may be formed using a chemical vapor deposition, an atomic layer deposition process, or a sputtering process. In this implementation, after the two-dimensional barrier layer 301 is formed, the metal barrier layer 303 is formed, and then the gate 302 is formed.
In other embodiments, the metal barrier 303 may also be located between the two-dimensional barrier 301 and the insulating layer 111. In other embodiments, the diffusion layer between the gate electrode 302 and the insulating layer 111 may further include more than two metal barrier layers 303, and the two-dimensional barrier layer 301 may be located between the two metal barrier layers 303.
The conductivity of the two-dimensional barrier layer 301 is greater than that of the metal barrier layer 303, and, because the material of the two-dimensional barrier layer 301 is a two-dimensional material, the thickness is lower, and compared with the metal barrier layer, the two-dimensional barrier layer 301 has lower thickness and lower resistance under the same barrier capability, so that the RC delay can be reduced and the process window of the gate 302 can be improved.
Referring to fig. 7, on the basis of the structure of fig. 5, insulating spacers 401 and common sources 402 filling the gate line isolation trenches 200 are formed on the sidewall surfaces of the gate line isolation trenches 200.
In the process of forming the gate 302 and the two-dimensional barrier 301, a gate material and a two-dimensional barrier material are deposited on the sidewall surface of the gate line isolation trench 200, and the gate material and the two-dimensional barrier material in the gate line isolation trench 200 are removed before forming the insulating sidewall 401 and the common source 402.
The method for forming the insulating sidewall 401 and the common source 402 includes: after depositing a side wall material layer on the inner wall surface of the grid line isolation groove 200, removing the side wall material at the bottom of the grid line isolation groove 200 by adopting a side wall etching process to form an insulating side wall 401 covering the side wall surface of the grid line isolation groove 200; then, the gate line isolation groove 200 is filled with a source material and planarized, so that the common source 402 filled with the gate line isolation groove 200 is formed. The insulating sidewall 401 is made of dielectric materials such as silicon oxide, silicon oxynitride, hafnium oxide, etc. In this embodiment, the material of the common source 402 is W. In other embodiments, the material of the common source 402 may be polysilicon, al, cu, co, ag, metal silicide, or other conductive materials.
In the method for forming a memory structure of the above embodiment, after the opening is formed by removing the sacrificial layer, a diffusion barrier layer and a gate electrode are formed as the control gate electrode in the opening. The diffusion barrier layer at least comprises a two-dimensional barrier layer, the two-dimensional barrier layer is made of a two-dimensional conductive material, the resistance is low, RC delay can be reduced, programming time of the memory can be shortened, and performance of the memory is improved. And the thickness of the two-dimensional conductive material is low, so that a process window for forming the grid electrode can be increased, and the deposition quality of the grid electrode is improved.
The embodiment of the invention also provides a memory structure.
Fig. 7 is a schematic structural diagram of a memory structure according to an embodiment of the invention.
The memory structure includes: a semiconductor substrate 100; a memory stack structure on the semiconductor substrate 100, the memory stack structure including an insulating layer 111 and a control gate layer stacked on each other; a channel structure 120 extending through the memory stack structure to the semiconductor substrate 100.
The semiconductor substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI, GOI, or the like; a suitable semiconductor substrate 100 may be selected according to the actual requirements of the device, and is not limited herein. In this embodiment, the semiconductor substrate 100 is a monocrystalline silicon wafer.
The channel structure 120 includes a substrate epitaxial layer 123 formed at the bottom of the channel hole, a functional layer 121 covering the sidewall of the channel hole, and a channel dielectric layer 122 located on the surface of the functional layer 121 and filling the channel hole. The functional layer 121 further includes a blocking layer, a charge trapping layer, a tunneling layer, and a channel layer stacked in this order from the surface of the sidewall of the channel hole. In this embodiment, the functional layer 121 has a composite layer structure of O-N-O-P (silicon oxide-silicon nitride-silicon oxide-polysilicon). The material of the channel dielectric layer 122 may be silicon oxide.
The insulating layer 111 may be made of an insulating dielectric material such as silicon oxide.
The control gate layer includes a gate 302 and a diffusion barrier layer between the gate 302 and the channel structure 200, the insulating layer 111, the diffusion barrier layer including at least one two-dimensional barrier layer 301 using a two-dimensional conductive material.
In this embodiment, the diffusion barrier layer comprises a two-dimensional barrier layer 301. Since electrons of the two-dimensional conductive material conduct in a two-dimensional plane, the conductivity of the two-dimensional conductive material is generally higher than that of the three-dimensional conductive material, the resistance is lower, and the resistance of the control gate can be reduced, so that RC delay is reduced.
In this embodiment, the material of the two-dimensional barrier layer 301 is graphene. The graphene has high conductivity and diffusion blocking effect on metal atoms, so that the gate atoms formed later can be blocked from diffusing outwards, and the resistance of the control gate can be reduced.
Too large a thickness of the two-dimensional barrier 301 may result in a decrease in conductivity; the thickness of the two-dimensional barrier 301 should not be too small to avoid the problem of low deposition quality of the two-dimensional barrier 301. The two-dimensional barrier layer 301 includes 1 to 10 two-dimensional graphene layers having a monoatomic layer structure. The thickness of the two-dimensional barrier layer 301 is 0.3 nm to 3 nm.
In other embodiments, the two-dimensional barrier 301 may also be other two-dimensional conductive materials, such as tin alkene. In other embodiments, the diffusion layer between the gate electrode 302 and the insulating layer 111 may further include two or more two-dimensional barrier layers 301.
In this embodiment, the material of the gate 302 is W; in other embodiments, the material of the gate 302 may be polysilicon, al, cu, co, ag, metal silicide, or other conductive materials.
The gate 302 and the two-dimensional diffusion barrier 301 form a control gate layer, the two-dimensional barrier 301 is located between the gate 302 and the channel structure 200 and between the two-dimensional barrier 301 and between the two-dimensional barrier and the insulating layer 111, and the control gate layer and the insulating layer 111 are alternately stacked to form a storage stack structure.
Referring to fig. 6, in another embodiment of the present invention, the diffusion barrier layer of the memory structure further includes a metal barrier layer 303. The metal barrier 303 is located between the two-dimensional barrier 301 and the gate 302. The material of the metal barrier layer 303 is TiN, which has a high capability of blocking metal diffusion, and can further prevent metal atoms of the gate 302 from diffusing outwards. In other specific embodiments, the material of the metal barrier layer 203 may further include at least one of Ti, ta, tiN, taN, co, coWP and TiW.
In other embodiments, the metal barrier 303 may also be located between the two-dimensional barrier 301 and the insulating layer 111. In other embodiments, the diffusion layer between the gate electrode 302 and the insulating layer 111 may further include two or more metal barrier layers 303. The two-dimensional barrier 301 may be located between two metal barriers 303.
The conductivity of the two-dimensional barrier layer 301 is greater than that of the metal barrier layer 303, and, because the material of the two-dimensional barrier layer 301 is a two-dimensional material, the thickness is lower, and compared with the metal barrier layer, the two-dimensional barrier layer 301 has lower thickness and lower resistance under the same barrier capability, so that the RC delay can be reduced and the process window of the gate 302 can be improved.
With continued reference to fig. 6, the memory structure further includes a common source structure. The common source structure penetrates through the storage stack structure and comprises an insulating side wall 401 covering the side wall of the grid line isolation groove and a common source 402 filling the grid line isolation groove. A source doped region 201 is further provided in the semiconductor substrate 100 at the bottom of the common source structure, and an oxide layer 202 is further provided between the bottom of the common source structure and the semiconductor substrate 100.
The insulating sidewall 401 is made of dielectric materials such as silicon oxide, silicon oxynitride, hafnium oxide, etc. In this embodiment, the material of the common source 402 is W. In other embodiments, the material of the common source 402 may be polysilicon, al, cu, co, ag, metal silicide, or other conductive materials.
In the memory structure of the above embodiment, the control gate layer includes a diffusion barrier layer and a gate. The diffusion barrier layer at least comprises a two-dimensional barrier layer, the two-dimensional barrier layer is made of a two-dimensional conductive material, the resistance is low, RC delay can be reduced, programming time of the memory can be shortened, and performance of the memory is improved. And the thickness of the two-dimensional conductive material is low, so that a process window for forming the grid electrode can be increased, and the quality of the grid electrode is improved.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (15)
1. A memory structure, comprising:
a semiconductor substrate;
a memory stack structure on the semiconductor substrate, including an insulating layer and a control gate layer stacked on each other;
a channel structure extending through the storage stack structure to the semiconductor substrate;
the control grid layer comprises a grid electrode, a channel structure and a diffusion barrier layer positioned between the grid electrode and the insulating layer, wherein the diffusion barrier layer comprises at least one two-dimensional barrier layer made of a two-dimensional conductive material;
and a common source structure penetrating the storage stack structure.
2. The memory structure of claim 1, wherein the diffusion barrier layer further comprises at least one metal barrier layer.
3. The memory structure of claim 2, wherein the two-dimensional barrier is located between the metal barrier and a gate or the metal barrier is located between the two-dimensional barrier and a gate.
4. The memory structure of claim 2, wherein the conductivity of the two-dimensional barrier is greater than the conductivity of the metal barrier.
5. The memory structure of claim 2, wherein the material of the metal barrier layer comprises at least one of Ti, ta, tiN, taN, co, coWP and TiW.
6. The memory structure of claim 1 or 2, wherein the material of the two-dimensional barrier layer comprises at least one of graphene and stannene.
7. The memory structure of claim 1, wherein the two-dimensional barrier layer has a thickness of 0.3 nm to 3 nm.
8. A method of forming a memory structure, comprising:
providing a semiconductor substrate, wherein an initial stacking structure and a channel structure are formed on the surface of the semiconductor substrate, the initial stacking structure comprises an insulating layer and a sacrificial layer which are sequentially stacked with each other, and the channel structure penetrates through the initial stacking structure;
forming a grid line isolation groove penetrating through the initial stacking structure;
removing the sacrificial layer along the grid line isolation groove to form an opening between adjacent insulating layers;
forming a diffusion barrier layer covering the inner wall of the opening and a grid electrode positioned on the surface of the diffusion barrier layer;
the diffusion barrier layer comprises at least one two-dimensional barrier layer made of a two-dimensional conductive material.
9. The method of forming a memory structure of claim 8, wherein the diffusion barrier further comprises at least one metal barrier.
10. The method of claim 9, wherein the two-dimensional barrier is located between the metal barrier and the gate or the metal barrier is located between the two-dimensional barrier and the gate.
11. The method of claim 9, wherein the conductivity of the two-dimensional barrier layer is greater than the conductivity of the metal barrier layer.
12. The method of claim 9, wherein the material of the metal barrier layer comprises at least one of Ti, ta, tiN, taN, co, coWP and TiW.
13. The method of claim 8 or 9, wherein the material of the two-dimensional barrier layer comprises at least one of graphene and stannene.
14. The method of claim 8, wherein the two-dimensional barrier layer is formed using a chemical vapor deposition process, a silicon carbide epitaxial growth process, a metal-catalyzed epitaxial growth process, or an atomic layer deposition process.
15. The method of claim 8, wherein the two-dimensional barrier layer has a thickness of 0.3 nm to 3 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810890862.4A CN109003985B (en) | 2018-08-07 | 2018-08-07 | Memory structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810890862.4A CN109003985B (en) | 2018-08-07 | 2018-08-07 | Memory structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109003985A CN109003985A (en) | 2018-12-14 |
| CN109003985B true CN109003985B (en) | 2024-03-29 |
Family
ID=64596187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810890862.4A Active CN109003985B (en) | 2018-08-07 | 2018-08-07 | Memory structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109003985B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211967B (en) * | 2019-04-19 | 2021-07-27 | 华中科技大学 | Three-dimensional flash memory based on titanium-tungsten alloy gate electrode and preparation method thereof |
| CN110808253B (en) * | 2019-10-12 | 2022-10-11 | 长江存储科技有限责任公司 | Three-dimensional memory structure and preparation method thereof |
| CN110676256B (en) * | 2019-10-14 | 2023-08-08 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111180320B (en) * | 2020-01-02 | 2022-10-28 | 长江存储科技有限责任公司 | Manufacturing method of grid electrode, structure thereof and semiconductor device |
| CN111466026B (en) * | 2020-03-11 | 2022-06-07 | 长江存储科技有限责任公司 | Three-dimensional memory device with two-dimensional material |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102509727A (en) * | 2011-12-02 | 2012-06-20 | 清华大学 | Trapped charge capture type flash memory array structure and operation method thereof |
| KR20140045167A (en) * | 2012-10-08 | 2014-04-16 | 삼성전자주식회사 | Memory array using graphene switching device |
| WO2015173580A1 (en) * | 2014-05-16 | 2015-11-19 | The University Of Manchester | Improved plasmonic structures and devices |
| CN105355602A (en) * | 2015-10-19 | 2016-02-24 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and fabrication method thereof |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and manufacturing method therefor |
| CN105679761A (en) * | 2016-01-26 | 2016-06-15 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and production method of three-dimensional semiconductor device |
| CN106558587A (en) * | 2015-09-22 | 2017-04-05 | 爱思开海力士有限公司 | Semiconductor device and its manufacture method |
| US9806256B1 (en) * | 2016-10-21 | 2017-10-31 | Sandisk Technologies Llc | Resistive memory device having sidewall spacer electrode and method of making thereof |
| CN107331646A (en) * | 2016-04-28 | 2017-11-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108365008A (en) * | 2018-01-11 | 2018-08-03 | 北京华碳科技有限责任公司 | Has the preparation method of p-type two-dimensional material grid enhancement type gallium nitride fieldtron |
| CN208521934U (en) * | 2018-08-07 | 2019-02-19 | 长江存储科技有限责任公司 | Memory construction |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10131627B4 (en) * | 2001-06-29 | 2006-08-10 | Infineon Technologies Ag | Method for producing a semiconductor memory device |
| KR100760923B1 (en) * | 2006-08-30 | 2007-09-21 | 동부일렉트로닉스 주식회사 | Semiconductor devic having fluorine diffusion barrier layer and method for manufacturing the same |
| US20120286349A1 (en) * | 2011-05-13 | 2012-11-15 | Globalfoundries Singapore Pte Ltd | Non-Volatile Memory Device With Additional Conductive Storage Layer |
| KR101912397B1 (en) * | 2011-11-25 | 2018-10-29 | 삼성전자주식회사 | Semiconductor memory device having three-dimensionally arranged resistive memory cells |
| WO2013096273A1 (en) * | 2011-12-20 | 2013-06-27 | University Of Florida Research Foundation, Inc. | Graphene-based metal diffusion barrier |
| US9472450B2 (en) * | 2012-05-10 | 2016-10-18 | Samsung Electronics Co., Ltd. | Graphene cap for copper interconnect structures |
| JP6095951B2 (en) * | 2012-11-09 | 2017-03-15 | エスケーハイニックス株式会社ＳＫ ｈｙｎｉｘ Ｉｎｃ． | Semiconductor device and manufacturing method thereof |
| US9685559B2 (en) * | 2012-12-21 | 2017-06-20 | The Regents Of The University Of California | Vertically stacked heterostructures including graphene |
| US9293205B2 (en) * | 2013-09-14 | 2016-03-22 | Aplus Flash Technology, Inc | Multi-task concurrent/pipeline NAND operations on all planes |
| KR102356682B1 (en) * | 2015-05-11 | 2022-01-27 | 삼성전자주식회사 | Nonvolatile memory device using 2-dimensional material and method of manufacturing the same |
| US10361213B2 (en) * | 2016-06-28 | 2019-07-23 | Sandisk Technologies Llc | Three dimensional memory device containing multilayer wordline barrier films and method of making thereof |
| KR20180027708A (en) * | 2016-09-06 | 2018-03-15 | 삼성전자주식회사 | Semiconductor memory device and method of fabricating the same |
| KR102629466B1 (en) * | 2016-09-21 | 2024-01-26 | 에스케이하이닉스 주식회사 | Manufacturing method of semiconductor device |
| US10083982B2 (en) * | 2016-11-17 | 2018-09-25 | Sandisk Technologies Llc | Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof |
-
2018
- 2018-08-07 CN CN201810890862.4A patent/CN109003985B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102509727A (en) * | 2011-12-02 | 2012-06-20 | 清华大学 | Trapped charge capture type flash memory array structure and operation method thereof |
| KR20140045167A (en) * | 2012-10-08 | 2014-04-16 | 삼성전자주식회사 | Memory array using graphene switching device |
| WO2015173580A1 (en) * | 2014-05-16 | 2015-11-19 | The University Of Manchester | Improved plasmonic structures and devices |
| CN106558587A (en) * | 2015-09-22 | 2017-04-05 | 爱思开海力士有限公司 | Semiconductor device and its manufacture method |
| CN105355602A (en) * | 2015-10-19 | 2016-02-24 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and fabrication method thereof |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and manufacturing method therefor |
| CN105679761A (en) * | 2016-01-26 | 2016-06-15 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and production method of three-dimensional semiconductor device |
| CN107331646A (en) * | 2016-04-28 | 2017-11-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US9806256B1 (en) * | 2016-10-21 | 2017-10-31 | Sandisk Technologies Llc | Resistive memory device having sidewall spacer electrode and method of making thereof |
| CN108365008A (en) * | 2018-01-11 | 2018-08-03 | 北京华碳科技有限责任公司 | Has the preparation method of p-type two-dimensional material grid enhancement type gallium nitride fieldtron |
| CN208521934U (en) * | 2018-08-07 | 2019-02-19 | 长江存储科技有限责任公司 | Memory construction |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109003985A (en) | 2018-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109003985B (en) | Memory structure and forming method thereof | |
| US9773708B1 (en) | Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI | |
| US8637913B2 (en) | Nonvolatile memory device and method for fabricating the same | |
| US20230209822A1 (en) | Integrated Assemblies and Methods of Forming Integrated Assemblies | |
| US8163617B2 (en) | Vertical channel type non-volatile memory device and method for fabricating the same | |
| US9000510B2 (en) | Nonvolatile memory device with upper source plane and buried bit line | |
| CN103824860B (en) | Method for manufacturing memory cell, method for manufacturing memory cell arrangement, and memory cell | |
| US20090096011A1 (en) | Non-Volatile Memory Device Having Asymmetric Source/Drain Junction and Method for Fabricating the Same | |
| CN109698200A (en) | Transistor, semiconductor subassembly and the method for forming memory subassembly | |
| CN111564442B (en) | Semiconductor structure and preparation method | |
| WO2007005191A1 (en) | Source side injection storage device with spacer gates and method therefor | |
| JP2006228844A (en) | Nonvolatile semiconductor memory device and its manufacturing method | |
| CN112951841B (en) | Three-dimensional memory and preparation method thereof | |
| CN104900594A (en) | Nonvolatile memory forming method | |
| CN108807392B (en) | Flash memory and manufacturing method thereof | |
| CN112838097A (en) | Three-dimensional memory and preparation method thereof | |
| CN112820736A (en) | Three-dimensional memory and preparation method thereof | |
| CN110112136B (en) | Semiconductor structure and forming method thereof | |
| CN111373538B (en) | Three-dimensional memory device and method of fabricating the same | |
| US7195973B2 (en) | Method for fabricating a trench capacitor with an insulation collar and corresponding trench capacitor | |
| CN109256393B (en) | Method for forming memory structure | |
| TWI824528B (en) | Semiconductor devices having vertical channel transistor structures | |
| CN109755312B (en) | Nanowire transistor and preparation method thereof | |
| CN208521934U (en) | Memory construction | |
| US20110176363A1 (en) | Junction leakage suppression in memory devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |