CN105679761A - Three-dimensional semiconductor device and production method of three-dimensional semiconductor device - Google Patents
Three-dimensional semiconductor device and production method of three-dimensional semiconductor device Download PDFInfo
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- CN105679761A CN105679761A CN201610052951.2A CN201610052951A CN105679761A CN 105679761 A CN105679761 A CN 105679761A CN 201610052951 A CN201610052951 A CN 201610052951A CN 105679761 A CN105679761 A CN 105679761A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims description 243
- 239000000463 material Substances 0.000 claims description 57
- 238000009825 accumulation Methods 0.000 claims description 45
- 230000004888 barrier function Effects 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000009826 distribution Methods 0.000 claims description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 11
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 10
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000005121 nitriding Methods 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 25
- 238000003860 storage Methods 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 230000005641 tunneling Effects 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 238000001451 molecular beam epitaxy Methods 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000005755 formation reaction Methods 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- -1 SiN Chemical class 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 229910003465 moissanite Inorganic materials 0.000 description 4
- 230000036961 partial effect Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000002585 base Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000013081 microcrystal Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000035755 proliferation Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000004576 sand Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052693 Europium Inorganic materials 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 235000019994 cava Nutrition 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052702 rhenium Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910017107 AlOx Inorganic materials 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910005538 GaSn Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910004304 SiNy Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 229910010252 TiO3 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910003134 ZrOx Inorganic materials 0.000 description 1
- TZHYBRCGYCPGBQ-UHFFFAOYSA-N [B].[N] Chemical compound [B].[N] TZHYBRCGYCPGBQ-UHFFFAOYSA-N 0.000 description 1
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000001117 sulphuric acid Substances 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a production method of a three-dimensional semiconductor device. The method comprises following steps of forming a mask layer stack composed of multiple alternate first and second mask layers on a substrate; etching the mask stack to form channel holes, thus exposing the top of the substrate and the side walls of the first and second mask layers; removing one part of the second mask layers to form hollows; conformally forming blocking layer in the channel holes and the hollows; forming storage layers on the blocking layers; selectively etching so as to remove one part of the storage layers; and conformally forming tunneling layers in the channel holes and the hollows. According to the three-dimensional semiconductor device and the production method of the three-dimensional semiconductor device provided by the invention, the transversely diffused accesses are cut off by utilizing separated storage layer structures; and the data hold characteristic is improved.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of three-dimensional semiconductor memory device and manufacture method thereof.
Background technology
In order to improve the density of memory device, industry has extensively been devoted to the method for the size of the memory cell of research and development reduction two-dimensional arrangement. Along with the memory cell dimensions continual reductions of two dimension (2D) memory device, signal conflict and interference can enlarge markedly, to such an extent as to are difficult to carry out multi-level-cell (MLC) operation. In order to overcome the restriction of 2D memory device, industry has been developed that the memory device with three-dimensional (3D) structure, improves integration density by memory cell is three-dimensionally disposed in substrate.
Concrete, it is possible to first at deposited on substrates multi-layer laminate structure (such as oxide and nitride multiple ONO structure alternately); By anisotropic etching technics, multi-layer laminate structure etching on substrate is formed along the distribution of memory cell wordline (WL) bearing of trend, is perpendicular to multiple raceway groove through holes (can go directly substrate surface or have certain over etching) of substrate surface; The laminated construction of selective etch raceway groove through-hole side wall is to form multiple depression, such as partly etching is removed a part for the nitride in ONO structure and is formed depression in upper and lower two-layer oxide, sequentially forms the stacked dielectric layer of barrier layer, accumulation layer, tunnel layer composition subsequently in the valley; In raceway groove through hole, the material such as deposit polycrystalline silicon forms column raceway groove; Etch multi-layer laminate structure along WL direction and form the groove of through substrate, expose be enclosed in around column raceway groove multilayer laminated; Wet method removes a certain types of material (such as removing the oxide in ONO structure, only retained nitrogen compound completely) in lamination, leaves the raised structures of cross direction profiles around column raceway groove; The side wall deposition gate dielectric layer (such as high K medium material) of raised structures and grid conducting layer (such as Ti, W, Cu, Mo etc.) form gate stack in the trench, for instance include bottom and select gate line, dummy gate electrode line, wordline, top to select gate line; Perpendicular magnetic anisotropy etching removes the gate stack outside raised sides plane, until exposing the gate dielectric layer of projection side; Etching stack structure forms source and drain and contacts and complete back end fabrication. Now, the sealing coat that a part of projection that laminated construction stays in column trench sidewalls defines between gate electrode, and the gate stack stayed is folded between multiple sealing coat as controlling electrode. When a voltage is applied to the gate electrode, the fringe field of grid can make sensing in the column trench sidewalls of such as polycrystalline silicon material form source-drain area, thus constitutes multiple series-parallel MOSFET gate array constituted and records stored logic state.By the voltage of control gate so that in accumulation layer, CHARGE DISTRIBUTION changes, thus corresponding to the change of logic state.
But, as it is shown in figure 1, in the local structure figure of above-mentioned device, As time goes on the electric charge (shown in semicircular area) of accumulation in accumulation layer gradually to external diffusion, can cause the threshold voltage shift shown in Fig. 2. Wherein, the Vt drift that in Fig. 2,1. curve causes to the electric charge of control gate, barrier insulating layer diffusion corresponding to being perpendicular to raceway groove distribution arrangement in Fig. 1. In addition, in accumulation layer, the electric charge of accumulation not only can to directly corresponding grid direction diffusion, also can further to adjacent (along raceway groove distribution arrangement, namely vertical direction) grid corresponding charge storaging area diffusion, cause neutralization unnecessary between erasing hole and programming electronics, cause that 1.+2. bigger shown in curve Vt drifts about in Fig. 2.
Summary of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, it is proposed to a kind of novelty three-dimensional semiconductor memory device and manufacture method thereof, utilizing the accumulation layer structure separated to block the path of horizontal proliferation, thus improving data retention characteristics.
For this, one aspect of the present invention provides a kind of three-dimensional semiconductor device manufacture method, including: the mask layer forming alternately multiple first, second mask layer composition on substrate is stacking; Etch mask layer stacking formation raceway groove hole, exposes substrate top, the first and second mask layer sidewalls; Remove a part for the second mask layer to form depression; Raceway groove hole and depression are conformally formed barrier layer; Form accumulation layer over the barrier layer; Selective etch removes a part for accumulation layer; Raceway groove hole and depression are conformally formed tunnel layer.
Wherein, the first mask layer is insulant, and the second mask layer is semi-conducting material or insulant; Preferably, insulant is any one or its combination of silicon nitride, silicon oxide, silicon oxynitride, amorphous carbon, carbonitride of silicium, silicon oxide carbide, boron nitride, aluminium oxide; Preferably, semi-conducting material is silicon, germanium or its combination; Preferably, semi-conducting material is polycrystalline, amorphous, crystallite.
Wherein, the step forming barrier layer farther includes: be conformally formed adhesion layer in raceway groove hole and depression; Perform oxidation and/or nitriding process, adhesion layer is converted into barrier layer at least partially; Preferably, oxidation technology is ISSG, FRE--RTO, chemical oxidation; Preferably, adhesion layer material is same or like with the second mask layer material.
Wherein, the step of the part that selective etch removes accumulation layer farther includes: be conformally formed sacrifice bed course in raceway groove hole and depression; Perform oxidation and/or nitriding process, sacrifice backing layer portion is converted into sacrifice layer, accumulation layer in the valley leaves protective layer; Remove sacrifice layer; Selective etch removes a part for accumulation layer, retains the residue accumulation layer covered by protective layer.
Wherein, form depression before, formed after raceway groove hole and farther include: form epitaxial layer at raceway groove hole base substrate Epitaxial growth.
Wherein, the material of barrier layer and/or tunnel layer is silicon oxide or high-g value; Optionally, accumulation layer material is silicon nitride, hafnium oxide, zirconium oxide, yittrium oxide or its combination.
Wherein, step is farther included after formation tunnel layer: in raceway groove hole and depression, form channel layer; Drain electrode is formed at channel layer top; The stacking formation vertical openings of etch mask layer, exposes remaining second mask layer sidewall and substrate top;Selective etch removes remaining second mask layer, leaves groove; Common source is formed bottom vertical openings; Form control gate in a groove; Form source and drain deriving structure.
Present invention also offers a kind of three-dimensional semiconductor device, including: channel layer, along the directional spreding being perpendicular to substrate surface; Multiple insulating barriers, alternately laminated along the sidewall of channel layer; Control gate, is folded between adjacent insulating barrier; Gate insulator stack, is distributed between channel layer and control gate, including barrier layer, accumulation layer and tunnel layer, and wherein barrier layer and tunnel layer continuous distribution and accumulation layer Disjunct distribution.
Wherein, also include drain electrode, be positioned at the top of channel layer; And source electrode, in the substrate between adjacent two memory element of multiple memory element.
Wherein, the material of barrier layer and/or tunnel layer is silicon oxide or high-g value; Optionally, accumulation layer material is silicon nitride, hafnium oxide, zirconium oxide, yittrium oxide or its combination.
According to three-dimensional semiconductor memory device and the manufacture method thereof of the present invention, the accumulation layer structure separated is utilized to block the path of horizontal proliferation, thus improving data retention characteristics.
Accompanying drawing explanation
Technical scheme is described in detail referring to accompanying drawing, wherein:
Fig. 1 is the partial sectional view of prior art 3D memory device;
Fig. 2 is the Vt drift schematic diagram of device shown in Fig. 1;
Fig. 3 A to Fig. 3 J is the sectional view of each step of the three-dimensional semiconductor memory device manufacture method according to the embodiment of the present invention;
Fig. 4 is the partial enlarged drawing of structure shown in Fig. 3 J;
Fig. 5 is the indicative flowchart of the three-dimensional semiconductor memory device manufacture method according to the embodiment of the present invention.
Detailed description of the invention
Referring to accompanying drawing the feature and the technique effect thereof that describe technical solution of the present invention in conjunction with schematic embodiment in detail, disclose the semiconductor storage unit and manufacture method thereof that effectively improve data retention characteristics. It is pointed out that similar accompanying drawing labelling represents similar structure, term " first " use herein, " second ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process. These modifications do not imply that modified device architecture or the space of manufacturing process, order or hierarchical relationship unless stated otherwise.
As shown in Figure 3A, multiple raceway groove hole epitaxial substrate are etched.
Substrate 1 is provided, its material can include body silicon (bulkSi), body germanium (bulkGe), silicon-on-insulator (SOI), germanium on insulator (GeOI) or other compound semiconductor substrate, such as SiGe, SiC, GaN, GaAs, InP etc., and the combination of these materials. In order to compatible with existing IC manufacturing process, substrate is preferably the substrate of siliceous material, for instance Si, SOI, SiGe, Si:C etc.
Adopt the film-forming process such as including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, oxidation etc., form mask layer stacking 2, including alternately laminated multiple first mask layer 2A and multiple second mask layer 2B. Preferably, between adjacent sublayers, material is insulant and mutually different: such as layer 2A is silicon oxide
SiOx, layer 2B is silicon oxynitride SiOxNyOr silicon nitride SiNy; Or layer 2A is silicon oxide or silicon nitride or silicon oxynitride, and layer 2B is amorphous carbon, fire sand, silicon oxide carbide, boron nitride, aluminium oxide etc.; Or each sublayer 2A/2B formula is SiOxNy, but between adjacent layer, ON atom ratio is different to obtain different Etch selectivities.In a preferred embodiment of the invention, the first mask layer 2A is silicon oxide, and the second mask layer 2B is silicon nitride. In other preferred embodiments of the present invention, layer 2B can also be the semi-conducting materials such as polysilicon/germanium, non-crystalline silicon/germanium, microcrystal silicon/germanium, and layer 2A is then above-mentioned insulant, as long as having bigger Etch selectivity between adjacent layer.
Preferably, more than the second mask layer 2B one of the number of the first mask layer 2A, such as stacking orlop and top are the first mask layer 2A, and it is further preferred that the first mask layer 2A thickness of top to be significantly greater than remaining first mask layer 2A or the second mask layer 2B. Such as, except the 2A of top, remaining layer of 2A, 2B thickness is 10～200nm, and the 2A thickness of top is that 300～1000nm is for use as the etch hardmask at top, protective layer or the dielectric isolation layer covering whole wafer.
The stacking 2A/2B of mask layer in etched substrate, forms the multiple deep hole 2T (only illustrating in Fig. 3 A) exposing stacking sidewall. Select anisotropic etch process, for instance select the fluorine-based (C of carbonxHyFzConstitute fluorohydrocarbon) as the plasma dry etch of etching gas or RIE, the folded 2A/2B of etching aforementioned mask layer stack vertically downward, until exposing substrate 1 surface, form multiple deep hole or groove 2T (although Fig. 3 A only illustrates one, but can essentially exist multiple in plan view, corresponding to multiple memory cells), deep hole or groove 2T expose the sidewall of multiple mask layer 2A and 2B, to be used for being subsequently formed charge storage structure and channel layer, therefore also be called raceway groove hole 2T. The cross sectional shape being parallel to the raceway groove hole 2T cut on substrate 1 surface can be rectangle, square, the various geometry of rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc. Preferably, raceway groove hole 2T gos deep under substrate 1 surface, namely performs over etching, in order to increases growth area and the degree of depth of subsequently epitaxial growing channel layer or epitaxial layer, improves epitaxial growth quality and mechanical support intensity.
Optionally, epitaxial growth technology is adopted to form epitaxial layer 1E in the bottom of each raceway groove hole 2T. Epitaxy technique can utilize the techniques such as PECVD, HDPCVD, MBE, ALD, UHVCVD, MOCVD, and the lattice paprmeter of epitaxial layer 1E material can be same or like with substrate 1, for instance epitaxial layer 1E material is Si, SiGe, SiC, SiGeC etc. Epitaxial layer 1E will act as the common source district of future device or the channel region of bottom selection transistor. As shown in Figure 3A, the thickness of epitaxial layer 1E is at least above first mask layer 2A and one the second mask layer 2B thickness sum, namely the top of epitaxial layer 1E crosses on the second mask layer 2B top of the bottom, in order to be subsequently formed bottom and select the bottom control gate making to substitute the second mask layer 2B during transistor can cross over the channel region of lifting.
As shown in Figure 3 B, the stacking 2A/2B of the laterally etched mask layer of selectivity, removes the part of the second mask layer 2B that 2T side, raceway groove hole exposes, forms multiple lateral concave 2R. In a preferred embodiment of the invention, adopt the plasma dry etch process of the fluorine-based etching gas of carbon, reducing C:F atomic ratio makes etching tend to isotropism, and further preferably regulate H:F atomic ratio to increase the Etch selectivity between adjacent sublayers, namely the speed etching the first mask layer 2A is substantially zeroed or less than the 5% of the speed etching the second mask layer 2B.In addition, wet etching liquid can also be selected, such as hot phosphoric acid is for silicon nitride, HF acid is for silicon oxide, strong oxidizer (hydrogen peroxide, deionized water ozoniferous) and strong acid (sulphuric acid, nitric acid) mixture are for silicon oxynitride, SiGe etc., TMAH, for the silicon materials of each crystal formation, utilizes chemical property difference between material, each crystal orientation etching speed difference to etch a part of removal the second mask layer 2B targetedly. The shape of the depression 2B ultimately formed is not limited to the rectangle shown in Fig. 3 B, can also be other shapes, such as triangle, rectangle, square, trapezoidal, inverted trapezoidal, Σ shape (multistage broken line is connected), C shape are (more than 1/2 curved surface, curved surface can be disc, ellipsoid, hyperboloid), D-shaped (1/2 curved surface, curved surface can be disc, ellipsoid, hyperboloid) etc.
As shown in Fig. 3 C, 3D, form barrier layer 2D.
In an embodiment of the invention, barrier layer 2D is silicon oxide or high-g value (includes but not limited to AlOx、AlNx、HfOx、HfAlxOy, HfSiON etc.), utilize the techniques such as HDPCVD, MBE, ALD to be conformally deposited on the side of raceway groove hole 2T and the side of bottom and depression 2R, cover multiple first mask layer 2A, multiple second mask layer 2B and epitaxial layer 2E.
Existence due to the 2R that caves in, when barrier layer 2D material differs greatly with the second mask layer 2B material, it is not sufficiently good that barrier layer 2D is likely to step coverage in depression 2R side and the second mask layer 2B interface, in order to improve conformability and the step coverage of barrier layer 2D further, the application forms barrier layer 2D preferably by two-step process shown in Fig. 3 C, 3D in another embodiment.
As shown in Figure 3 C, utilize the adhesion layer 2C of the technique conformal deposited isolation material such as HDPCVD, MBE, ALD, its material is same or like with the second mask layer 2B material, such as the second mask layer 2B is silicon nitride then adhesion layer 2C is silicon nitride, silicon oxynitride, fire sand, but or to be silicon oxynitride N different with O atom ratio.
Subsequently as shown in Figure 3 D, adhesion layer 2C is converted into barrier layer 2D. For example with ISSG (original position steam generates oxidation), FRE--RTO (free radical rapid thermal oxidation), chemical oxidation (such as deionized water ozoniferous or hydrogen peroxide wet treatment, or ozone, oxygen gas plasma dry process) etc. oxidation technology silicon nitride, silicon oxynitride, fire sand are converted to silicon oxide, or adopt nitriding process (in nitrogen containing atmosphere high annealing) that silicon oxide, silicon oxide carbide, silicon oxynitride are converted to silicon nitride. Especially, for improving barrier film quality further, reducing the purpose of conversion process median surface defect, it is preferred to use ISSG performs oxidation technology, thus avoids adhesion layer 2C and the second mask layer 2B interface excessive erosion peel off or break. Barrier layer 2D thinner thickness (such as 1～10nm) that is consequently formed and simultaneously by the sharp corner passivation of depression 2R or sphering, to improve electric field abnormalization in the step coverage of deposition, reduction corner, device reliability can be improved further. Further preferably, the conversion of adhesion layer 2C to barrier layer 2D can be partly, namely the part adhesion layer 2C on surface is converted into barrier layer 2D, and remains remaining part adhesion layer 2C (not shown) and collectively form stop stacked structure to be effectively improved blocking effect and interlayer adhesion force with barrier layer 2D.
Deposition accumulation layer 2E, covers on the 2D of barrier layer subsequently, namely has been partially filled with the sidewall of raceway groove hole 2T, depression 2R.Utilizing the technique conformal deposited accumulation layer 2E such as HDPCVD, MBE, ALD, its material is can at any dielectric material with the interface of barrier layer 2D and the interface storage electric charge with following tunnel layer 4, for instance silicon nitride SiNx, hafnium oxide HfOx, zirconium oxide ZrOx, yittrium oxide YOxOr its combination. As shown in FIGURE 3 E, accumulation layer 2E is continuous distribution at the beginning.
As shown in Fig. 3 E～Fig. 3 G, on accumulation layer 2E, depression 2R forms protective layer 3A. As shown in FIGURE 3 E, in raceway groove hole 2T and depression 2R at least in part (or completely) deposited sacrificial bed course 3A at least to fill depression 2R, it is also possible to stay part raceway groove hole 2T not to be filled with the speed of raising subsequent oxidation/nitriding process. Depositing operation is the conformal technique such as HDPCVD, MBE, ALD, and sacrificing bed course 3A material is polysilicon/germanium, non-crystalline silicon/germanium, microcrystal silicon/germanium or amorphous carbon. Perform oxidation or nitriding process, sacrifice bed course 3A is partially converted into the sacrifice layer 3B of oxide or nitride. Existence due to the 2R that caves in; the sacrifice bed course 3A of depression 2R depths cannot be changed by conversion process completely; therefore also retains partial sacrifice bed course 3A as illustrated in Figure 3 F except the sacrifice layer 3B being converted in depression 2R, this sacrifice bed course 3A will be used for protecting the part accumulation layer 2E of its side. Subsequently as shown in Figure 3 G, etching removes sacrifice layer 3B to expose remaining sacrifice bed course namely protective layer 3A, for instance adopt HF acid for the sacrifice layer 3B of silicon oxide material. As shown in Figure 3 G, multiple protective layer 3A are distributed in multiple depression 2R, cover a part of accumulation layer 2E.
As shown in figure 3h, selective etch removes part accumulation layer 2E, is formed by the separated multiple accumulation layer sections of the first mask layer 2A, barrier layer 2D. Isotropic dry etching or wet etching can be adopted, such as hot phosphoric acid is for the accumulation layer 2E of silicon nitride material, or regulates the etching speed (such as big 5 times, 10 times or even more than 20 times) that etching gas proportioning makes to be noticeably greater than other adjacent materials for the etching speed of accumulation layer 2E. In the process; owing to accumulation layer 2E protected seam 3A part covers; the part accumulation layer 2E therefore suffering from covering will retain; the removal and the remainder exposed is etched; namely make accumulation layer 2E by " pinch off "; thus avoiding the lateral transfer of electric charge between adjacent storage layers 2E, reducing the time dependent drift of threshold voltage, as shown in Figure 4.
As shown in fig. 31, etching removes protective layer 3A. Isotropic dry etching or wet etching can be adopted, for instance TMAH is for the silicon materials of various crystal formations, or oxygen plasma etching removes amorphous carbon etc., is removed completely by the protective layer 3A on each accumulation layer section 2E.
Finally, as shown in figure 3j, in raceway groove hole 2T and depression 2R, tunnel layer 4 is formed. Utilizing the technique conformal deposited tunnel layers 4 such as HDPCVD, MBE, ALD, material includes SiO2Or high-g value, wherein high-g value includes but not limited to that nitride (such as SiN, AlN, TiN, TaN), metal-oxide (are mainly subgroup and lanthanide element oxide, for instance MgO, Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3), nitrogen oxides (such as SiON, HfSiON), Perovskite Phase oxide (such as PbZrxTi1--xO3(PZT)、BaxSr1--xTiO3(BST)) etc., tunnel layer can be single layer structure or the multilayer lamination structure of above-mentioned material.
Hereafter, 3D memory construction is continuously formed.
Such as, the techniques such as MOCVD, MBE, ALD are adopted to be conformally formed the channel layer (all not shown below) being perpendicular to substrate surface and extend in the 2T of raceway groove hole.Channel layer is semiconductor material, equal or close with epitaxial layer 1E lattice paprmeter. Channel layer materials can be selected from IV race element semiconductor, IV compound semiconductor, III--V race or II--VI compound semiconductor, such as Si, Ge, SiGe, SiC, GeC, GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs etc. and combination thereof. The depositional mode of channel layer is be locally filled with the hollow cylindrical that the sidewall of raceway groove hole 2T is formed as having air-gap. In other embodiments that the present invention is not shown, select the depositional mode of channel layer fully or partly to fill raceway groove hole 2T, form core--the shell mechanism filling insulating barrier in solid post, cavity ring or cavity ring. The shape of the horizontal cross-section of channel layer is similar with raceway groove hole 2T and preferably conformal, can be solid rectangle, square, the various geometry of rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc., or for above-mentioned geometry develop obtain hollow ring-type, barrel-like structure (and insulating barrier can be filled inside it). Preferably for hollow column channel layer structure, it is possible to fill dielectric isolation layer further inside channel layer, for instance formed the layer of such as silicon oxide material by techniques such as LPCVD, PECVD, HDPCVD, it is used for supporting, insulating and isolating trenches channel layer 6A.
Hereafter, in channel layer deposited atop drain region. Preferably, adopt (such as with Si close material amorphous Si, polycrystalline Si, SiGe, SiC etc. same or like with channel layer material, to finely tune lattice paprmeter and to improve carrier mobility, thus the driveability of control unit device) material be deposited on the top of raceway groove hole 2T and adulterate and form the drain region of memory device unit transistor. Natural, if channel layer is complete filling of solid construction, then channel layer then constitutes corresponding drain region without extra drain region deposition step in the part of whole top device. In other embodiments of the present invention, drain region can also be metal, metal nitride, metal silicide, for instance the combination of any one or its such as W, WN, WSi, constitutes gold half contact and forms Schottky type device at top.
Form interlayer dielectric layer (ILD, not shown) and etching exposes substrate. ILD can be CVD or the silicon oxide of oxidizing process formation, or spin coating, spraying, the low-k materials that the techniques such as silk screen printing are formed, low-k materials includes but not limited to organic low-k materials (such as containing the organic polymer of aryl or many rings), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer). preferably, cmp planarization ILD. utilizing photoresist mask graph (not shown) to perform anisotropic etch process, successively vertical etch ILD, mask stack 2A/2B, until exposing substrate 1 surface, forming multiple vertical openings (not shown). multiple vertical openings will be around each vertical-channel, for instance each vertical-channel on average has 2～6 vertical openings around periphery. the cross sectional shape of opening can be identical with raceway groove hole 2T. vertical openings will expose the side deviating from channel region of stacking 2A/2B, in order to selective etch removes the second mask layer 2B subsequently.
Selecting isotropic etching technique, selective etch removes the second mask layer 2B. Different according to each sublayer material, it is possible to selective wet etching liquid removes required sublayer isotropically to etch. Specifically, take HF base corrosive liquid for silicon oxide material, adopt hot phosphoric acid corrosion liquid for silicon nitride material, adopt the alkali corrosion liquid such as KOH or TMAH for polysilicon or non-crystalline silicon material. It can in addition contain select oxygen plasma dry etching for the carbon back material such as amorphous carbon, DLC so that O and C reaction forms gas and extracts out. After removing the second mask layer 2B, between the first mask layer 2A, leave multiple groove (not shown) of transverse direction (being parallel to the horizontal direction of substrate surface), for forming control electrode after a while.
Common-source (not shown) is formed subsequently in vertical openings base substrate 1. Such as select ion implantation technology, define multiple common-source bottom self aligned vertical injection substrate 1, and preferably form metal silicide (not shown) further on surface to reduce surface contacted resistance. Metal silicide is NiSi such as2--y、Ni1--xPtxSi2--y、CoSi2--yOr Ni1--xCoxSi2--y, wherein x is all higher than 0 and is all higher than less than 1, y being equal to 0 less than 1. Common source district has different doping types from substrate, forms different carrier path hence for erasable read operation.
Depositional control grid in transverse concave groove. Depositing operation is the conformal film-forming process that step coverage is good, filling rate is high such as HDPCVD, MOCVD, MBE, ALD such as. The control gate material polysilicon that such as (n or p) adulterates, non-crystalline silicon, microcrystal silicon, can also be metal, metal alloy, conductive metal nitride and/or oxide and/or silicide, it can be the single layer structure of these materials, can also be the multiple structure (such as stacking) of these materials, for instance metal is selected from any one or its combination of Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La. Also can doped with elements such as C, F, N, O, B, P, As to regulate work function in control gate. Preferably, control gate is metal_based material.
Finally, device line is completed. Vertical openings is filled the deriving structure forming source region. Such as first CVD or oxide/nitride technique form insulation material layer and anisotropic etching is removed bottom and exposed source electrode and form side wall to avoid the control gate short circuit with bit line, the soruce terminal of metal material is formed subsequently by techniques such as MOCVD, ALD, evaporation, sputterings, its material such as metal, it may include the alloy of the metal simple-substances such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals and the conductive nitride of these metals or conductive oxide. Preferably, cmp planarization lead-out wire is until exposing ILD. Etching ILD is until exposing drain region subsequently, fills the material similar with lead-out wire and forms bit line lead-out wire.
Finally the device section view partial enlarged drawing of realization is as shown in Figure 4, a kind of three-dimensional semiconductor device, and including multiple memory element, each of multiple memory element includes: channel layer (not shown), along the directional spreding being perpendicular to substrate surface; Multiple (the first mask) insulating barrier 2A is alternately laminated along the sidewall of channel layer; Control gate (substitutes the position of the second mask layer 2B) and is folded between adjacent insulating barrier 2A; Gate insulator stack, is distributed between channel layer and control gate, including barrier layer 2D, accumulation layer 2E and tunnel layer 4, and wherein barrier layer 2D and tunnel layer 4 continuous distribution and accumulation layer 2E Disjunct distribution.Further, device also includes drain electrode, is positioned at the top of channel layer; And source electrode, in the substrate between adjacent two memory element of multiple memory element. Described in the material of other each layers and structural feature such as process part, do not repeat them here.
According to three-dimensional semiconductor memory device and the manufacture method thereof of the present invention, the accumulation layer structure separated is utilized to block the path of horizontal proliferation, thus improving data retention characteristics.
Although the present invention being described with reference to one or more exemplary embodiments, those skilled in the art could be aware that and device architecture or method flow are made without departing from the scope of the invention various suitable change and equivalents. Additionally, many amendments that can be adapted to particular condition or material can be made without deviating from the scope of the invention by disclosed instruction. Therefore, the purpose of the present invention does not lie in and is limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will include all embodiments fallen within the scope of the present invention.
Claims (10)
1. a three-dimensional semiconductor device manufacture method, including:
The mask layer forming alternately multiple first, second mask layer composition on substrate is stacking;
Etch mask layer stacking formation raceway groove hole, exposes substrate top, the first and second mask layer sidewalls;
Remove a part for the second mask layer to form depression;
Raceway groove hole and depression are conformally formed barrier layer;
Form accumulation layer over the barrier layer;
Selective etch removes a part for accumulation layer;
Raceway groove hole and depression are conformally formed tunnel layer.
2. three-dimensional semiconductor device manufacture method as claimed in claim 1, wherein, the first mask layer is insulant, and the second mask layer is semi-conducting material or insulant; Preferably, insulant is any one or its combination of silicon nitride, silicon oxide, silicon oxynitride, amorphous carbon, carbonitride of silicium, silicon oxide carbide, boron nitride, aluminium oxide; Preferably, semi-conducting material is silicon, germanium or its combination; Preferably, semi-conducting material is polycrystalline, amorphous, crystallite.
3. three-dimensional semiconductor device manufacture method as claimed in claim 1, wherein, the step forming barrier layer farther includes: be conformally formed adhesion layer in raceway groove hole and depression; Perform oxidation and/or nitriding process, adhesion layer is converted into barrier layer at least partially; Preferably, oxidation technology is ISSG, FRE--RTO, chemical oxidation; Preferably, adhesion layer material is same or like with the second mask layer material.
4. three-dimensional semiconductor device manufacture method as claimed in claim 1, wherein, the step of the part that selective etch removes accumulation layer farther includes: be conformally formed sacrifice bed course in raceway groove hole and depression; Perform oxidation and/or nitriding process, sacrifice backing layer portion is converted into sacrifice layer, accumulation layer in the valley leaves protective layer; Remove sacrifice layer; Selective etch removes a part for accumulation layer, retains the residue accumulation layer covered by protective layer.
5. three-dimensional semiconductor device manufacture method as claimed in claim 1, wherein, before forming depression, form raceway groove hole after farther include: form epitaxial layer at raceway groove hole base substrate Epitaxial growth.
6. three-dimensional semiconductor device manufacture method as claimed in claim 1, wherein, the material of barrier layer and/or tunnel layer is silicon oxide or high-g value; Optionally, accumulation layer material is silicon nitride, hafnium oxide, zirconium oxide, yittrium oxide or its combination.
7. three-dimensional semiconductor device manufacture method as claimed in claim 1, wherein, farther includes step after forming tunnel layer: form channel layer in raceway groove hole and depression; Drain electrode is formed at channel layer top; The stacking formation vertical openings of etch mask layer, exposes remaining second mask layer sidewall and substrate top; Selective etch removes remaining second mask layer, leaves groove; Common source is formed bottom vertical openings; Form control gate in a groove; Form source and drain deriving structure.
8. a three-dimensional semiconductor device, including:
Channel layer, along the directional spreding being perpendicular to substrate surface;
Multiple insulating barriers, alternately laminated along the sidewall of channel layer;
Control gate, is folded between adjacent insulating barrier;
Gate insulator stack, is distributed between channel layer and control gate, including barrier layer, accumulation layer and tunnel layer, and wherein barrier layer and tunnel layer continuous distribution and accumulation layer Disjunct distribution.
9. three-dimensional semiconductor device as claimed in claim 8, wherein, also includes drain electrode, is positioned at the top of channel layer; And source electrode, in the substrate between adjacent two memory element of multiple memory element.
10. three-dimensional semiconductor device as claimed in claim 8, wherein, the material of barrier layer and/or tunnel layer is silicon oxide or high-g value; Optionally, accumulation layer material is silicon nitride, hafnium oxide, zirconium oxide, yittrium oxide or its combination.
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