CN110071113A - Three dimensional nonvolatile memory and its manufacturing method - Google Patents
Three dimensional nonvolatile memory and its manufacturing method Download PDFInfo
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- CN110071113A CN110071113A CN201810063404.3A CN201810063404A CN110071113A CN 110071113 A CN110071113 A CN 110071113A CN 201810063404 A CN201810063404 A CN 201810063404A CN 110071113 A CN110071113 A CN 110071113A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
A kind of three dimensional nonvolatile memory and its manufacturing method.Three dimensional nonvolatile memory includes substrate, charge storing structure, laminated construction and channel layer.Charge storing structure is configured in substrate.Laminated construction is configured at the side of charge storing structure, and including multiple insulating layers, multiple grids, buffer layer and barrier layer.Insulating layer and grid alternately lamination.Buffer layer is configured between each grid and charge storing structure and is configured on the surface of insulating layer.Barrier layer is configured between each grid and buffer layer.The end of grid is protrusion on the direction far from channel layer relative to the end of barrier layer.
Description
Technical field
The invention relates to a kind of memory and its manufacturing methods, and deposit in particular to a kind of three dimensional nonvolatile
Reservoir and its manufacturing method.
Background technique
Non-volatile memory device (e.g., flash memory) is excellent due to having the data for making deposit that will not disappear after a loss of power
Point, therefore become a kind of memory component that personal computer and other electronic equipments are widely used.
The more commonly used flash array of industry includes nor gate (NOR) flash memory and NAND gate (NAND) flash memory at present.Due to
The structure of nand flash memory is that each storage unit is made to be serially connected, and integrated level and area utilization are efficient compared with NOR flash memory, because
The storage density of this nand flash memory is more much higher than the storage density of NOR flash memory.Therefore, nand flash memory has been widely used in
In a variety of electronic products, especially mass data field of storage.
In addition, developing a kind of three-dimensional to further promote the storage density of memory component and integrated level
Nand flash memory.However, carrying out in operating process in current three dimensional NAND flash memory, the interference of storage unit is in three dimensional NAND flash memory
One of main challenge, is especially in the presence of micro residue.
Summary of the invention
The present invention provides a kind of three dimensional nonvolatile memory and its manufacturing method, can eliminate the grid during being operated
Such as electrical connection/electric bridge interference phenomenon between pole.
It is of the invention to propose a kind of three dimensional nonvolatile memory, including substrate, charge storing structure, laminated construction and
Channel layer.Charge storing structure is configured in substrate.Laminated construction is configured at the side of charge storing structure, and including multiple exhausted
Edge layer, multiple grids, buffer layer and barrier layer.Insulating layer and grid alternately lamination.Buffer layer is configured at each grid and electricity
Between lotus memory structure and it is configured on the surface of insulating layer.Barrier layer is configured between each grid and buffer layer.Channel layer is matched
It is placed in the charge storing structure other side.The end of grid is on the direction far from channel layer relative to the end of barrier layer
Protrusion.
In some embodiments of the invention, the end E1 of insulating layer 102a is in the direction perpendicular to channel layer up to grid
The distance of the end E2 of 124a is L1, and the end E1 of insulating layer 102a is in the direction perpendicular to channel layer up to barrier layer 122a's
The distance of end E3 is L2, and 1 < L2/L1 < 2.
In some embodiments of the invention, the first part of above-mentioned buffer layer contacted with barrier layer with a thickness of
T1, the second part of buffer layer not contacted with barrier layer with a thickness of T2, and 0 T1-T2≤30 angstrom <
In some embodiments of the invention, the second part of above-mentioned buffer layer is discontinuous.
In some embodiments of the invention, the atomic concentration of the atom in above-mentioned second part containing the barrier layer
It is smaller than 1 atom %.
In some embodiments of the invention, the material of above-mentioned barrier layer be, for example, titanium, titanium nitride, tantalum, tantalum nitride or
A combination thereof.
In some embodiments of the invention, the material of above-mentioned buffer layer is, for example, the material of high dielectric constant.
The present invention proposes a kind of manufacturing method of three dimensional nonvolatile memory, includes the following steps.In being formed in substrate
Charge storing structure and laminated construction.Charge storing structure is configured on the side wall of laminated construction.Laminated construction includes multiple
Insulating layer, multiple grids, buffer layer and barrier layer.Insulating layer and grid alternately lamination.Buffer layer be configured at each grid with
Between charge storing structure and it is configured on the surface of insulating layer.Barrier layer is configured between each grid and buffer layer.In charge
Channel layer is formed on memory structure.The end of grid is protrusion on the direction far from channel layer relative to the end of barrier layer
's.
In some embodiments of the invention, the end E1 of insulating layer 102a is in the direction perpendicular to channel layer up to grid
The distance of the end E2 of 124a is L1, and the end E1 of insulating layer 102a is in the direction perpendicular to channel layer up to barrier layer 122a's
The distance of end E3 is L2, and 1 < L2/L1 < 2.
In some embodiments of the invention, the first part of above-mentioned buffer layer contacted with barrier layer with a thickness of
T1, the second part of buffer layer not contacted with barrier layer with a thickness of T2, and 0 T1-T2≤30 angstrom <.
In some embodiments of the invention, the second part of above-mentioned buffer layer is discontinuous.
In some embodiments of the invention, the atomic concentration of the atom in above-mentioned second part containing the barrier layer
It is smaller than 1 atom %.
In some embodiments of the invention, the forming method of above-mentioned laminated construction includes the following steps.In in substrate
Form the multiple insulation material layers and multiple sacrificial layers of alternative stacked.Patternized technique is carried out to insulation material layer and sacrificial layer,
To form the first opening.The exposed sacrificial layer of the first opening is removed, is opened with form expose portion charge storing structure second
Mouthful.In forming grid layer on the surface of the first opening and inserting grid layer in the second opening, grid layer includes sequentially forming
Cushioned material layer, barrier material layer with gate material layers.Remove the gate material layers of part, the cushioned material layer of part and
Partial barrier material layer, to form grid, buffer layer and barrier layer.
In some embodiments of the invention, the gate material layers of above-mentioned removal part, the barrier material layer of part and
The method of partial cushioned material layer includes the following steps.The first etching technics is carried out, the gate material layers of part are removed, with sudden and violent
Reveal barrier material layer.The second etching technics is carried out, the barrier material layer of part is removed, to expose cushioned material layer.Carry out third
Etching technics removes the cushioned material layer of part, to form buffer layer.
In some embodiments of the invention, the first above-mentioned etching technics is, for example, to be etched back to technique.
In some embodiments of the invention, the second above-mentioned etching technics is, for example, dry etch process or wet etching
Technique.
In some embodiments of the invention, above-mentioned third etching technics is, for example, alternately dry process and wet
Formula processing.
In some embodiments of the invention, above-mentioned dry process is, for example, corona treatment.
In some embodiments of the invention, above-mentioned wet processed is, for example, to use fluoride solvent as the wet of etching liquid
Formula processing.
Based on above-mentioned, in three dimensional nonvolatile memory proposed by the invention and its manufacturing method, pass through removal portion
Insulating layer between point grid and remove the residual of the ladder in insulating layer simultaneously, therefore can be greatly reduced in and be operated
When grid between interference (e.g. metal residue) and short circuit problem.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Figure 1A, Figure 1B, Figure 1B -1, Fig. 1 C to Fig. 1 I are the system of the three dimensional nonvolatile memory of some embodiments of the invention
Make process sectional view.
Fig. 2 is the top view of Figure 1B.
Fig. 3 is the partial enlarged view of the region A of Fig. 1 I.
Fig. 4 is the partial enlarged view of the region A of another embodiment.
[symbol description]
100: substrate
101,127: laminated construction
102,121: insulation material layer
102a, 117: insulating layer
104: sacrificial layer
106,118: opening
109,111,135,137,139: silicon oxide layer
110,136,138: silicon nitride layer
112: charge storing structure
114: channel layer
115: dielectric layer
116: conductive plugs
120: lateral openings
121: cushioned material layer
121a: buffer layer
122: barrier material layer
122a: barrier layer
123: first part
124: gate material layers
124a: grid
125: second part
126: grid layer
128: insulating layer
130: barrier layer
132: metal layer
A: region
E1, E2, E3: end
L1, L2: length
T1, T2: thickness
Specific embodiment
Figure 1A to Fig. 1 I is the manufacturing process sectional view of the three dimensional nonvolatile memory of some embodiments of the invention.Fig. 2
For the top view of Figure 1B.
Figure 1A is please referred to, in formation laminated construction 101 in substrate 100.Substrate 100 is, for example, silicon base.In some implementations
In example, doped region (e.g., N+ doped region) (not being painted) can be formed in substrate 100 according to design requirement.Laminated construction 101 wraps
Include alternately multiple insulation material layers 102 of lamination and multiple sacrificial layers 104.The material of insulation material layer 102 includes dielectric material
Material, e.g. silica.The material of sacrificial layer 104 is different from insulation material layer 102, and has enough with insulation material layer 102
Etching selection ratio, furthermore there is no particular restriction.In some embodiments, the material of sacrificial layer 104 is, for example, silicon nitride.Absolutely
Edge material layer 102 is, for example, to be formed by carrying out multiple chemical gas-phase deposition with sacrificial layer 104.In laminated construction 101
The number of plies of insulation material layer 102 and sacrificial layer 104 can be greater than 16.However, the present invention is not limited thereto, laminated construction
The number of plies of insulation material layer 102 and sacrificial layer 104 may depend on the design and density of memory device in 101.
Then, laminated construction 101 is performed etching, to form the opening 106 across laminated construction 101.In some implementations
In example, in above-mentioned etching technics, part of substrate 100 is optionally removed, so that opening 106 extends in substrate 100.It opens
Mouth 106 is, for example, hole, as shown in Figure 2.
Referring to Figure 1B and Fig. 2, in formation charge storing structure 112 on the side wall of opening 106.Charge storage
112 covering insulating material layer 102 of structure and sacrificial layer 104.Charge storing structure 112 can be oxide, nitride or its group
It closes.In some embodiments, charge storing structure 112 includes oxidenitride oxide (ONO) composite layer.In an example
Show in embodiment, charge storing structure 112 includes silicon oxide layer 109, silicon nitride layer 110 and silicon oxide layer 111.In some realities
It applies in example, charge storing structure 112 includes oxidenitride oxide-Nitride Oxide (ONONO) composite layer.?
In one illustrative embodiments, charge storing structure 112 includes silicon oxide layer 135, silicon nitride layer 136, silicon oxide layer 137, silicon nitride
Layer 138 and silicon oxide layer 139, as shown in figure ib-i.More specifically, the shape in the form of clearance wall of charge storing structure 112
At in opening 106 side wall on, and expose opening 106 bottom surface substrate 100.
In the present embodiment, the opening 106 in Fig. 2 is array arrangement, however, the present invention is not limited thereto.In some embodiments
In, opening 106 is random alignment, as long as the distance between opening 106 is greater than 100 angstroms.
Then, in formation channel layer 114 on charge storing structure 112.Specifically, the covering of channel layer 114 opening 106
Side on charge storing structure 112, and contacted with the substrate 100 that is exposed of bottom surface of opening 106.In some embodiments
In, channel layer 114 can be used as bit line.The material of channel layer 114 is, for example, semiconductor material, such as polysilicon or DOPOS doped polycrystalline silicon
Deng.It can be doped by doping in situ to be doped, or by ion implantation technology.
Fig. 1 C is please referred to, forms dielectric layer 115 in opening 106.The forming method of dielectric layer 115 is, for example, to utilize chemistry
Vapour deposition process or spin-coating method form the dielectric materials layer (not being painted) for filling up opening 106, then carve to dielectric materials layer
Etching technique, so that the upper surface for being formed by dielectric layer 115 is lower than the top surface of laminated construction 101.
Then, in formation conductive plugs 116 on dielectric layer 115.Conductive plugs 116 are contacted with channel layer 114.Some
In embodiment, the material of conductive plugs 116 is, for example, polysilicon or DOPOS doped polycrystalline silicon.The forming method of conductive plugs 116 is for example
Be be initially formed fill up opening 106 conductor material layer (not being painted), then to conductor material layer carry out chemical mechanical milling tech and/
Or it is etched back to technique, to remove the conductor material layer outside opening 106.
Then, in formation insulating layer 117 on laminated construction 101.Insulating layer 117 covers charge storing structure 112, channel layer
114, conductive plugs 116 and laminated construction 101.In some embodiments, the material of insulating layer 117 be, for example, silica or its
His insulating materials.
Fig. 1 D is please referred to, Patternized technique is carried out to insulating layer 117, insulation material layer 102 and sacrificial layer 104, to be formed
Across the opening (also referred to as irrigation canals and ditches) 118 of insulating layer 117, insulation material layer 102 and sacrificial layer 104.In some embodiments, exist
During carrying out the Patternized technique, part of substrate 100 can be also removed simultaneously, so that opening 118 extends to substrate 100.In addition,
After carrying out Patternized technique to insulation material layer 102, the remainder of insulation material layer 102 forms insulating layer 102a.
Then, the sacrificial layer 104 that opening 118 is exposed is removed, to form the side for exposing Partial charge memory structure 112
To opening 120.The method for removing the sacrificial layer 104 that opening 118 is exposed is, for example, dry etching method or wet etching method.It uses
Etching agent in dry etching method is, for example, NF3、 H2、HBr、O2、N2Or He.Etching liquid used in above-mentioned wet etching method
E.g. phosphoric acid (H3PO4) solution.
Fig. 1 E is please referred to, in formation grid layer 126 on the surface of opening 118 and inserts grid layer in lateral openings 120
126.Grid layer 126 include sequentially form cushioned material layer 121, barrier material layer 122 with gate conductor material layer 124.
In some embodiments, cushioned material layer 121 is formed between barrier material layer 122 and charge storing structure 112 and insulate
On the surface of layer 102a.The material of cushioned material layer 121 is, for example, the material of high dielectric constant of the dielectric constant greater than 7, such as oxygen
Change aluminium (Al2O3)、HfO2、La2O5, transition metal oxide, lanthanide oxide or combinations thereof etc..In some embodiments,
The forming method of cushioned material layer 121 needs good stepcoverage, obtains good film thickness uniformity over the entire structure.Institute
The method of stating is, for example, chemical vapour deposition technique or atomic layer deposition method (ALD).Cushioned material layer 121 can be used to be promoted erasing and
Programming characteristic.The material of barrier material layer 122 be, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or its
Combination.The forming method of barrier material layer 122 is, for example, chemical vapour deposition technique.The material of gate conductor material layer 124 is for example
It is polysilicon, amorphous silicon, tungsten (W), cobalt (Co) aluminium (Al), tungsten silicide (WSix) or cobalt silicide (CoSix).Gate conductor materials
The forming method of layer 124 is, for example, chemical vapour deposition technique.
Please refer to Fig. 1 F to Fig. 1 H, remove the gate conductor material layer 124 of part, the barrier material layer 122 of part and
Partial cushioned material layer 121, to form grid 124a, buffer layer 121a and barrier layer 122a.
In some embodiments, as shown in fig. 1F, the first etching technics is carried out, the gate conductor material layer of part is removed
124, to expose barrier material layer 122.First etching technics, which can be, is etched back to technique, such as wet etching process or dry type are carved
Etching technique.Dry etch process or wet etching process are all feasible.It in some embodiments, can be in plasma system
Lower carry out dry etching, plasma system include inductively coupled plasma (inductively coupled plasma,
ICP), remote plasma, condenser type radio frequency plasma (capacitive coupled plasma, CCP) or electron cyclotron
Resonance Plasma (electron cyclotron resonance, ECR) system.And it can be using e.g. NF3、SF6Or
CF4Fluoride compound.In some embodiments, in the case where wet etching, NH can be applied4OH、H2O2、H2SO4、HNO3
Or acetic acid.In some embodiments, during carrying out the first etching technics, in addition to removing the gate conductor materials in opening 118
Outside layer 124, the gate conductor material layer 124 of part in lateral openings 120 can be also removed.In addition, to gate conductor materials
After layer 124 carries out the first etching technics, the remainder of gate conductor material layer 124 forms grid 124a.In some implementations
In example, grid 124a can be used as wordline.In some embodiments, the end E1 of insulating layer 102a is relative in lateral openings 120
The end E2 of the grid 124a exposed is protrusion.Specifically, the end E1 of insulating layer 102a is relative to grid 124a's
End E2 is protrusion on the direction far from channel layer 114.In the present embodiment, two neighboring grid 124a is by being located at it
Between insulating layer 102a and be isolated, and since insulating layer 102a protrudes from adjacent lateral openings 120 (upper and lower) two
Therefore grid 124a can avoid adjacent grid 124a and be in contact with each other.In the present embodiment, the end E2 of grid 124a has
Substantially planar surface, however, the present invention is not limited thereto.In further embodiments, the end E2 of grid 124a has arc-shaped table
Face.In some embodiments, surface end E2 than grid 124a of the end E2 of grid 124a at 120 centers of close opening
(shown in dotted line) is protruded on the surface close to opening 120 edges (i.e. close to barrier material layer 122).
Then, Fig. 1 G is please referred to, the second etching technics is carried out, the barrier material layer 122 of part is removed, to expose fender
The bed of material 121.Second etching technics is, for example, dry etch process or wet etching process.In some embodiments, the is being carried out
During two etching technics, other than removing the barrier material layer 122 in opening 118, exposure in lateral openings 120 can be also removed
Barrier material layer 122 with the barrier material layer 122 of part between grid 124a and cushioned material layer 121.To potential barrier material
After the bed of material 122 carries out the second etching technics, the remainder of barrier material layer 122 forms barrier layer 122a.In some implementations
In example, the end E2 of the grid 124a exposed in lateral openings 120 is relative to the barrier layer exposed in lateral openings 120
The end E3 of 122a is protrusion.Specifically, the end E2 of grid 124a is relative to the end E3 of barrier layer 122a separate
It is protrusion on the direction of channel layer 114.In the present embodiment, by removing the barrier material layer 122 and even in opening 118
The barrier material layer 122 in lateral openings 120 is removed to the end E2 for being lower than grid 124a, can help to adjacent side opening
The isolation between grid 124a in 120, and reduce ladder residual (stringer) (i.e. gesture between adjacent side opening 120
The residue of barrier material layer).In the present embodiment, the end E3 of barrier layer 122a has substantially planar surface, but the present invention
It is without being limited thereto.In further embodiments, the end E3 of barrier layer 122a has inclined surface.Specifically, barrier layer
The end E3 of 122a has from the point contacted with cushioned material layer 121 to the inclined surface of channel layer 114.
In some embodiments, can by single etching technics come simultaneously remove the gate conductor material layer 124 of part with
And partial barrier material layer 122.
Fig. 1 H is please referred to, third etching technics is carried out, removes the cushioned material layer 121 of part exposed, it is slow to be formed
Rush layer 121a.In some embodiments, third etching technics can be alternately dry process and wet processed.At dry type
Reason e.g. corona treatment.In some embodiments, dry process, plasma can be carried out under plasma system
System includes inductively coupled plasma (inductively coupled plasma, ICP), remote plasma, condenser type
Radio frequency plasma (capacitive coupled plasma, CCP) or Ecr plasma (electron
Cyclotron resonance, ECR) system.In some embodiments, can be used oxidizing gas, inert gas or combinations thereof into
Row corona treatment.Oxidizing gas can hardly be with semiconductor material to react with grid material generation.Oxidizing gas is for example
It is oxygen, inert gas.Inert gas is, for example, nitrogen, Krypton or argon gas.In some embodiments, wet processed is, for example, and makes
With fluoride solvent as the wet processed of etching liquid, e.g. diluted hydrofluoric acid (diluted hydrofluoric acid,
DHF) or buffer silicon oxide etching agent (buffered oxide etch, BOE), however, the present invention is not limited thereto, it is possible to use its
His etching liquid carries out wet processed.In some embodiments, during carrying out third etching technics, in addition to removing opening 118
On part cushioned material layer 121 outside, can also remove in part lateral openings 120 cushioned material layer 121 of exposure.Specifically
For, after carrying out dry process to the cushioned material layer 121 exposed, cushioned material layer 121 after dry process
Surface becomes looser or amorphous compared to not plasma-treated cushioned material layer 121.Then, at through dry type
Cushioned material layer 121 after reason carries out wet processed, to remove the cushioned material layer 121 of part.
Especially it is noted that in the known technique for avoiding interfering between grid, although the gesture between grid can be removed
Barrier material layer has a small amount of rank to reduce the residual of the ladder between neighboring gates (i.e. the residue of barrier material layer)
Ladder residual is embedded in the surface of cushioned material layer contacted with barrier material layer.Above-mentioned ladder residual can omission path easy to form
(leakage path) with grid bridge (gate bridge), and then cause the problem of interference between grid and short circuit.
However, in the present invention, by carrying out third etching technics to the cushioned material layer exposed, to remove the padded coaming of part
Layer, while removing the ladder residual being located in cushioned material layer.
In some embodiments, repeat what alternately dry process and wet processed until remove completely was exposed
Ladder in cushioned material layer 121 remains (stringer).In addition, carrying out third quarter to the cushioned material layer 121 exposed
After etching technique, the remainder of cushioned material layer 121 forms buffer layer 121a.In some embodiments, each time alternately into
Grid 124a, barrier layer 122a, the buffer layer 121a of the amount greater than 1 angstrom can be removed in row dry process and wet processed.
In some embodiments, as shown in fig. 1H, to the cushioned material layer 121 that is exposed carry out third etching technics it
Afterwards, buffer layer 121a is formed by still continuously to be covered on the surface of insulating layer 102a.In some embodiments, to it is sudden and violent
After the cushioned material layer 121 of dew carries out third etching technics, it is formed by buffer layer 121a and is discontinuously covered on insulating layer
On the surface of 102a.In further embodiments, after carrying out third etching technics to the cushioned material layer 121 exposed,
It is formed by the corner (not being painted) of buffer layer 121a exposure insulating layer 102a, can be blocked between metal/metal oxide whereby
Entity connect (physical connection).
Fig. 1 I is please referred to, the side wall of covering opening 118 is formed and fills the insulating layer 128 of lateral openings 120.Some
In embodiment, the material of insulating layer 128 is, for example, silica.The method for forming insulating layer 128 is, for example, chemical vapour deposition technique
Or atomic layer deposition method (ALD).Then, technique is performed etching to remove the insulating layer 128 for the bottom for being located at opening 118.One
In a little embodiments, after performing etching technique to insulating layer 128, the substrate 100 of part can be selectively removed.In opening
Barrier layer 130 and metal layer 132 are sequentially inserted in 118.The material of barrier layer 130 be, for example, titanium (Ti), titanium nitride (TiN),
Tantalum (Ta), tantalum nitride (TaN) or combinations thereof.The method for forming barrier layer 130 is, for example, chemical vapour deposition technique.Metal layer 132
Material be, for example, tungsten (W), polysilicon, cobalt, tungsten silicide (WSix) or cobalt silicide (CoSix).Form the method example of metal layer 132
Chemical vapour deposition technique in this way.In some embodiments, metal layer 132 can be used as shared source electrode line (common source
line).So far, the production of three dimensional nonvolatile memory of the invention is completed.
Hereinafter, I referring to Fig.1 to be illustrated to the structure of three dimensional nonvolatile memory of the invention.In addition, the three of the present embodiment
The manufacturing method of dimension nonvolatile memory be although in the above way for be illustrated, three-dimensional of the invention is non-volatile
The forming method of property memory is not limited thereto.Fig. 3 is the partial enlarged view of the region A of Fig. 1 I.Fig. 4 is another embodiment
Region A partial enlarged view.
Please refer to Fig. 1 I, Fig. 3 and Fig. 4, three dimensional nonvolatile memory include substrate 100, charge storing structure 112,
Laminated construction 127 and channel layer 114.Laminated construction 127 and charge storing structure 112 configure in substrate 100, and laminated construction
127 are configured at the side of charge storing structure 112.Laminated construction 127 includes multiple insulating layer 102a, multiple grid 124a, delays
Rush layer 121a and barrier layer 122a.Insulating layer 102a and grid 124a alternately lamination.Buffer layer 121a is configured at each grid
Between 124a and charge storing structure 112 and it is configured on the surface of insulating layer 102a.Barrier layer 122a is configured at each grid
Between 124a and buffer layer 121a.Channel layer 114 is configured on charge storing structure 112.
In some embodiments, the end E2 of grid 124a is relative to the end E3 of barrier layer 122a far from channel layer
It is protrusion on 114 direction.In some embodiments, the end E1 of insulating layer 102a the direction perpendicular to channel layer up to
The distance of the end E2 of grid 124a is L1, and the end E1 of insulating layer 102a is in the direction perpendicular to channel layer up to barrier layer
The distance of the end E3 of 122a is L2, and 1 < L2/L1 < 2.In some embodiments, 50 angstroms of 400 angstroms of < L2-L1 <.Some
In embodiment, L1 is generally higher than 50 angstroms.In further embodiments, the end E3 of barrier layer 122a has inclined surface.Tool
For body, the end E3 of barrier layer 122a has from the point contacted with cushioned material layer 121 to the inclined table of channel layer 114
Face, as shown in Figure 4.In the case, the end E1 of insulating layer 102a the direction perpendicular to channel layer up to end E3 with
The distance for the point that cushioned material layer 121 contacts is L2.
In some embodiments, buffer layer 121a include the first part 123 contacted with barrier layer 122a and not with gesture
The second part 125 of barrier layer 122a contact, wherein the first part 123 of buffer layer 121a with a thickness of T1, buffer layer 121a's
Second part 125 with a thickness of T2, and 0 T1-T2≤30 angstrom <.In some embodiments, the second part of buffer layer 121a
125 be discontinuous.Specifically, the corner (not being painted) of the exposure of the second part 125 insulating layer 102a of buffer layer 121a, by
This can block the entity between metal/metal oxide to connect (physical connection).
In some embodiments, the atom of the atom containing buffer layer 121a is dense in the second part 125 of buffer layer 121a
Degree is less than 1 atom %.
In some embodiments, three dimensional nonvolatile memory can further include dielectric layer 115 and conductive plugs 116.It is situated between
Electric layer 115 is located at the lower part of opening 106, and channel layer 114 is around dielectric layer 115.Conductive plugs 116 are located at the upper of opening 106
It portion and is contacted with channel layer 114.
In conclusion in the three dimensional nonvolatile memory and its manufacturing method of above-described embodiment, by removing part
Insulating layer between grid and remove the residual of the ladder in insulating layer simultaneously, therefore can improve when being operated grid it
Between interference and short circuit problem.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the invention
Protection scope, which is worked as, is subject to what claim was defined.
Claims (10)
1. a kind of three dimensional nonvolatile memory, comprising:
Substrate；
Charge storing structure is configured in the substrate；
Laminated construction, is configured at the side of the charge storing structure, and includes:
Multiple insulating layers and multiple grids, wherein the insulating layer and the grid alternately lamination；
Buffer layer is configured between each grid and the charge storing structure and is configured on the surface of the insulating layer；And
Barrier layer is configured between each grid and the buffer layer；And
Channel layer is configured at the charge storing structure other side,
Wherein the end of the grid is protrusion on the direction far from the channel layer relative to the end of the barrier layer.
2. three dimensional nonvolatile memory as described in claim 1, wherein the end of the insulating layer is perpendicular to channel layer
Direction up to the end of the grid distance be L1, the end of the insulating layer is in the direction perpendicular to channel layer up to institute
The distance of the end of barrier layer is stated as L2, and 1 < L2/L1 < 2.
3. three dimensional nonvolatile memory as described in claim 1, wherein the buffer layer is contacted with the barrier layer
First part with a thickness of T1, the second part of the buffer layer not contacted with the barrier layer with a thickness of T2, and 0 <
T1-T2≤30 angstrom.
4. three dimensional nonvolatile memory as claimed in claim 3, wherein the second part of the buffer layer is not connect
Continuous.
5. three dimensional nonvolatile memory as described in claim 1, wherein the material of the barrier layer include titanium, titanium nitride,
Tantalum, tantalum nitride or combinations thereof.
6. three dimensional nonvolatile memory as described in claim 1, wherein the material of the buffer layer is that dielectric constant is greater than 7
High dielectric constant material.
7. a kind of manufacturing method of three dimensional nonvolatile memory, comprising:
The laminated construction is configured in formation charge storing structure and laminated construction, the charge storing structure in substrate
On side wall, wherein the lamination packs include:
Multiple insulating layers and multiple grids, wherein the insulating layer and the grid alternately lamination；
Buffer layer is configured between each grid and the charge storing structure and is configured on the surface of the insulating layer；And
Barrier layer configures between each grid and the buffer layer；And
In forming channel layer on the charge storing structure,
Wherein the end of the grid is protrusion on the direction far from the channel layer relative to the end of the barrier layer.
8. the manufacturing method of three dimensional nonvolatile memory as claimed in claim 7, wherein the end of the insulating layer is being hung down
Directly in the direction of channel layer, the distance up to the end of the grid is L1, and the end of the insulating layer is perpendicular to channel layer
Distance of the direction up to the end of the barrier layer is L2, and 1 < L2/L1 < 2.
9. the manufacturing method of three dimensional nonvolatile memory as claimed in claim 7, wherein the buffer layer with the gesture
The first part of barrier layer contact with a thickness of T1, the second part of the buffer layer not contacted with the barrier layer with a thickness of
T2, and 0 angstrom of T1-T2≤30 angstrom <.
10. the manufacturing method of three dimensional nonvolatile memory as claimed in claim 9, wherein described the second of the buffer layer
Part is discontinuous.
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| US20150243675A1 (en) * | 2014-02-24 | 2015-08-27 | Tai-Soo Lim | Semiconductor memory device and method of fabricating the same |
| CN105679761A (en) * | 2016-01-26 | 2016-06-15 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and production method of three-dimensional semiconductor device |
| US20170148806A1 (en) * | 2015-11-19 | 2017-05-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| CN107017261A (en) * | 2015-11-02 | 2017-08-04 | 三星电子株式会社 | Semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150243675A1 (en) * | 2014-02-24 | 2015-08-27 | Tai-Soo Lim | Semiconductor memory device and method of fabricating the same |
| CN107017261A (en) * | 2015-11-02 | 2017-08-04 | 三星电子株式会社 | Semiconductor devices |
| US20170148806A1 (en) * | 2015-11-19 | 2017-05-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| CN105679761A (en) * | 2016-01-26 | 2016-06-15 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and production method of three-dimensional semiconductor device |
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