TWI464884B - Semiconductor device and method for manufacturing thereof - Google Patents
Semiconductor device and method for manufacturing thereof Download PDFInfo
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- TWI464884B TWI464884B TW097133387A TW97133387A TWI464884B TW I464884 B TWI464884 B TW I464884B TW 097133387 A TW097133387 A TW 097133387A TW 97133387 A TW97133387 A TW 97133387A TW I464884 B TWI464884 B TW I464884B
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- 239000004065 semiconductor Substances 0.000 title claims description 60
- 238000000034 method Methods 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000003860 storage Methods 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 10
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 8
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 8
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 75
- 230000008569 process Effects 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 9
- 238000009413 insulation Methods 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 4
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Description
本發明係關於半導體裝置和製造該半導體裝置之方法，且詳言之，係關於提供有非揮發性記憶體之半導體裝置和製造該半導體裝置之方法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device provided with a non-volatile memory and a method of fabricating the same.
最近，已廣泛使用一種其為半導體裝置、能夠於關斷電源後保持住資料之非揮發性記憶體。於由非揮發性記憶體所表示之快閃記憶體中，形成記憶體胞(memory cell)之電晶體具有浮置閘極或稱之為電荷儲存層用於儲存電荷至記錄資料之絕緣膜。具有絕緣膜作為電荷儲存層之快閃記憶體包含SONOS(矽化物氧化物氮化物氧化物矽化物)結構用來儲存電荷於ONO膜(氧化物膜/氮化物膜/氧化物膜)內部之陷捕層(trap layer)。美國專利第6,011,725號揭示一種類型之SONOS快閃記憶體，也就是，具有虛擬接地類型記憶體胞之快閃記憶體，該記憶體胞以對稱方式操作可交換之源極和汲極。Recently, a non-volatile memory which is a semiconductor device capable of holding data after the power is turned off has been widely used. In a flash memory represented by a non-volatile memory, a transistor forming a memory cell has a floating gate or an insulating film called a charge storage layer for storing charges to record data. A flash memory having an insulating film as a charge storage layer contains a SONOS (methane oxide oxide nitride oxide) structure for storing charges in an ONO film (oxide film/nitride film/oxide film) Traps layer. U.S. Patent No. 6,011,725 discloses a type of SONOS flash memory, i.e., a flash memory having a virtual ground type memory cell that operates the exchangeable source and drain in a symmetrical manner.
日本專利申請公報第2000－004014和2004－343014號揭示一種具有電荷儲存層部分形成於閘極電極下方區域上之技術。Japanese Patent Application Publication Nos. 2000-004014 and 2004-343014 disclose a technique in which a portion of a charge storage layer is formed on a region below a gate electrode.
於美國專利第6,011,725號中，二位元資料能儲存於單一記憶體胞中。當記憶體胞最小化時，二位元資料之間之干擾更可能發生。電荷儲存層被分離用來分別儲存二個位元以便抑制干擾。然而，不容易製造在閘極電極下方具 有電荷儲存層被分為二段之半導體裝置。In U.S. Patent No. 6,011,725, the binary data can be stored in a single memory cell. When memory cells are minimized, interference between binary data is more likely to occur. The charge storage layer is separated to store two bits separately to suppress interference. However, it is not easy to manufacture under the gate electrode A semiconductor device having a charge storage layer is divided into two stages.
本發明提供一種在閘極電極下方具有分離之電荷儲存層之半導體裝置，以及一種用來容易製造該半導體裝置之方法。The present invention provides a semiconductor device having a separate charge storage layer under a gate electrode, and a method for easily fabricating the semiconductor device.
根據本發明之一態樣，提供一種半導體裝置，其包含閘極電極，設在半導體基板之上方；閘極絕緣膜，設在該半導體基板上而在該閘極電極中央之下方；第一絕緣膜，設置從該閘極絕緣膜上方區域至該閘電極之二端下方之區域，且其由與該閘極絕緣膜之材料不同之材料形成；隧道絕緣膜，形成在該半導體基板上於該閘極絕緣膜之二端處；以及電荷儲存層，插置於該隧道絕緣膜和該第一絕緣膜之間。根據本發明，能夠容易製造在閘極電極下方具有分離之電荷儲存層之半導體裝置，以及能夠個別設定第一絕緣膜和隧道絕緣膜之各膜的厚度。According to an aspect of the present invention, a semiconductor device includes a gate electrode disposed above a semiconductor substrate, and a gate insulating film disposed on the semiconductor substrate below a center of the gate electrode; a film disposed from a region above the gate insulating film to a region below the two ends of the gate electrode, and formed of a material different from a material of the gate insulating film; a tunnel insulating film formed on the semiconductor substrate The two ends of the gate insulating film; and a charge storage layer interposed between the tunnel insulating film and the first insulating film. According to the present invention, it is possible to easily manufacture a semiconductor device having a separate charge storage layer under the gate electrode, and to individually set the thickness of each of the first insulating film and the tunnel insulating film.
根據本發明之另一態樣，提供一種用於製造半導體裝置之方法，該方法包含下列步驟：在半導體基板上形成閘極絕緣膜；在該閘極絕緣膜上形成第一絕緣膜；在該第一絕緣膜上形成閘極電極；選擇性地去除該閘極電極、該第一絕緣膜和該閘極絕緣膜，該閘極電極、該第一絕緣膜和該閘極絕緣膜係疊層以允許該閘極電極和該第一絕緣膜被各向異性地蝕刻，和該閘極絕緣膜被側面蝕刻；於半導體基板上該閘極絕緣膜被側面蝕刻的區域上形成隧道絕緣膜；以及在該隧道絕緣膜上形成電荷儲存層。根據本發明， 能夠容易製造在閘極電極下方具有分離之電荷儲存層之半導體裝置，以及能夠個別設定第一絕緣膜和隧道絕緣膜之各膜的厚度。According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, the method comprising the steps of: forming a gate insulating film on a semiconductor substrate; forming a first insulating film on the gate insulating film; Forming a gate electrode on the first insulating film; selectively removing the gate electrode, the first insulating film and the gate insulating film, and stacking the gate electrode, the first insulating film and the gate insulating film The gate electrode and the first insulating film are allowed to be anisotropically etched, and the gate insulating film is etched sideways; a tunnel insulating film is formed on a region of the semiconductor substrate where the gate insulating film is etched sideways; A charge storage layer is formed on the tunnel insulating film. According to the present invention, It is possible to easily manufacture a semiconductor device having a separate charge storage layer under the gate electrode, and to individually set the thickness of each of the first insulating film and the tunnel insulating film.
第1圖為根據比較的範例和第一至第三實施例之快閃記憶體之平面圖。作為擴散區30之位元線延伸於矽基板10之內側。字元線34延伸相交於半導體基板10上之擴散區30。擴散區30之間之半導體基板10用作為通道區44，在其上形成電荷儲存層26。參照第1圖，顯示電荷儲存層26穿過字元線34，如影線區所示。電荷儲存層26形成在字元線34之延伸方向於通道區44上之E1和E2端。當電荷儲存層26彼此分離，則儲存於單一記憶體胞中之二個位元之間之干擾被抑制。電荷儲存層26可以連續地形成於擴散區30之延伸方向。Fig. 1 is a plan view of a flash memory according to a comparative example and first to third embodiments. A bit line as the diffusion region 30 extends inside the ruthenium substrate 10. The word line 34 extends across the diffusion region 30 on the semiconductor substrate 10. The semiconductor substrate 10 between the diffusion regions 30 serves as a channel region 44 on which the charge storage layer 26 is formed. Referring to Figure 1, charge storage layer 26 is shown passing through word line 34 as shown in the hatched area. The charge storage layer 26 is formed at the E1 and E2 ends of the channel region 44 in the direction in which the word lines 34 extend. When the charge storage layers 26 are separated from each other, the interference between the two bits stored in the single memory cell is suppressed. The charge storage layer 26 may be continuously formed in the extending direction of the diffusion region 30.
接著，將說明根據比較的範例製造半導體裝置之方法。第2A至3C圖之各圖對應沿著第1圖中所示線A－A之剖面圖。參照第2A圖，閘極絕緣膜12形成於半導體基板10上，以及假層(dummy layer)36進一步形成在閘極絕緣膜12上。假層36和閘極絕緣膜12之預定區域被蝕刻。參照第2B圖，閘極絕緣膜12受到從假層36之二端之側面蝕刻以形成底切部(undercut portion)18。參照第2C圖，絕緣膜20分別形成在閘極絕緣膜12之側面、半導體基板10之上表面、和假層36之下表面上。於半導體基板10上之絕緣膜20變成隧道絕緣膜21，而假層36下方之絕緣膜 20變成第二絕緣膜23。Next, a method of manufacturing a semiconductor device according to a comparative example will be explained. Each of Figs. 2A to 3C corresponds to a cross-sectional view taken along line A-A shown in Fig. 1. Referring to FIG. 2A, a gate insulating film 12 is formed on the semiconductor substrate 10, and a dummy layer 36 is further formed on the gate insulating film 12. The predetermined area of the dummy layer 36 and the gate insulating film 12 is etched. Referring to FIG. 2B, the gate insulating film 12 is etched from the side of both ends of the dummy layer 36 to form an undercut portion 18. Referring to FIG. 2C, the insulating film 20 is formed on the side surface of the gate insulating film 12, the upper surface of the semiconductor substrate 10, and the lower surface of the dummy layer 36, respectively. The insulating film 20 on the semiconductor substrate 10 becomes the tunnel insulating film 21, and the insulating film under the dummy layer 36 20 becomes the second insulating film 23.
參照第3A圖，電荷儲存層26形成於第二絕緣膜23和隧道絕緣膜21之間。擴散層30使用假層36作為遮罩，形成於半導體基板10之內側。形成絕緣層32以覆蓋假層36，該絕緣層32被研磨直到假層36之上表面被暴露為止。參照第3B圖，去除假層36。第一絕緣膜38形成於該閘極絕緣膜12、第二絕緣膜23、和絕緣層32上。上絕緣膜(top insulating film)40係由第一絕緣膜38和第二絕緣膜23形成。參照第3C圖，亦用作為閘極電極之字元線34形成於第一絕緣膜38上。於此種方法，產生根據比較的範例之半導體裝置。Referring to FIG. 3A, a charge storage layer 26 is formed between the second insulating film 23 and the tunnel insulating film 21. The diffusion layer 30 is formed on the inner side of the semiconductor substrate 10 using the dummy layer 36 as a mask. An insulating layer 32 is formed to cover the dummy layer 36, which is ground until the upper surface of the dummy layer 36 is exposed. Referring to Figure 3B, the dummy layer 36 is removed. The first insulating film 38 is formed on the gate insulating film 12, the second insulating film 23, and the insulating layer 32. A top insulating film 40 is formed of a first insulating film 38 and a second insulating film 23. Referring to Fig. 3C, a word line 34 as a gate electrode is also formed on the first insulating film 38. In this way, a semiconductor device according to a comparative example is produced.
於比較的範例中，二個電荷儲存層26形成於閘極電極之下方。然而，使用假層36使製造步驟複雜化。假層36用來形成要較隧道絕緣膜21為厚的上絕緣膜40。當隧道絕緣膜21和第二絕緣膜23使用如第2C圖中所示之底切部18形成時，隧道絕緣膜21具有與第二絕緣膜23實質相同的厚度。因此，如第3B圖所示，於去除假層36之後，第一絕緣膜38形成於第二絕緣膜23上，以及上絕緣膜40由第一絕緣膜38和第二絕緣膜23形成。結果，上絕緣膜40能夠製得較隧道絕緣膜21為厚。In the comparative example, two charge storage layers 26 are formed below the gate electrode. However, the use of the dummy layer 36 complicates the manufacturing steps. The dummy layer 36 is used to form an upper insulating film 40 which is thicker than the tunnel insulating film 21. When the tunnel insulating film 21 and the second insulating film 23 are formed using the undercut portion 18 as shown in FIG. 2C, the tunnel insulating film 21 has substantially the same thickness as the second insulating film 23. Therefore, as shown in FIG. 3B, after the dummy layer 36 is removed, the first insulating film 38 is formed on the second insulating film 23, and the upper insulating film 40 is formed of the first insulating film 38 and the second insulating film 23. As a result, the upper insulating film 40 can be made thicker than the tunnel insulating film 21.
上絕緣膜40製得較隧道絕緣膜21為厚係基於下列理由：要求薄的隧道絕緣膜21是為了儲存或去除施加於電荷儲存層26和通道區44之間電流之電荷(電子)。同時，要求上絕緣膜40之厚度要厚係為了維持電荷儲存層26之電 荷保持性。也就是說，要求上絕緣膜40要厚是為了當去除電荷時能抑制電荷從閘極電極16遷移至電荷儲存層26。這是為什麼上絕緣膜40要製得較隧道絕緣膜21為厚的原因。The upper insulating film 40 is made thicker than the tunnel insulating film 21 for the following reason: The thin tunnel insulating film 21 is required to store or remove charges (electrons) applied to the current between the charge storage layer 26 and the channel region 44. At the same time, the thickness of the upper insulating film 40 is required to be thick in order to maintain the electric charge of the charge storage layer 26. Load retention. That is, the upper insulating film 40 is required to be thick in order to suppress migration of charges from the gate electrode 16 to the charge storage layer 26 when the charge is removed. This is why the upper insulating film 40 is made thicker than the tunnel insulating film 21.
第1圖顯示在閘極電極下方具有分離之電荷儲存層26之半導體裝置，該閘極電極透過簡單的製程而產生，該製程使得各隧道絕緣膜21和上絕緣膜40具有最佳的厚度而不須使用假層36。1 shows a semiconductor device having a separate charge storage layer 26 under the gate electrode, the gate electrode being produced by a simple process which allows each of the tunnel insulating film 21 and the upper insulating film 40 to have an optimum thickness. It is not necessary to use the dummy layer 36.
參照第4A至7B圖，將說明根據第一實施例製造該半導體裝置之方法。第4A至6圖為對應分別沿著第1圖中所示線A－A和B－B之剖面圖。第7A圖為對應沿著第1圖中所示線A－A之剖面之圖式，第7B圖為對應沿著第1圖中所示線B－B之剖面之圖式。Referring to Figures 4A to 7B, a method of manufacturing the semiconductor device according to the first embodiment will be explained. 4A to 6 are cross-sectional views corresponding to the lines A-A and B-B shown in Fig. 1, respectively. Fig. 7A is a view corresponding to a cross section taken along line A-A shown in Fig. 1, and Fig. 7B is a view corresponding to a cross section taken along line B-B shown in Fig. 1.
參照第4A圖，二氧化矽膜形成之閘極絕緣膜12透過熱氧化製程形成於P型矽半導體基板10上(或矽半導體基板中之P型區中)。由氧化鋁形成之第一絕緣膜14透過原子層沉積(Atomic Layer Deposition,ALD)製程形成於閘極絕緣膜12上。由多晶矽形成之閘極電極16透過化學氣相沉積(Chemical Vapor Deposition,CVD)製程形成於第一絕緣膜14上。閘極絕緣膜12、第一絕緣膜14、和閘極電極16之厚度可分別設定至20nm、10nm、和150nm。參照第4B圖，閘極電極16、第一絕緣膜14、和閘極絕緣膜12經受到各向異性蝕刻(anisotropic etching)被去除以便形成 延伸於位元線方向之條狀圖案(stripe pattern)。參照第4C圖，閘極絕緣膜12使用例如氟化酸水溶液經受到側面蝕刻。因此，其為側面蝕刻區之底切部18形成於閘極電極16之下方。Referring to FIG. 4A, a gate insulating film 12 formed of a hafnium oxide film is formed on a P-type germanium semiconductor substrate 10 (or a P-type region in a germanium semiconductor substrate) through a thermal oxidation process. The first insulating film 14 formed of aluminum oxide is formed on the gate insulating film 12 by an Atomic Layer Deposition (ALD) process. The gate electrode 16 formed of polysilicon is formed on the first insulating film 14 by a chemical vapor deposition (CVD) process. The thickness of the gate insulating film 12, the first insulating film 14, and the gate electrode 16 can be set to 20 nm, 10 nm, and 150 nm, respectively. Referring to FIG. 4B, the gate electrode 16, the first insulating film 14, and the gate insulating film 12 are removed by anisotropic etching to form A stripe pattern extending in the direction of the bit line. Referring to Fig. 4C, the gate insulating film 12 is subjected to side etching using, for example, an aqueous solution of a fluorinated acid. Therefore, the undercut portion 18, which is a side etching region, is formed under the gate electrode 16.
參照第5A圖，透過ALD製程形成由氧化鋁形成之絕緣膜20，以覆蓋底切部18之內表面(也就是說，在半導體基板10上和第一絕緣膜14下方之底切部18，和閘極絕緣膜12之側表面之區域)和閘極電極16。絕緣膜20之厚度可以設定至5nm。在半導體基板10上底切部18之區域上之絕緣膜20變成隧道絕緣膜21。在第一絕緣膜14下方在底切部18之區域上之絕緣膜20變成第二絕緣膜22。第一絕緣膜14和第二絕緣膜22形成上絕緣膜24。參照第5B圖，由氧化鉿(hafnium oxide)形成之電荷儲存層26透過ALD製程而形成，以便填滿底切部18和覆蓋該絕緣膜20。結果，包含隧道絕緣膜21、電荷儲存層26、和上絕緣膜24之疊層(laminated layer)28形成於底切部18之內側。參照第5C圖，使用閘極電極16作為遮罩而蝕刻電荷儲存層26和絕緣膜20。Referring to FIG. 5A, an insulating film 20 formed of aluminum oxide is formed through an ALD process to cover an inner surface of the undercut portion 18 (that is, an undercut portion 18 on the semiconductor substrate 10 and below the first insulating film 14, And a region of the side surface of the gate insulating film 12) and the gate electrode 16. The thickness of the insulating film 20 can be set to 5 nm. The insulating film 20 on the region of the undercut portion 18 on the semiconductor substrate 10 becomes the tunnel insulating film 21. The insulating film 20 on the region of the undercut portion 18 under the first insulating film 14 becomes the second insulating film 22. The first insulating film 14 and the second insulating film 22 form an upper insulating film 24. Referring to FIG. 5B, a charge storage layer 26 formed of hafnium oxide is formed through an ALD process to fill the undercut portion 18 and cover the insulating film 20. As a result, a laminated layer 28 including the tunnel insulating film 21, the charge storage layer 26, and the upper insulating film 24 is formed inside the undercut portion 18. Referring to FIG. 5C, the charge storage layer 26 and the insulating film 20 are etched using the gate electrode 16 as a mask.
參照第6圖，砷離子係使用閘極電極16作為遮罩而植入於半導體基板10中，以形成為N型擴散區30之位元線。形成由氧化矽形成之絕緣層32，以覆蓋擴散區30和閘極電極16之上表面。透過化學機械研磨(Chemical Mechanical Polish，CMP)製程該絕緣層32被研磨以暴露該閘極電極16。此使得可能平坦化閘極電極16和絕緣層32之上表面。Referring to Fig. 6, arsenic ions are implanted in the semiconductor substrate 10 using the gate electrode 16 as a mask to form a bit line of the N-type diffusion region 30. An insulating layer 32 formed of yttrium oxide is formed to cover the diffusion region 30 and the upper surface of the gate electrode 16. The insulating layer 32 is ground to expose the gate electrode 16 by a chemical mechanical polishing (CMP) process. This makes it possible to planarize the upper surface of the gate electrode 16 and the insulating layer 32.
參照第7A和7B圖，多晶矽層形成在閘極電極16和絕緣層32上。參照第7B圖，去除對應於預期形成於字元線之間區域(第1圖中所示線B－B)之多晶矽層和閘極電極16。參照第7A圖，多晶矽層存在於預期形成為字元線之區域，並與閘極電極16電性耦接。結果，形成與擴散區30相交之字元線34。其後，形成層間(inter－layer)絕緣膜、插塞金屬(plug metal)、接線層等，以產生根據第一實施例之半導體裝置。Referring to Figures 7A and 7B, a polysilicon layer is formed on the gate electrode 16 and the insulating layer 32. Referring to Fig. 7B, the polysilicon layer and the gate electrode 16 corresponding to the region (line B-B shown in Fig. 1) expected to be formed between the word lines are removed. Referring to FIG. 7A, a polysilicon layer exists in a region expected to be formed as a word line, and is electrically coupled to the gate electrode 16. As a result, a word line 34 intersecting the diffusion region 30 is formed. Thereafter, an inter-layer insulating film, a plug metal, a wiring layer, or the like is formed to produce the semiconductor device according to the first embodiment.
參照第4A圖，閘極絕緣膜12和第一絕緣膜14用不同的材料形成。參照第4C圖，取決於閘極絕緣膜12之側面蝕刻，使用蝕刻該閘極絕緣膜12但是幾乎不蝕刻第一絕緣膜14之化學物品。於該閘極絕緣膜12由氧化矽膜形成，而該第一絕緣膜14由氧化鋁膜形成之狀況中，氟化酸水溶液用來側面蝕刻閘極絕緣膜12。於上述步驟中，蝕刻如第4B圖中實施，使得閘極電極16和第一絕緣膜14以各向異性方式蝕刻。如第4C圖中之蝕刻允許閘極絕緣膜12使用閘極電極16作為遮罩而被選擇性方式側面蝕刻。於此方法中，疊置之閘極電極16、第一絕緣膜14和閘極絕緣膜12被選擇性地去除。Referring to Fig. 4A, the gate insulating film 12 and the first insulating film 14 are formed of different materials. Referring to FIG. 4C, depending on the side etching of the gate insulating film 12, the chemical which etches the gate insulating film 12 but hardly etches the first insulating film 14 is used. In the case where the gate insulating film 12 is formed of a hafnium oxide film and the first insulating film 14 is formed of an aluminum oxide film, an aqueous solution of a fluoride acid is used to laterally etch the gate insulating film 12. In the above steps, the etching is carried out as in Fig. 4B, so that the gate electrode 16 and the first insulating film 14 are etched in an anisotropic manner. The etching as in FIG. 4C allows the gate insulating film 12 to be side-etched selectively in a selective manner using the gate electrode 16 as a mask. In this method, the stacked gate electrode 16, the first insulating film 14, and the gate insulating film 12 are selectively removed.
如第4C圖中所示，因為第一絕緣膜14存在於底切部18上方，因此第一和第二絕緣膜14和22形成上絕緣膜24，如第5A圖中所示。絕緣膜20透過ALD製程而形成，以使得隧道絕緣膜21和第二絕緣膜22具有實質相同的厚度。結果，上絕緣膜24之厚度(藉由加上第一和第二絕緣 膜厚度所得的膜厚度)能夠製得大於隧道絕緣膜21之厚度。如此一來，上絕緣膜24和隧道絕緣膜21各自之厚度能被設定於最佳值。不似比較的範例，第一實施例不使用假層，因此相較於該比較的範例減化製造步驟。As shown in FIG. 4C, since the first insulating film 14 exists above the undercut portion 18, the first and second insulating films 14 and 22 form the upper insulating film 24 as shown in FIG. 5A. The insulating film 20 is formed through an ALD process so that the tunnel insulating film 21 and the second insulating film 22 have substantially the same thickness. As a result, the thickness of the upper insulating film 24 (by adding the first and second insulation) The film thickness obtained by the film thickness can be made larger than the thickness of the tunnel insulating film 21. As a result, the thickness of each of the upper insulating film 24 and the tunnel insulating film 21 can be set to an optimum value. Unlike the comparative example, the first embodiment does not use a dummy layer and therefore reduces the manufacturing steps compared to the comparative example.
於如上述製造之半導體裝置中，閘極電極16形成在半導體基板10之上方，如第7A圖中所示。參照第7A圖和第1圖，閘極絕緣膜12形成在閘極電極16之中央(在字元線34之延伸方向閘極電極16之中央)下方，並於半導體基板10上。第一絕緣膜14被形成從閘極絕緣膜12上區域延伸至閘極電極16之二端(在字元線34之延伸方向閘極電極16之二端)下方區域。第一絕緣膜14由與閘極絕緣膜12不同的材料製成。隧道絕緣膜21形成在半導體基板10上於閘極絕緣膜12之二端。電荷儲存層26插置於隧道絕緣膜21和第一絕緣膜14之間。第二絕緣膜22形成在第一絕緣膜14下方並在電荷儲存層26上。第二絕緣膜22和隧道絕緣膜21由相同的材料製成。In the semiconductor device manufactured as described above, the gate electrode 16 is formed over the semiconductor substrate 10 as shown in Fig. 7A. Referring to FIG. 7A and FIG. 1, the gate insulating film 12 is formed under the gate electrode 16 (in the center of the gate electrode 16 in the direction in which the word line 34 extends), and is formed on the semiconductor substrate 10. The first insulating film 14 is formed in a region extending from a region above the gate insulating film 12 to both ends of the gate electrode 16 (at both ends of the gate electrode 16 in the direction in which the word line 34 extends). The first insulating film 14 is made of a material different from that of the gate insulating film 12. A tunnel insulating film 21 is formed on the semiconductor substrate 10 at both ends of the gate insulating film 12. The charge storage layer 26 is interposed between the tunnel insulating film 21 and the first insulating film 14. The second insulating film 22 is formed under the first insulating film 14 and on the charge storage layer 26. The second insulating film 22 and the tunnel insulating film 21 are made of the same material.
隧道絕緣膜21供使用為電荷儲存層26之隧道阻障。較佳地，隧道絕緣膜21之能隙(energy gap)相關於電荷儲存層26為大。例如，當氧化鋁膜用來形成隧道絕緣膜21時，電荷儲存層26可以由氧化鉿形成。The tunnel insulating film 21 is used as a tunnel barrier for the charge storage layer 26. Preferably, the energy gap of the tunnel insulating film 21 is large in relation to the charge storage layer 26. For example, when an aluminum oxide film is used to form the tunnel insulating film 21, the charge storage layer 26 may be formed of ruthenium oxide.
參照第5A圖，透過ALD製程形成絕緣膜20之前，具有厚度大約1 nm之薄氧化矽膜可以形成於半導體基板10上。如此可能改進由絕緣膜20形成之隧道絕緣膜21之品質。Referring to FIG. 5A, a thin tantalum oxide film having a thickness of about 1 nm may be formed on the semiconductor substrate 10 before the insulating film 20 is formed by an ALD process. It is thus possible to improve the quality of the tunnel insulating film 21 formed of the insulating film 20.
於第二實施例中，上絕緣膜由第一絕緣膜形成。參照第8A圖，執行根據第4A至4C圖中所示第一實施例之製程步驟。參照第8B圖，使用熱氧化作用製程以形成由氧化矽膜形成之絕緣膜20a，以覆蓋半導體基板10和閘極電極16之上表面。使用熱氧化作用製程不允許絕緣膜20a待形成於第一絕緣膜14下方和在閘極絕緣膜12側表面上。絕緣膜20a之厚度例如可設定至5 nm。隧道絕緣膜21a由底切部18中在半導體基板10上之絕緣膜20a形成。In the second embodiment, the upper insulating film is formed of the first insulating film. Referring to Fig. 8A, the process steps according to the first embodiment shown in Figs. 4A to 4C are performed. Referring to Fig. 8B, a thermal oxidation process is used to form an insulating film 20a formed of a hafnium oxide film to cover the upper surfaces of the semiconductor substrate 10 and the gate electrode 16. The use of the thermal oxidation process does not allow the insulating film 20a to be formed under the first insulating film 14 and on the side surface of the gate insulating film 12. The thickness of the insulating film 20a can be set, for example, to 5 nm. The tunnel insulating film 21a is formed of an insulating film 20a on the semiconductor substrate 10 in the undercut portion 18.
參照第8C圖，透過CVD製程形成由氮化矽膜形成之電荷儲存層26a，以便填滿於底切部18中，並覆蓋該絕緣膜20a。因此，第一絕緣膜14直接形成在電荷儲存層26a上。疊層28a由隧道絕緣膜21a、電荷儲存層26a、和上絕緣層24a形成。Referring to Fig. 8C, a charge storage layer 26a formed of a tantalum nitride film is formed by a CVD process so as to fill the undercut portion 18 and cover the insulating film 20a. Therefore, the first insulating film 14 is directly formed on the charge storage layer 26a. The laminate 28a is formed of a tunnel insulating film 21a, a charge storage layer 26a, and an upper insulating layer 24a.
參照第9圖，執行根據第一實施例第5C至7B圖中所示之製程步驟，以產生根據第二實施例之半導體裝置。Referring to Fig. 9, a process step shown in Figs. 5C to 7B of the first embodiment is performed to produce a semiconductor device according to the second embodiment.
如第8B圖中所示，第二實施例取決於形成之隧道絕緣膜21a，不要求待形成之第二絕緣膜。隧道絕緣膜21可以與形成之第二絕緣膜22同時形成，如根據第一實施例之第5A圖中所示。As shown in Fig. 8B, the second embodiment depends on the formed tunnel insulating film 21a, and the second insulating film to be formed is not required. The tunnel insulating film 21 may be formed simultaneously with the formed second insulating film 22 as shown in Fig. 5A according to the first embodiment.
於第一實施例中，當閘極絕緣膜12由氧化矽膜形成時，第一絕緣膜14由氧化鋁膜形成，用來獲得第4C圖中所示之選擇性的側面蝕刻。當與由第一絕緣膜14相同的材料形成之膜被要求用來形成上絕緣膜24時，絕緣膜20(亦 即，隧道絕緣膜21)期望由氧化鋁膜形成。同時，於第二實施例中，可選擇任意的材料用來形成隧道絕緣膜21a。此允許使用能夠形成具有更優越品質之隧道絕緣膜之氧化矽膜，如隧道絕緣膜21a。In the first embodiment, when the gate insulating film 12 is formed of a hafnium oxide film, the first insulating film 14 is formed of an aluminum oxide film for obtaining a selective side etching shown in Fig. 4C. When a film formed of the same material as the first insulating film 14 is required to form the upper insulating film 24, the insulating film 20 (also That is, the tunnel insulating film 21) is desirably formed of an aluminum oxide film. Meanwhile, in the second embodiment, any material may be selected to form the tunnel insulating film 21a. This allows the use of a ruthenium oxide film capable of forming a tunnel insulating film having a superior quality, such as the tunnel insulating film 21a.
於第一實施例中，當使用氧化鋁膜作為隧道絕緣膜21時，具有能隙小於氧化鋁之能隙之氧化鉿被用來形成電荷儲存層26。於第二實施例中，當氧化矽膜用來形成隧道絕緣膜21時，使得容易製造之氮化矽膜能夠用來形成電荷儲存層26a。In the first embodiment, when an aluminum oxide film is used as the tunnel insulating film 21, cerium oxide having an energy gap smaller than that of the aluminum oxide is used to form the charge storage layer 26. In the second embodiment, when the ruthenium oxide film is used to form the tunnel insulating film 21, the nitride film which is easy to manufacture can be used to form the charge storage layer 26a.
於第二實施例中，上絕緣膜24a和隧道絕緣膜21a之各厚度可以個別設定。當第一絕緣膜14之厚度(亦即，上絕緣膜24a)製得大於隧道絕緣膜21a之厚度時，隧道絕緣膜21a允許隧道電流流過，而上絕緣膜24a具有足夠保持電荷儲存層26a之電荷保持性之厚度。In the second embodiment, the respective thicknesses of the upper insulating film 24a and the tunnel insulating film 21a can be individually set. When the thickness of the first insulating film 14 (that is, the upper insulating film 24a) is made larger than the thickness of the tunnel insulating film 21a, the tunnel insulating film 21a allows a tunnel current to flow, and the upper insulating film 24a has a sufficient holding charge storage layer 26a. The thickness of the charge retention.
於第三實施例中，第一和第二絕緣膜由不同的材料形成。參照第10A圖，執行根據第4A至4C圖中所示第一實施例之製程步驟。參照第10B圖，透過ALD製程形成由氧化矽形成之絕緣膜20b，以便覆蓋底切部18和閘極電極16之內表面。絕緣膜20b之厚度可以設定至5 nm。隧道絕緣膜21b由底切部18中半導體基板10上之絕緣膜20b形成。該底切部18中第一絕緣膜14下方之絕緣膜20b變成第二絕緣膜22b。上絕緣膜24b由該第一和第二絕緣膜14和22b形成。透過CVD製程形成由氮化矽膜形成之電 荷儲存層26b，以便填滿於底切部18並覆蓋該絕緣膜20b。於是，由隧道絕緣膜21b、電荷儲存層26b、和上絕緣膜24b形成之疊層28b形成在底切部18之內側。參照第10C圖，執行根據第5C至7B圖中所示之第一實施例之製造步驟，以產生根據第三實施例之半導體裝置。In the third embodiment, the first and second insulating films are formed of different materials. Referring to Fig. 10A, the process steps according to the first embodiment shown in Figs. 4A to 4C are performed. Referring to FIG. 10B, an insulating film 20b formed of yttrium oxide is formed through an ALD process so as to cover the undercut portion 18 and the inner surface of the gate electrode 16. The thickness of the insulating film 20b can be set to 5 nm. The tunnel insulating film 21b is formed of an insulating film 20b on the semiconductor substrate 10 in the undercut portion 18. The insulating film 20b under the first insulating film 14 in the undercut portion 18 becomes the second insulating film 22b. The upper insulating film 24b is formed of the first and second insulating films 14 and 22b. Forming electricity formed by a tantalum nitride film through a CVD process The storage layer 26b is filled to fill the undercut portion 18 and cover the insulating film 20b. Then, the laminate 28b formed of the tunnel insulating film 21b, the charge storage layer 26b, and the upper insulating film 24b is formed inside the undercut portion 18. Referring to Fig. 10C, the manufacturing steps according to the first embodiment shown in Figs. 5C to 7B are performed to produce the semiconductor device according to the third embodiment.
於第三實施例中，氧化鋁膜用來形成第一絕緣膜14，而該氧化矽膜用來形成閘極絕緣膜12、第二絕緣膜22b、和隧道絕緣膜21b。參照第10A圖，第一絕緣膜14幾乎不受到基於閘極絕緣膜12之側面蝕刻之蝕刻。各閘極絕緣膜12和隧道絕緣膜21b可以由具有優越薄膜品質之氧化矽膜所形成。In the third embodiment, an aluminum oxide film is used to form the first insulating film 14, and this ruthenium oxide film is used to form the gate insulating film 12, the second insulating film 22b, and the tunnel insulating film 21b. Referring to FIG. 10A, the first insulating film 14 is hardly etched by the side etching based on the gate insulating film 12. Each of the gate insulating film 12 and the tunnel insulating film 21b can be formed of a hafnium oxide film having superior film quality.
於第一至第三實施例中，電荷儲存層26可以是譬如多晶矽之導體。當電荷儲存層26藉由導體形成並配置於字元線34之間，如第7B圖中所示時，於擴散區30之延伸方向鄰接記憶體胞之電荷儲存層26被電性耦合。當導體用作為電荷儲存層時，執行去除字元線之間電荷儲存層26之步驟。於此種方式，氧化鉿、氮化矽膜、和矽膜(例如，多晶矽膜)任何其中一種可用來形成電荷儲存層26。使用導體矽膜為電荷儲存層可使大量之電荷被儲存。譬如氧化鉿、氮化矽膜之絕緣膜可使用為電荷儲存層以省略去除字元線間電荷儲存層之步驟。In the first to third embodiments, the charge storage layer 26 may be a conductor such as a polysilicon. When the charge storage layer 26 is formed by a conductor and disposed between the word lines 34, as shown in FIG. 7B, the charge storage layer 26 adjacent to the memory cells in the extending direction of the diffusion region 30 is electrically coupled. When the conductor is used as a charge storage layer, the step of removing the charge storage layer 26 between the word lines is performed. In this manner, any one of yttrium oxide, tantalum nitride film, and tantalum film (e.g., polysilicon film) can be used to form charge storage layer 26. The use of a conductor diaphragm as a charge storage layer allows a large amount of charge to be stored. An insulating film such as a hafnium oxide or tantalum nitride film may be used as a charge storage layer to omit the step of removing the inter-line charge storage layer.
雖然以上已詳細說明了本發明之較佳實施例，但是本發明並不受這些特定實施例之限制，而在本發明之精神和範圍內，如申請專利範圍中所界定的，可作各種的修飾和 改變。Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited by these specific embodiments, and various modifications may be made within the spirit and scope of the present invention as defined in the scope of the claims. Modification and change.
10‧‧‧矽基板10‧‧‧矽 substrate
12‧‧‧閘極絕緣膜12‧‧‧Gate insulation film
14‧‧‧第一絕緣膜14‧‧‧First insulating film
16‧‧‧閘極電極16‧‧‧gate electrode
18‧‧‧底切部18‧‧‧ undercut
20、20a、20b‧‧‧絕緣膜20, 20a, 20b‧‧‧ insulating film
21、21a、21b‧‧‧隧道絕緣膜21, 21a, 21b‧‧‧ tunnel insulation film
22、22b‧‧‧第二絕緣膜22, 22b‧‧‧second insulation film
23‧‧‧第二絕緣膜23‧‧‧Second insulation film
24、24a、24b‧‧‧上絕緣膜24, 24a, 24b‧‧‧ upper insulation film
26、26a、26b‧‧‧電荷儲存層26, 26a, 26b‧‧‧ charge storage layer
28、28a、28b‧‧‧疊層28, 28a, 28b‧‧‧ laminate
30‧‧‧擴散區30‧‧‧Diffusion zone
32‧‧‧絕緣層32‧‧‧Insulation
34‧‧‧字元線34‧‧‧ character line
36‧‧‧假層36‧‧‧False
38‧‧‧第一絕緣膜38‧‧‧First insulating film
40‧‧‧上絕緣膜40‧‧‧Upper insulation film
44‧‧‧通道區44‧‧‧Channel area
第1圖為根據比較的範例和本發明之第一至第三實施例之快閃記憶體之平面圖；第2A至2C圖顯示根據比較的範例對應沿著第1圖中所示線A－A(部分1)製造快閃記憶體之步驟；第3A至3C圖顯示根據比較的範例對應沿著第1圖中所示線A－A(部分2)製造快閃記憶體之步驟；第4A至4C圖顯示根據第一實施例對應沿著第1圖中所示線A－A(部分1)製造快閃記憶體之步驟；第5A至5C圖顯示根據第一實施例對應沿著第1圖中所示線A－A(部分2)製造快閃記憶體之步驟；第6圖為顯示根據第一實施例對應沿著第1圖中所示線A－A(部分3)製造快閃記憶體之步驟之剖面圖；第7A和7B圖顯示根據第一實施例製造快閃記憶體之步驟，其中，第7A圖為對應沿著第1圖中所示線A－A之剖面之剖面圖，而第7B圖為對應沿著第1圖中所示線B－B之剖面之剖面圖；第8A至8C圖顯示根據第二實施例對應沿著第1圖中所示線A－A(部分1)製造快閃記憶體之步驟；第9圖為顯示根據第二實施例對應沿著第1圖中所示線A－A(部分2)製造快閃記憶體之步驟之剖面圖；以及第10A至10C圖顯示根據第三實施例對應沿著第1圖中所示線A－A製造快閃記憶體之步驟。1 is a plan view of a flash memory according to a comparative example and first to third embodiments of the present invention; FIGS. 2A to 2C are diagrams showing a line A-A shown in FIG. 1 according to a comparative example. (Part 1) a step of manufacturing a flash memory; FIGS. 3A to 3C show a step of manufacturing a flash memory along the line A-A (Part 2) shown in FIG. 1 according to a comparative example; 4A to 4C is a view showing a step of manufacturing a flash memory along the line A-A (part 1) shown in FIG. 1 according to the first embodiment; and FIGS. 5A to 5C are shown corresponding to the first figure according to the first embodiment. The steps of the line A-A (part 2) for manufacturing the flash memory are shown; and the sixth figure is for the manufacture of the flash memory corresponding to the line A-A (part 3) shown in the first figure according to the first embodiment. Sectional view of the steps of the body; FIGS. 7A and 7B are views showing the steps of manufacturing the flash memory according to the first embodiment, wherein FIG. 7A is a cross-sectional view corresponding to the section along the line A-A shown in FIG. And FIG. 7B is a cross-sectional view corresponding to the section along the line B-B shown in FIG. 1; FIGS. 8A to 8C are diagrams corresponding to the line shown in FIG. 1 according to the second embodiment. A-A (Part 1) step of manufacturing a flash memory; FIG. 9 is a view showing a step of manufacturing a flash memory corresponding to the line A-A (Part 2) shown in FIG. 1 according to the second embodiment. The sectional view; and the 10A to 10C drawings show the steps of manufacturing the flash memory corresponding to the line A-A shown in Fig. 1 according to the third embodiment.
10‧‧‧矽基板10‧‧‧矽 substrate
12‧‧‧閘極絕緣膜12‧‧‧Gate insulation film
14‧‧‧第一絕緣膜14‧‧‧First insulating film
16‧‧‧閘極電極16‧‧‧gate electrode
18‧‧‧底切部18‧‧‧ undercut
Claims (8)
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| TWI660426B (en) * | 2015-08-25 | 2019-05-21 | 聯華電子股份有限公司 | Flash cell and process thereof |
| JP2021150591A (en) | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | Semiconductor device |
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| TW251307B (en) * | 1992-10-05 | 1995-07-11 | Ciba Geigy | |
| JP2001156188A (en) * | 1999-03-08 | 2001-06-08 | Toshiba Corp | Semiconductor storage device and method for manufacturing the same |
| US20020149066A1 (en) * | 2001-03-29 | 2002-10-17 | Chang Kent Kuohua | Twin bit cell flash memory device |
| US6639271B1 (en) * | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
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| DE10205079B4 (en) * | 2002-02-07 | 2008-01-03 | Infineon Technologies Ag | Method for producing a memory cell |
| JP2004071877A (en) * | 2002-08-07 | 2004-03-04 | Fujitsu Ltd | Semiconductor storage device and its manufacturing method |
| JP4537680B2 (en) * | 2003-08-04 | 2010-09-01 | 株式会社東芝 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, ITS OPERATION METHOD, MANUFACTURING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SYSTEM |
| US6885072B1 (en) * | 2003-11-18 | 2005-04-26 | Applied Intellectual Properties Co., Ltd. | Nonvolatile memory with undercut trapping structure |
| TWI229924B (en) * | 2004-02-10 | 2005-03-21 | Powerchip Semiconductor Corp | Method of manufacturing non-volatile memory cell |
| US7186607B2 (en) * | 2005-02-18 | 2007-03-06 | Infineon Technologies Ag | Charge-trapping memory device and method for production |
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| TW251307B (en) * | 1992-10-05 | 1995-07-11 | Ciba Geigy | |
| JP2001156188A (en) * | 1999-03-08 | 2001-06-08 | Toshiba Corp | Semiconductor storage device and method for manufacturing the same |
| US20020149066A1 (en) * | 2001-03-29 | 2002-10-17 | Chang Kent Kuohua | Twin bit cell flash memory device |
| US6639271B1 (en) * | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
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| WO2009032678A1 (en) | 2009-03-12 |
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