TWI471936B - Semiconductor device and method for manufacturing thereof - Google Patents
Semiconductor device and method for manufacturing thereof Download PDFInfo
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- TWI471936B TWI471936B TW97146131A TW97146131A TWI471936B TW I471936 B TWI471936 B TW I471936B TW 97146131 A TW97146131 A TW 97146131A TW 97146131 A TW97146131 A TW 97146131A TW I471936 B TWI471936 B TW I471936B
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- 239000004065 semiconductor Substances 0.000 title claims description 67
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 title description 49
- 239000004020 conductor Substances 0.000 claims description 78
- 239000000758 substrate Substances 0.000 claims description 45
- 238000005530 etching Methods 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000010408 film Substances 0.000 description 146
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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Description
本發明係有關一種半導體裝置，其具有分隔的電荷儲存層。The present invention relates to a semiconductor device having a separate charge storage layer.
非揮發性的記憶體是已經被廣泛使用的半導體裝置，其中的資料不但可以重複寫入，即使切掉電源也還能保有儲藏的資料。在一種典型非揮發性記憶體的快閃記憶體(flash memory)中，組構記憶體單元(memory cell)的電晶體係包括所謂的電荷儲存層(charge storage layer)，不是由浮置閘(floating gate)便是由絕緣薄膜所構成。電荷會積聚在用來儲存資料的電荷儲存層內。Non-volatile memory is a widely used semiconductor device in which data can be rewritten without being erased, even if the power is cut off. In a typical non-volatile memory flash memory, the electromorphic system of a memory cell includes a so-called charge storage layer, not by a floating gate ( The floating gate is composed of an insulating film. The charge will accumulate in the charge storage layer used to store the data.
近來有各式各樣的方法被提出，用來增加於單一記憶體單元中所能儲存的資料容量。舉例來說，在虛接地(virtual ground)式的快閃記憶體中，區域會在源極區域以及汲極區域之間切換，用來在單一記憶體單元的電荷儲存層中形成兩個電荷儲存區域。這使得在單一記憶體單元中有可能儲存2個位元的資料。A variety of methods have recently been proposed to increase the amount of data that can be stored in a single memory unit. For example, in a virtual grounded flash memory, the region switches between the source region and the drain region to form two charge stores in the charge storage layer of a single memory cell. region. This makes it possible to store 2 bits of data in a single memory unit.
日本未經審查的專利申請案公開號No. 2002-313967揭露了一種快閃記憶體，其具有以STI(shallow trench isolation，淺溝槽隔離)區域來分隔的電荷儲存層。例如，使用以氮化物薄膜製成的遮罩層製作用來分隔電荷儲存層之STI區域的技術，係揭露於2007年非揮發性半導體記憶體研討會(Non-volatile Semiconductor Memory Workshop)，第110至111頁。A flash memory having a charge storage layer separated by STI (shallow trench isolation) regions is disclosed in Japanese Unexamined Patent Publication No. Publication No. 2002-313967. For example, a technique for forming an STI region for a charge storage layer using a mask layer made of a nitride film is disclosed in the 2007 Non-Volatile Semiconductor Memory Workshop, No. 110 To 111 pages.
於使用絕緣薄膜作為電荷儲存層的虛接地式快閃記憶體中，如果其電荷儲存層沒有在記憶體單元中之通道(通道)方向被分隔，那麼分別儲存在兩電荷儲存區域中的電荷便會彼此互相干擾，也就是所謂的CBD(Complementary Bit Disturb，互補位元干擾)。因此要分隔儲存在兩電荷儲存區域中的電荷是困難的，特別是當所採用虛接地式的快閃記憶體使用導電薄膜作為電荷儲存層時，所儲存的電荷會在電荷儲存層內移動。因此，電荷儲存層必須要在記憶體單元中之通道方向被分隔。In a virtual grounded flash memory using an insulating film as a charge storage layer, if the charge storage layer is not separated in the channel (channel) direction in the memory cell, the charge stored in the two charge storage regions respectively Will interfere with each other, the so-called CBD (Complementary Bit Disturb). Therefore, it is difficult to separate the charges stored in the two charge storage regions, especially when the virtual ground type flash memory using the conductive film as the charge storage layer, the stored charges move in the charge storage layer. Therefore, the charge storage layer must be separated in the direction of the channel in the memory cell.
當電荷儲存層連接在兩記憶體單元之間時，儲存在電荷儲存層的電荷會在其中移動，而影響到相鄰記憶體單元的臨界電壓。When the charge storage layer is connected between the two memory cells, the charge stored in the charge storage layer moves therein, affecting the threshold voltage of the adjacent memory cells.
本發明之一個實施例是：一種半導體裝置，其具有電荷儲存層，該電荷儲存層於記憶體單元內在通道方向中被分隔，並且在兩相鄰記憶體單元間被進一步分隔；以及製造此半導體裝置的方法。One embodiment of the present invention is a semiconductor device having a charge storage layer that is separated in a channel direction in a memory cell and further separated between two adjacent memory cells; and fabricating the semiconductor The method of the device.
根據本發明其中一個面向，係提出一種半導體裝置的製造方法，包括下列步驟：在半導體基板上形成電荷儲存層；利用形成於電荷儲存層上的遮罩層作為遮罩，而在電荷儲存層及半導體基板中形成延伸之第一凹槽(groove)；形成欲填入第一凹槽內的絕緣薄膜；在遮罩層與絕緣薄膜中形成延伸跨過第一凹槽的第二凹槽；藉由對形成在第二凹槽下方的電荷儲存層進行氧化，以形成閘極絕緣薄膜；形成欲填入第二凹槽之第一導體層；除去遮罩層；在第一導體層於寬度方向的兩個側面上形成第二導體層，以形成包含第一和第二導體層的字元線；以及利用字元線做為遮罩來除去電荷儲存層。According to one aspect of the present invention, a method of fabricating a semiconductor device includes the steps of: forming a charge storage layer on a semiconductor substrate; using a mask layer formed on the charge storage layer as a mask, and in the charge storage layer and Forming an extended first groove in the semiconductor substrate; forming an insulating film to be filled in the first groove; forming a second groove extending across the first groove in the mask layer and the insulating film; Oxidizing the charge storage layer formed under the second recess to form a gate insulating film; forming a first conductor layer to be filled in the second recess; removing the mask layer; in the width direction of the first conductor layer A second conductor layer is formed on both sides to form a word line including the first and second conductor layers; and the word line is used as a mask to remove the charge storage layer.
根據本發明另一面向，提供一種半導體裝置，包括：半導體基板，具有延伸的第一凹槽；絕緣薄膜，用來填入第一凹槽，並且突出於半導體基板上表面的上方；字元線，形成在半導體裝置上，並延伸跨過第一凹槽；閘極絕緣薄膜，係形成在半導體基板上並位於字元線之寬度方向中心下方，並且在字元線的延伸方向由絕緣薄膜所分隔；電荷儲存層，係形成在半導體基板上，並位於字元線之寬度方向兩端下方，並且於其間插進有閘極絕緣薄膜，以便在字元線的延伸方向由絕緣薄膜分隔。According to another aspect of the present invention, a semiconductor device includes: a semiconductor substrate having an extended first recess; an insulating film for filling the first recess and protruding above the upper surface of the semiconductor substrate; Formed on the semiconductor device and extending across the first recess; the gate insulating film is formed on the semiconductor substrate and located below the center of the width direction of the word line, and is extended by the insulating film in the extending direction of the word line Separating; a charge storage layer is formed on the semiconductor substrate and located under both ends in the width direction of the word line, and a gate insulating film is interposed therebetween so as to be separated by an insulating film in the extending direction of the word line.
第1圖是根據實施例之NAND型快閃記憶體的透視圖。參見第1圖，形成在半導體基板10中延伸之第一凹槽12。絕緣薄膜14係填入第一凹槽12內，並且從半導體基板10的上表面突出。被填入絕緣薄膜14的凹槽12，是用來當作STI(淺溝槽隔離)區域。在半導體基板10上形成跨過第一凹槽12延伸的字元線16。在一實施例中，字元線16是用來作為閘極電極。閘極絕緣薄膜18則是形成在半導體基板10上並位於字元線16的寬度方向之中心下方。閘極絕緣薄膜18係被絕緣薄膜14沿著字元線16長度或是延伸方向所分隔。層疊層25由隧道絕緣薄膜20、電荷儲存層22以及頂部絕緣薄膜24所組成。層疊層25係形成在字元線16沿著寬度方向的兩側下方，並插進閘極的絕緣薄膜18。層疊層25係被絕緣薄膜14沿著字元線16長度或是延伸方向所分隔。用來作為源極區域與汲極區域之擴散區域26係於第一凹槽12之間形成在字元線16之寬度方向兩側的半導體基板10之內。Fig. 1 is a perspective view of a NAND type flash memory according to an embodiment. Referring to FIG. 1, a first recess 12 extending in the semiconductor substrate 10 is formed. The insulating film 14 is filled in the first recess 12 and protrudes from the upper surface of the semiconductor substrate 10. The groove 12 filled in the insulating film 14 is used as an STI (Shallow Trench Isolation) region. A word line 16 extending across the first recess 12 is formed on the semiconductor substrate 10. In one embodiment, word line 16 is used as a gate electrode. The gate insulating film 18 is formed on the semiconductor substrate 10 and below the center of the width direction of the word line 16. The gate insulating film 18 is separated by the insulating film 14 along the length or extension direction of the word line 16. The layer stack 25 is composed of a tunnel insulating film 20, a charge storage layer 22, and a top insulating film 24. The laminated layer 25 is formed on the insulating film 18 which is inserted under the both sides of the word line 16 in the width direction and inserted into the gate. The layer stack 25 is separated by the insulating film 14 along the length or extension direction of the word line 16. A diffusion region 26 serving as a source region and a drain region is formed between the first recesses 12 in the semiconductor substrate 10 on both sides in the width direction of the word line 16.
第2A圖至第8C圖係圖解一種用來製造根據一實施例的NAND型快閃記憶體的方法。為了便於說明，此處將敘述的示範方法是用來製造單一的記憶體單元。2A through 8C are diagrams illustrating a method for fabricating a NAND type flash memory according to an embodiment. For ease of explanation, the exemplary method described herein is for making a single memory cell.
參見第2A至2C圖，在一實施例中，隧道絕緣薄膜20是由厚度約5nm的氧化矽薄膜所形成，電荷儲存層22是由厚度約7nm的非晶矽(amorphous silicon)薄膜所形成，而頂部絕緣薄膜24則是由厚度約15nm氧化矽薄膜所形成，各層依序製作在P型矽基板的半導體基板10上方。如此便在半導體基板10的上形成層疊層25。隧道絕緣薄膜20可採用熱氧化(thermal oxidation)製程來製作，而電荷儲存層22和頂部絕緣薄膜24則可採用CVD(Chemical Vapor Depositioh，化學氣相沉積)法來製作。Referring to FIGS. 2A to 2C, in one embodiment, the tunnel insulating film 20 is formed of a hafnium oxide film having a thickness of about 5 nm, and the charge storage layer 22 is formed of an amorphous silicon film having a thickness of about 7 nm. The top insulating film 24 is formed of a ruthenium oxide film having a thickness of about 15 nm, and each layer is sequentially formed over the semiconductor substrate 10 of the P-type germanium substrate. Thus, the laminated layer 25 is formed on the semiconductor substrate 10. The tunnel insulating film 20 can be fabricated by a thermal oxidation process, and the charge storage layer 22 and the top insulating film 24 can be fabricated by a CVD (Chemical Vapor Deposit) process.
具有延伸開口的遮罩層30係藉由CVD製程形成在頂部絕緣薄膜24上。在一實施例中，遮罩層30是由厚度約100nm的氮化矽薄膜所構成。以遮罩層30作為遮罩，透過RIE(reactive ion etching，反應性離子蝕刻)製程蝕刻層疊層25與半導體基板10。結果，於層疊層25與半導體基板10中形成延伸之第一凹槽12。絕緣薄膜14則是由氧化矽薄膜所構成，其實質上係藉由高密度CVD電漿製程所沈積，以便填入第一凹槽12。之後，絕緣薄膜14可利用CMP(Chemical Mechanical Polishing，化學機械研磨法)製程來移除，以暴露出遮罩層30的上表面。如此可讓絕緣薄膜14的上表面齊平於遮罩層30的上表面。The mask layer 30 having the extended opening is formed on the top insulating film 24 by a CVD process. In one embodiment, the mask layer 30 is formed of a tantalum nitride film having a thickness of about 100 nm. The layered layer 25 and the semiconductor substrate 10 are etched by a RIE (Reactive Ion Etching) process using the mask layer 30 as a mask. As a result, the extended first groove 12 is formed in the layer stack 25 and the semiconductor substrate 10. The insulating film 14 is composed of a ruthenium oxide film which is substantially deposited by a high density CVD plasma process to fill the first recess 12. Thereafter, the insulating film 14 can be removed by a CMP (Chemical Mechanical Polishing) process to expose the upper surface of the mask layer 30. This allows the upper surface of the insulating film 14 to be flush with the upper surface of the mask layer 30.
參見第3A至3C圖，厚度約100nm的光阻材料(未繪出)係塗敷在遮罩層30與絕緣薄膜14上。在一實施例中，藉由光阻收縮(resist shrink)或是雙曝光(dopble exposure)製程，於光阻材料內形成延伸跨過第一凹槽12、寬度約30nm的開口。遮罩層30、頂部絕緣薄膜24以及絕緣薄膜14能以光阻材料作為遮罩，利用RIE製程進行蝕刻。如此可形成第二凹槽32，其於遮罩層30、頂部絕緣薄膜24以及絕緣薄膜14中延伸跨過第一凹槽12。Referring to Figures 3A through 3C, a photoresist material (not shown) having a thickness of about 100 nm is applied over the mask layer 30 and the insulating film 14. In one embodiment, an opening extending across the first recess 12 and having a width of about 30 nm is formed in the photoresist material by a resist shrink or a dopble exposure process. The mask layer 30, the top insulating film 24, and the insulating film 14 can be etched by a RIE process using a photoresist as a mask. The second recess 32 is formed to extend across the first recess 12 in the mask layer 30, the top insulating film 24, and the insulating film 14.
在一實施例中，遮罩層30是由氮化矽薄膜製作而成，而頂部絕緣薄膜24以及絕緣薄膜14各者是由氧化矽薄膜製作而成。因此於製作第二凹槽32的步驟中，遮罩層30會被蝕刻以暴露出頂部絕緣薄膜24的表面。頂部絕緣薄膜24以及絕緣薄膜14可以同時被蝕刻。即使已經移除了頂部絕緣薄膜24而暴露出電荷儲存層22的表面，對於絕緣薄膜14仍可實施過蝕刻(over-etching)以蝕刻地更深。因為電荷儲存層22是由非晶矽的薄膜所製作，因此即使是採取過蝕刻的方式也很難被蝕刻。可實施過蝕刻讓第二凹槽32的下表面位於半導體基板10的上表面之上。換言之，就是實施過蝕刻好讓第二凹槽32的下表面位於隧道絕緣薄膜20的下表面之上。In one embodiment, the mask layer 30 is made of a tantalum nitride film, and the top insulating film 24 and the insulating film 14 are each made of a hafnium oxide film. Therefore, in the step of fabricating the second recess 32, the mask layer 30 is etched to expose the surface of the top insulating film 24. The top insulating film 24 and the insulating film 14 can be simultaneously etched. Even if the top insulating film 24 has been removed to expose the surface of the charge storage layer 22, the insulating film 14 can be over-etched to be etched deeper. Since the charge storage layer 22 is made of an amorphous germanium film, it is difficult to be etched even if it is over-etched. Over etching may be performed such that the lower surface of the second recess 32 is over the upper surface of the semiconductor substrate 10. In other words, etching is performed so that the lower surface of the second recess 32 is located above the lower surface of the tunnel insulating film 20.
參見第4A至4C圖，形成在第二凹槽32下方、表面暴露出來的電荷儲存層22，係經由熱氧化製程來氧化。如此可形成厚度約20nm、由氧化矽薄膜所構成的閘極絕緣薄膜18。Referring to Figures 4A through 4C, the charge storage layer 22, which is formed under the second recess 32 and exposed on the surface, is oxidized via a thermal oxidation process. Thus, a gate insulating film 18 made of a hafnium oxide film having a thickness of about 20 nm can be formed.
參見第5A至5C圖，由非晶矽薄膜(或是多晶矽薄膜)所構成的第一導體層34實質上以CVD製程沈積，以便填入第二凹槽32。之後，可透過CMP製程來移除第一導體層34，以便暴露出遮罩層30與絕緣薄膜14的每個上表面。如此，將閘極絕緣薄膜18形成於第一導體層34之下。Referring to FIGS. 5A through 5C, the first conductor layer 34 composed of an amorphous germanium film (or a polysilicon film) is deposited substantially in a CVD process to fill the second recess 32. Thereafter, the first conductor layer 34 may be removed through a CMP process to expose each of the upper surfaces of the mask layer 30 and the insulating film 14. Thus, the gate insulating film 18 is formed under the first conductor layer 34.
參見第6A至6C圖，利用第一導體層34與遮罩層30作為遮罩，透過RIE製程來蝕刻絕緣薄膜14。如此可降低絕緣薄膜14的高度。換言之，就是可以降低絕緣薄膜14從頂部絕緣薄膜24上表面突出的量。之後，可透過利用磷酸之濕蝕刻製程來移除遮罩層30。Referring to FIGS. 6A to 6C, the insulating film 14 is etched through the RIE process using the first conductor layer 34 and the mask layer 30 as a mask. This can lower the height of the insulating film 14. In other words, it is possible to reduce the amount by which the insulating film 14 protrudes from the upper surface of the top insulating film 24. Thereafter, the mask layer 30 can be removed by a wet etching process using phosphoric acid.
參見第7A至7C圖，由非晶矽薄膜(或是多晶矽薄膜)製成、厚度約25nm的第二導體層36係透過CVD製程來沈積，以實質上覆蓋住第一導體層34。之後第二導體層36的表面係利用RIE製程來蝕刻。如此一來，第二導體層36係留存在第一導體層34的寬度方向之兩側，以形成包含第一導體層34以及第二導體層36的字元線16。閘極絕緣薄膜18係形成於第一導體層34的下方，也就是位於字元線16之寬度方向中心的下方。Referring to Figures 7A through 7C, a second conductor layer 36 made of an amorphous germanium film (or a polysilicon film) having a thickness of about 25 nm is deposited by a CVD process to substantially cover the first conductor layer 34. The surface of the second conductor layer 36 is then etched using an RIE process. As a result, the second conductor layer 36 is left on both sides in the width direction of the first conductor layer 34 to form the word line 16 including the first conductor layer 34 and the second conductor layer 36. The gate insulating film 18 is formed under the first conductor layer 34, that is, below the center in the width direction of the word line 16.
參見第8A至8C圖，頂部絕緣薄膜24與電荷儲存層22係以字元線16作為遮罩並透過RIE製程來移除。因此電荷儲存層22係留存於字元線16之寬度方向兩端的下方。換言之，電荷儲存層22是形成於字元線16之寬度兩端的下方，以插進閘極絕緣薄膜18。之後，可利用字元線16與絕緣薄膜14作為遮罩，將砷離子植入半導體基板10。如此可讓作為源極區域與汲極區域的擴散區域26於第一凹槽12之間形成於字元線16之寬度方向兩側的半導體基板10之內。Referring to Figures 8A through 8C, the top insulating film 24 and the charge storage layer 22 are removed by the RIE process using the word line 16 as a mask. Therefore, the charge storage layer 22 remains below the both ends in the width direction of the word line 16. In other words, the charge storage layer 22 is formed under both ends of the width of the word line 16 to be inserted into the gate insulating film 18. Thereafter, arsenic ions can be implanted into the semiconductor substrate 10 by using the word line 16 and the insulating film 14 as a mask. In this way, the diffusion region 26 as the source region and the drain region can be formed in the semiconductor substrate 10 on both sides in the width direction of the word line 16 between the first grooves 12.
根據一實施例的製造方法，係利用形成在頂部絕緣薄膜24之上並具有延伸開口的遮罩層30作為遮罩來蝕刻層疊層薄膜25以及半導體基板10，以形成延伸的第一凹槽12，如第2A至2C圖所示。接著形成欲填入第一凹槽12內的絕緣薄膜14。如第3A至3C圖所示，在遮罩層30與絕緣薄膜14內，形成延伸跨過第一凹槽12的第二凹槽32。如第4A至4C圖所示，形成在第二凹槽32下方的電荷儲存層22係經氧化，以形成閘極絕緣薄膜18。如第5A至5C圖所示，在第二凹槽32內填入第一導體層34，之後如第6A至6C圖，移除遮罩層30。如第7A至7C圖，在第一導體層34的寬度方向之兩個側面處形成第二導體層36，以形成字元線16，而字元線16包含第一導體層34以及第二導體層36。之後，利用字元線16作為遮罩，以蝕刻的方式移除頂部絕緣薄膜24與電荷儲存層22，如第8A至8C圖所示。According to the manufacturing method of an embodiment, the laminate film 25 and the semiconductor substrate 10 are etched by using the mask layer 30 formed on the top insulating film 24 and having an extended opening as a mask to form the extended first groove 12 , as shown in Figures 2A through 2C. Next, an insulating film 14 to be filled in the first recess 12 is formed. As shown in FIGS. 3A to 3C, in the mask layer 30 and the insulating film 14, a second recess 32 extending across the first recess 12 is formed. As shown in FIGS. 4A to 4C, the charge storage layer 22 formed under the second recess 32 is oxidized to form the gate insulating film 18. As shown in FIGS. 5A to 5C, the first conductor layer 34 is filled in the second recess 32, and then the mask layer 30 is removed as shown in FIGS. 6A to 6C. As shown in FIGS. 7A to 7C, the second conductor layer 36 is formed at both side faces in the width direction of the first conductor layer 34 to form the word line 16, and the word line 16 includes the first conductor layer 34 and the second conductor. Layer 36. Thereafter, the top insulating film 24 and the charge storage layer 22 are removed by etching using the word line 16 as a mask as shown in Figs. 8A to 8C.
在上述的製造方法中，如第1圖所示，係形成延伸在半導體基板10內部的第一凹槽12，並於第一凹槽12內填入絕緣薄膜14，其係從於半導體基板10的表面突出。電荷儲存層22係被絕緣薄膜14在字元線16之長度或是延伸方向所分隔，且形成於字元線16之寬度方向兩端之下方。換言之，電荷儲存層22是在字元線16的延伸方向在兩相鄰的記憶體單元之間被分隔，並進一步沿著字元線16的寬度方向在兩相鄰的記憶體單元之間被分隔。再者，被絕緣薄膜14在字元線16延伸的方向所分隔的閘極絕緣薄膜18係形成在字元線16之寬度方向的中心下方。電荷儲存層22被形成以插入閘極絕緣薄膜18。也就是說，在記憶體單元的內部，係沿著通道的方向來分隔電荷儲存層22。In the above manufacturing method, as shown in FIG. 1, a first recess 12 extending inside the semiconductor substrate 10 is formed, and an insulating film 14 is filled in the first recess 12 from the semiconductor substrate 10. The surface is prominent. The charge storage layer 22 is partitioned by the insulating film 14 in the length or extending direction of the word line 16, and is formed below the both ends in the width direction of the word line 16. In other words, the charge storage layer 22 is separated between two adjacent memory cells in the extending direction of the word line 16, and further between the two adjacent memory cells along the width direction of the word line 16. Separate. Further, the gate insulating film 18 partitioned by the insulating film 14 in the direction in which the word line 16 extends is formed below the center in the width direction of the word line 16. The charge storage layer 22 is formed to be inserted into the gate insulating film 18. That is, inside the memory cell, the charge storage layer 22 is separated along the direction of the channel.
在一實施例中，電荷儲存層22在記憶體單元內部是沿著通道方向被分開地形成。所以就算電荷儲存層22由像是非晶矽薄膜的導電薄膜所製成，在單一記憶體單元內部也會形成兩個電荷儲存區域，因此可讓單一的記憶體單元儲存兩個位元的資料。特別是當採用導電薄膜來製作電荷儲存層22的時候，與採用絕緣薄膜的情形相較之下，可儲存的電荷量會變得更大。當採用絕緣薄膜(如氮化矽薄膜)來形成電荷儲存層22時，在記憶體單元內即使沒有沿著通道的方向來分隔，仍然可以製作出兩個電荷儲存區域。然而，當電荷儲存層22沿著通道的方向被分隔時，可以避免積聚在兩電荷儲存區域內的電荷互相干擾，也就是所謂的CBD(互補位元干擾)。如此可更有效地分隔儲存在兩電荷儲存區域內的電荷。舉例來說，如果是採用絕緣薄膜來製作電荷儲存層22，在記憶體單元內電荷儲存層22會沿著通道的方向被分隔。特別是當微型化(miniaturize)記憶體單元，使得通道長度減少的時候，抑制CBD的效果可以更好。In an embodiment, the charge storage layer 22 is formed separately along the channel direction inside the memory cell. Therefore, even if the charge storage layer 22 is made of a conductive film such as an amorphous germanium film, two charge storage regions are formed inside a single memory cell, so that a single memory cell can store two bits of data. In particular, when a conductive film is used to form the charge storage layer 22, the amount of charge that can be stored becomes larger as compared with the case of using an insulating film. When an insulating film such as a tantalum nitride film is used to form the charge storage layer 22, two charge storage regions can be fabricated even if they are not separated in the memory cell along the direction of the channel. However, when the charge storage layers 22 are separated in the direction of the channels, it is possible to prevent the charges accumulated in the two charge storage regions from interfering with each other, that is, the so-called CBD (complementary bit interference). This makes it possible to more effectively separate the charges stored in the two charge storage regions. For example, if the charge storage layer 22 is formed using an insulating film, the charge storage layer 22 is separated in the direction of the channel in the memory cell. Especially when miniaturizing the memory unit, the effect of suppressing the CBD can be better when the channel length is reduced.
在一實施例中，電荷儲存層22係在兩相鄰的記憶體單元之間被分隔。當電荷儲存層是連接在兩相鄰記憶體單元之間的情況下，使用導電薄膜來製作電荷儲存層時會讓積聚在電荷儲存層22內的電荷在兩相鄰的記憶體單元間移動，而影響到相鄰記憶體單元的臨界電壓。舉例來說，如果採用絕緣薄膜來製作電荷儲存層22，當記憶體單元被微型化以縮短兩相鄰記憶體單元間的間距時，便有可能影響相鄰記憶體單元的臨界電壓。在一實施例中，電荷儲存層22是在兩相鄰的記憶體單元之間被分隔。所以不論是使用導電薄膜或是絕緣薄膜來製作電荷儲存層22之情形，都可以抑制相鄰的記憶體單元對於相鄰記憶體單元之臨界電壓的影響。採用這種方式，於一實施例中，於記憶體單元內不但沿著通道的方向來分隔電荷儲存層22，也進一步在兩相鄰的記憶體單元之間來分隔電荷儲存層22。如此可增加可以用來製作電荷儲存層22的材料。In one embodiment, the charge storage layer 22 is separated between two adjacent memory cells. When the charge storage layer is connected between two adjacent memory cells, the use of the conductive film to form the charge storage layer causes the charge accumulated in the charge storage layer 22 to move between the adjacent memory cells. It affects the threshold voltage of adjacent memory cells. For example, if the charge storage layer 22 is formed by using an insulating film, when the memory cell is miniaturized to shorten the spacing between two adjacent memory cells, it is possible to affect the threshold voltage of the adjacent memory cells. In one embodiment, the charge storage layer 22 is separated between two adjacent memory cells. Therefore, regardless of whether the charge storage layer 22 is formed by using a conductive film or an insulating film, the influence of adjacent memory cells on the threshold voltage of the adjacent memory cells can be suppressed. In this manner, in one embodiment, the charge storage layer 22 is separated not only in the direction of the channel in the memory cell, but also between the two adjacent memory cells. This can increase the materials that can be used to make the charge storage layer 22.
參見第8A至8C圖，使用字元線16作為遮罩，藉由蝕刻移除電荷儲存層22，以便將電荷儲存層22形成在字元線16之寬度方向兩端之下方。如此可以自我對齊(self-alignment)字元線16的方式來製作電荷儲存層22。參見第7A至7C圖，字元線16是由第一導體層34以及第二導體層36所形成，其中，第二導體層36是形成在第一導體層34的寬度方向的兩個側面。閘極絕緣薄膜18係形成在第一導體層34的下方，而電荷儲存層22則是形成在第二導體層36的下方。如此可藉由控制第二導體層之厚度而避免電荷儲存層22的尺寸之增加。Referring to FIGS. 8A to 8C, using the word line 16 as a mask, the charge storage layer 22 is removed by etching so that the charge storage layer 22 is formed below both ends in the width direction of the word line 16. The charge storage layer 22 can thus be fabricated in a manner that self-aligns the word lines 16. Referring to FIGS. 7A to 7C, the word line 16 is formed of the first conductor layer 34 and the second conductor layer 36, wherein the second conductor layer 36 is formed on both sides in the width direction of the first conductor layer 34. The gate insulating film 18 is formed under the first conductor layer 34, and the charge storage layer 22 is formed under the second conductor layer 36. Thus, an increase in the size of the charge storage layer 22 can be avoided by controlling the thickness of the second conductor layer.
參見第1圖，電荷儲存層22係形成在字元線16的兩端之下。相較於電荷儲存層形成在閘極電極之側表面上的情形，此結構可以如預期地從字元線16施加電場。如此可更有效率地在電荷儲存層22中儲存電荷。Referring to FIG. 1, a charge storage layer 22 is formed under both ends of the word line 16. This structure can apply an electric field from the word line 16 as expected, as compared to the case where the charge storage layer is formed on the side surface of the gate electrode. This makes it possible to store charges in the charge storage layer 22 more efficiently.
參見第6A至6C圖，在第二凹槽32內填入第一導體層34，然後利用第一導體層34以及遮罩層30作為遮罩，蝕刻絕緣薄膜14。如此可減少絕緣薄膜14從頂部絕緣薄膜24突出的量。因為此，如第7A至7C圖所示，當沈積第二導體層36以實質覆蓋第一導體層34的時候，形成在絕緣薄膜14側表面上之第二導體層36的高度便可以降低。在接下來實質上蝕刻第二導體層36的步驟，很有可能會移除掉形成在絕緣薄膜14側面上的第二導體層36，因此可避免第二導體層36仍然殘留在絕緣薄膜14的側面上。舉例來說，如果第二導體層36仍然殘留在絕緣薄膜14的側面上，相鄰的字元線16將會被電氣耦合。因此根據一實施例的製造方法，其能夠避免相鄰字元線16發生電氣耦合。Referring to FIGS. 6A to 6C, the first conductor layer 34 is filled in the second recess 32, and then the insulating film 14 is etched by using the first conductor layer 34 and the mask layer 30 as a mask. This can reduce the amount by which the insulating film 14 protrudes from the top insulating film 24. Because of this, as shown in Figs. 7A to 7C, when the second conductor layer 36 is deposited to substantially cover the first conductor layer 34, the height of the second conductor layer 36 formed on the side surface of the insulating film 14 can be lowered. In the subsequent step of substantially etching the second conductor layer 36, it is highly possible to remove the second conductor layer 36 formed on the side of the insulating film 14, thereby preventing the second conductor layer 36 from remaining on the insulating film 14. On the side. For example, if the second conductor layer 36 remains on the side of the insulating film 14, adjacent word lines 16 will be electrically coupled. Thus, in accordance with an embodiment of the fabrication method, it is possible to avoid electrical coupling of adjacent word lines 16 .
參見第2A至2C圖，絕緣薄膜14係經形成為其上表面會齊平於遮罩層30的上表面。舉例來說，在絕緣薄膜14的上表面低於遮罩層30的上表面的情形中，在形成第一導體層34來填入第二凹槽32的步驟中(如第5A至5C圖所示)，可能會將第一導體層34形成為於絕緣薄膜14上方延伸於第一凹槽12的延伸方向。在上述的例子，相鄰的第一導體層34可能會發生電氣耦合。也就是說，相鄰的字元線16可能會發生電氣耦合。然而根據一實施例的製造方法，係將絕緣薄膜14形成為使其上表面齊平於遮罩層30的上表面。如此可避免將第一導體層34形成為於絕緣薄膜14的上方延伸於第一凹槽12的延伸方向。如此便可避免相鄰的字元線16發生電氣耦合。Referring to FIGS. 2A to 2C, the insulating film 14 is formed such that its upper surface is flush with the upper surface of the mask layer 30. For example, in the case where the upper surface of the insulating film 14 is lower than the upper surface of the mask layer 30, in the step of forming the first conductor layer 34 to fill the second groove 32 (as shown in FIGS. 5A to 5C) The first conductor layer 34 may be formed to extend over the insulating film 14 in the extending direction of the first groove 12. In the above example, adjacent first conductor layers 34 may be electrically coupled. That is, adjacent word lines 16 may be electrically coupled. However, according to the manufacturing method of an embodiment, the insulating film 14 is formed such that its upper surface is flush with the upper surface of the mask layer 30. Thus, the formation of the first conductor layer 34 to extend over the insulating film 14 in the extending direction of the first groove 12 can be avoided. This avoids electrical coupling between adjacent word lines 16.
參見第3A至3C圖，第二凹槽32的下表面是位於半導體基板10上表面的上方。如此可避免要被填入第二凹槽32的第一導體層34接觸到半導體基板10，如第5A至5C圖所示。也就是說，可避免字元線16以及半導體基板10互相接觸，而發生電氣耦合。如第3A至3C圖所示，以暴露出電荷儲存層22的表面之方式形成第二凹槽32。於是在形成閘極絕緣薄膜18的步驟裡，便能輕易氧化電荷儲存層22，如第4A至4C圖所示。Referring to FIGS. 3A to 3C, the lower surface of the second recess 32 is located above the upper surface of the semiconductor substrate 10. This prevents the first conductor layer 34 to be filled in the second recess 32 from contacting the semiconductor substrate 10 as shown in Figs. 5A to 5C. That is, the word line 16 and the semiconductor substrate 10 can be prevented from contacting each other, and electrical coupling occurs. As shown in FIGS. 3A to 3C, the second groove 32 is formed in such a manner as to expose the surface of the charge storage layer 22. Thus, in the step of forming the gate insulating film 18, the charge storage layer 22 can be easily oxidized as shown in Figs. 4A to 4C.
根據一實施例的前述方法所製造的NAND型快閃記憶體中，在字元線之寬度方向中心處的閘極絕緣薄膜18的上方之字元線16的高度，可能會和位於絕緣薄膜14上方之字元線16的高度不同。字元線16在寬度方向之中心處的高度係不同於字元線16在絕緣薄膜14上方、在寬度方向之每一端的高度。In the NAND type flash memory manufactured by the foregoing method of the embodiment, the height of the word line 16 above the gate insulating film 18 at the center in the width direction of the word line may be located at the insulating film 14. The height of the upper character line 16 is different. The height of the word line 16 at the center of the width direction is different from the height of the word line 16 above the insulating film 14 at each end in the width direction.
在另一實施例之NAND型快閃記憶體中，係採用實質上相同的材料來形成電荷儲存層22及遮罩層30。以下參照第9A至10B圖說明製造另一實施例之快閃記憶體的方法。第9A至10B圖為例示性剖視圖，其分別對應於沿第2圖B-B線所取之剖面。In another embodiment of the NAND type flash memory, the charge storage layer 22 and the mask layer 30 are formed using substantially the same material. A method of manufacturing a flash memory of another embodiment will be described below with reference to Figs. 9A to 10B. 9A to 10B are exemplary cross-sectional views respectively corresponding to the cross-section taken along line B-B of Fig. 2.
進行如參照第2A至3C圖敘述的製造步驟，而採用氮化矽薄膜來製作電荷儲存層22。參見第9A圖，形成在第二凹槽32下方的電荷儲存層22係藉由自由基氧化(radical oxidation)製程或是電漿氧化製程來氧化，以形成閘極絕緣薄膜18。由於是採用氮化矽薄膜來形成電荷儲存層22與遮罩層30，故將遮罩層30的上表面與側面兩者予以氧化，以形成氧化物薄膜層38。The manufacturing process described with reference to FIGS. 2A to 3C is performed, and the charge storage layer 22 is formed using a tantalum nitride film. Referring to FIG. 9A, the charge storage layer 22 formed under the second recess 32 is oxidized by a radical oxidation process or a plasma oxidation process to form a gate insulating film 18. Since the charge storage layer 22 and the mask layer 30 are formed using a tantalum nitride film, both the upper surface and the side surface of the mask layer 30 are oxidized to form the oxide thin film layer 38.
參見第9B圖，形成第一導體層34來填入第二凹槽32。參照第9C圖，藉由RIE製程或是濕蝕刻製程(例如，使用氟酸(fluorinated acid))來移除氧化物薄膜38，以暴露出第一導體層34的側面。Referring to Figure 9B, a first conductor layer 34 is formed to fill the second recess 32. Referring to FIG. 9C, the oxide film 38 is removed by an RIE process or a wet etching process (for example, using fluorinated acid) to expose the side surface of the first conductor layer 34.
參見第10A圖，移除遮罩層30並在第一導體層34之寬度方向兩側面上形成第二導體層36，以形成字元線16，其中字元線16係包含第一導體層34以及第二導體層36。參見第10B圖，利用字元線16作為遮罩，以蝕刻的方式移除頂部絕緣薄膜24以及電荷儲存層22。之後，在第一凹槽12之間，在字元線16之寬度方向兩側的半導體基板10內製作擴散區域26，以作為源極區域以及汲極區域兩者。Referring to FIG. 10A, the mask layer 30 is removed and a second conductor layer 36 is formed on both sides in the width direction of the first conductor layer 34 to form a word line 16, wherein the word line 16 includes the first conductor layer 34. And a second conductor layer 36. Referring to FIG. 10B, the top insulating film 24 and the charge storage layer 22 are removed by etching using the word line 16 as a mask. Thereafter, a diffusion region 26 is formed between the first grooves 12 in the semiconductor substrate 10 on both sides in the width direction of the word line 16 as both the source region and the drain region.
在根據另一實施例的製造方法中，採用實質上類似的材料來製作電荷儲存層22與遮罩層30。如第9A圖，於實施藉由氧化電荷儲存層22以製作出閘極絕緣薄膜18的步驟中，氧化物薄膜38會形成在遮罩層30的上表面與側面。如第9C圖，於第二凹槽32中形成第一導體層34之後，除去氧化物薄膜38以暴露出第一導體層34的側面。如第10A圖，第一導體層34可與形成在第一導體層34兩側面上的第二導體層36發生電氣耦合。考慮到第一導體層34與第二導體層36之間電氣耦合的關係，較佳的作法為移除氧化物的薄膜38，以暴露出第一導體層34側面的一半或者是一半以上。In a fabrication method in accordance with another embodiment, the charge storage layer 22 and the mask layer 30 are fabricated using substantially similar materials. As shown in FIG. 9A, in the step of forming the gate insulating film 18 by oxidizing the charge storage layer 22, the oxide film 38 is formed on the upper surface and the side surface of the mask layer 30. As shown in FIG. 9C, after the first conductor layer 34 is formed in the second recess 32, the oxide film 38 is removed to expose the side surface of the first conductor layer 34. As shown in FIG. 10A, the first conductor layer 34 can be electrically coupled to the second conductor layer 36 formed on both sides of the first conductor layer 34. In view of the electrical coupling relationship between the first conductor layer 34 and the second conductor layer 36, it is preferred to remove the oxide film 38 to expose half or more of the sides of the first conductor layer 34.
在透過前述方法所製造之另一實施例的NAND型快閃記憶體中，在第一導體層34與第二導體層36之間形成有氧化物薄膜38。換言之，氧化物薄膜38是形成在字元線16內，而從閘極絕緣薄膜18在字元線16的寬度方向兩側突出。In the NAND type flash memory of another embodiment manufactured by the above method, an oxide film 38 is formed between the first conductor layer 34 and the second conductor layer 36. In other words, the oxide film 38 is formed in the word line 16 and protrudes from the gate insulating film 18 on both sides in the width direction of the word line 16.
根據本發明的一個面向，提供一種用來製造半導體裝置的方法，其包括下列步驟：在半導體基板上形成電荷儲存層；利用形成在電荷儲存層上的遮罩層作為遮罩，而在電荷儲存層與半導體基板內形成延伸的第一凹槽；形成欲填入第一凹槽內的絕緣薄膜；在遮罩層與絕緣薄膜內形成延伸跨過第一凹槽的第二凹槽；藉由氧化形成在第二凹槽下方的電荷儲存層，形成閘極絕緣薄膜；形成欲填入第二凹槽的第一導體層；移除遮罩層；在第一導體層於寬度方向的兩側面上形成第二導體層，以形成包含第一和第二導體層的字元線；以及利用字元線作為遮罩來移除電荷儲存層。本方法可製作在記憶體單元內部於通道方向被分隔、並且在兩相鄰記憶體單元之間被進一步分隔的電荷儲存層。本方法還能以自我對齊字元線的方式來製作電荷儲存層。According to an aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming a charge storage layer on a semiconductor substrate; using a mask layer formed on the charge storage layer as a mask, and storing the charge Forming an extended first groove in the layer and the semiconductor substrate; forming an insulating film to be filled in the first groove; forming a second groove extending across the first groove in the mask layer and the insulating film; Oxidizing a charge storage layer formed under the second recess to form a gate insulating film; forming a first conductor layer to be filled in the second recess; removing the mask layer; on both sides of the first conductor layer in the width direction A second conductor layer is formed over to form word lines including the first and second conductor layers; and the charge storage layer is removed using the word lines as a mask. The method can produce a charge storage layer that is separated inside the memory cell in the channel direction and further separated between two adjacent memory cells. The method can also fabricate a charge storage layer by self-aligning the word lines.
本方法包括：在施行形成第一導體層的步驟之後，利用第一導體層與遮罩層作為遮罩蝕刻絕緣薄膜的步驟。如此可抑制相鄰的字元線發生電氣耦合。The method includes the step of etching the insulating film using the first conductor layer and the mask layer as a mask after the step of forming the first conductor layer. This can suppress the electrical coupling of adjacent word lines.
在本方法之形成絕緣薄膜的步驟中，絕緣薄膜係成為使其上表面齊平於遮罩層的上表面。如此可抑制相鄰的字元線發生電氣耦合。In the step of forming the insulating film of the present method, the insulating film is formed such that its upper surface is flush with the upper surface of the mask layer. This can suppress the electrical coupling of adjacent word lines.
在本方法之形成第二凹槽的步驟中，第二凹槽係形成為使其下表面位於半導體基板上表面的上方。如此可避免字元線與半導體基板互相接觸，造成電氣耦合。In the step of forming the second recess of the method, the second recess is formed such that its lower surface is located above the upper surface of the semiconductor substrate. This prevents the word lines from contacting the semiconductor substrate, resulting in electrical coupling.
在本方法之形成第二凹槽的步驟中，第二凹槽係製作成可暴露出電荷的儲存層。如此在形成閘極絕緣薄膜的步驟裡，可輕易地氧化電荷儲存層。In the step of forming the second recess of the method, the second recess is formed as a storage layer that exposes the charge. Thus, in the step of forming the gate insulating film, the charge storage layer can be easily oxidized.
在本方法尚包括在半導體基板內部製作擴散區域的步驟，其利用字元線以及絕緣薄膜來作為遮罩。The method further includes the step of forming a diffusion region inside the semiconductor substrate, which uses a word line and an insulating film as a mask.
在本方法中，形成閘極絕緣薄膜的步驟係包含在遮罩層的上表面與側面雙方上形成氧化物薄膜的步驟。於施行過形成第一導體層的步驟之後，實施移除氧化物薄膜的步驟，以暴露出第一導體層之側面。當採用實質上類似的材料來製作電荷儲存層與遮罩層時，如此可將第一導體層與第二導體層予以電氣耦合。In the method, the step of forming the gate insulating film includes the step of forming an oxide film on both the upper surface and the side surface of the mask layer. After the step of forming the first conductor layer is performed, a step of removing the oxide film is performed to expose the side surface of the first conductor layer. When a substantially similar material is used to form the charge storage layer and the mask layer, the first conductor layer and the second conductor layer can be electrically coupled in this manner.
根據本發明的另一面向，提出一種半導體裝置，包括：半導體基板，其具有延伸的第一凹槽；絕緣薄膜，被填入第一凹槽內並突出在半導體基板上表面的上方；字元線，形成在半導體裝置上，並且延伸跨過第一凹槽；閘極絕緣薄膜，係形成在半導體基板上並位於字元線之寬度方向中心下方，並且在字元線的延伸的方向由絕緣薄膜分隔；以及電荷儲存層，係形成在半導體基板上並位於字元線之寬度方向兩端下方，並且於其間插進有閘極絕緣薄膜，以便在字元線的延伸方向由絕緣薄膜分隔。此結構提供在記憶體單元內部於通道方向被分隔、並且在兩相鄰記憶體單元之間被進一步分隔的電荷儲存層。According to another aspect of the present invention, a semiconductor device includes: a semiconductor substrate having an extended first recess; an insulating film filled in the first recess and protruding above the upper surface of the semiconductor substrate; a wire formed on the semiconductor device and extending across the first recess; the gate insulating film is formed on the semiconductor substrate and located below the center of the width direction of the word line, and is insulated by the direction of extension of the word line The film is divided; and the charge storage layer is formed on the semiconductor substrate and located below both ends in the width direction of the word line, and a gate insulating film is interposed therebetween so as to be separated by the insulating film in the extending direction of the word line. This structure provides a charge storage layer that is separated inside the memory cell in the channel direction and further separated between two adjacent memory cells.
本結構中，字元線在閘極絕緣薄膜上方的高度，可能會和字元線在絕緣薄膜上方的高度不同，其中閘極絕緣薄膜是位於字元線寬度方向的中心處。In this structure, the height of the word line above the gate insulating film may be different from the height of the word line above the insulating film, wherein the gate insulating film is located at the center of the width direction of the word line.
本結構包括位於字元線內的氧化物薄膜，其係從閘極絕緣薄膜之在字元線寬度方向的兩端突出。The structure includes an oxide film in the word line which protrudes from both ends of the gate insulating film in the width direction of the word line.
以上描述雖然是本發明的較佳實施例，但是本發明並不侷限於這些特定的實施例，在由專利申請範圍所定義的本發明之精神與範圍內，可採取別種作法與進行各樣的變更。The above description is a preferred embodiment of the present invention, but the present invention is not limited to the specific embodiments, and various other methods and various modifications can be made within the spirit and scope of the invention as defined by the scope of the patent application. change.
10．．．半導體基板10. . . Semiconductor substrate
12．．．第一凹槽12. . . First groove
14．．．絕緣薄膜14. . . Insulating film
16．．．字元線16. . . Word line
18．．．閘極絕緣薄膜18. . . Gate insulating film
20．．．隧道絕緣薄膜20. . . Tunnel insulation film
22．．．電荷儲存層twenty two. . . Charge storage layer
24．．．頂部絕緣薄膜twenty four. . . Top insulating film
25．．．層疊層25. . . Laminated layer
26．．．擴散區域26. . . Diffusion zone
30．．．遮罩層30. . . Mask layer
32．．．第二凹槽32. . . Second groove
34．．．第一導體層34. . . First conductor layer
36．．．第二導體層36. . . Second conductor layer
38．．．氧化物薄膜層38. . . Oxide film layer
第1圖是根據一實施例之NAND型快閃記憶體的例示性透視圖。1 is an exemplary perspective view of a NAND type flash memory according to an embodiment.
第2A圖的例示性透視圖展示一種方法，用來製作根據一實施例的NAND型快閃記憶體。An exemplary perspective view of FIG. 2A shows a method for fabricating a NAND type flash memory in accordance with an embodiment.
第2B與2C圖是根據一實施例，沿著第2A圖中B-B與C-C直線所取的例示性剖面圖。2B and 2C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 2A, according to an embodiment.
第3A圖的例示性透視圖展示一種方法，用來製作根據一實施例的NAND型快閃記憶體。An exemplary perspective view of Figure 3A shows a method for fabricating a NAND type flash memory in accordance with an embodiment.
第3B與3C圖是根據一實施例，沿著第3A圖中B-B與C-C直線所取的例示性剖面圖。3B and 3C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 3A, according to an embodiment.
第4A圖的例示性透視圖展示一種方法，用來製作根據一實施例的NAND型快閃記憶體。An exemplary perspective view of FIG. 4A shows a method for fabricating a NAND type flash memory in accordance with an embodiment.
第4B與4C圖是根據一實施例，沿第4A圖中B-B與C-C直線所取的例示性剖面圖。4B and 4C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 4A, according to an embodiment.
第5A圖的例示性透視圖展示一種方法，用來製作根據一實施例的NAND型快閃記憶體。An exemplary perspective view of Figure 5A shows a method for fabricating a NAND type flash memory in accordance with an embodiment.
第5B與5C圖是根據一實施例，沿著第5A圖中B-B與C-C直線所取的例示性剖面圖。5B and 5C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 5A, according to an embodiment.
第6A圖的例示性透視圖展示一種方法，用來製作根據一實施例的NAND型快閃記憶體。An exemplary perspective view of Figure 6A shows a method for fabricating a NAND type flash memory in accordance with an embodiment.
第6B與6C圖是根據一實施例，沿著第6A圖中B-B與C-C直線所取的例示性剖面圖。6B and 6C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 6A, according to an embodiment.
第7A圖的例示'性透視圖展示一種方法，用來製作根據一實施例的NAND型快閃記憶體。The exemplified 'Sensual Perspective' of Figure 7A shows a method for fabricating a NAND type flash memory in accordance with an embodiment.
第7B與7C圖是根據一實施例，沿著第7A圖中B-B與C-C直線所取的例示性剖面圖。Figures 7B and 7C are exemplary cross-sectional views taken along lines B-B and C-C of Figure 7A, in accordance with an embodiment.
第8A圖的例示性透視圖展示一種方法，用來製作根據一實施例的NAND型快閃記憶體。An exemplary perspective view of Fig. 8A shows a method for fabricating a NAND type flash memory in accordance with an embodiment.
第8B與8C圖是根據一實施例，沿著第8A圖中B-B與C-C直線所取的例示性剖面圖。8B and 8C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 8A, according to an embodiment.
第9A至9C圖的例示性剖面圖展示一種方法，用來製作根據另一實施例的NAND型快閃記憶體，每張圖相當於沿著第2圖中B-B直線所取的剖面。The exemplary cross-sectional views of Figs. 9A through 9C show a method for fabricating a NAND type flash memory according to another embodiment, each of which corresponds to a section taken along the line B-B in Fig. 2.
第10A與10B圖的例示性剖面圖展示一種方法，用來製作根據另一實施例的NAND型快閃記憶體，每張圖相當於沿著第2圖中B-B直線所取的剖面。The exemplary cross-sectional views of Figs. 10A and 10B show a method for fabricating a NAND type flash memory according to another embodiment, each of which corresponds to a section taken along the line B-B in Fig. 2.
10．．．半導體基板10. . . Semiconductor substrate
12．．．第一凹槽12. . . First groove
14．．．絕緣薄膜14. . . Insulating film
16．．．字元線16. . . Word line
18．．．閘極絕緣薄膜18. . . Gate insulating film
20．．．隧道絕緣薄膜20. . . Tunnel insulation film
22．．．電荷儲存層twenty two. . . Charge storage layer
24．．．頂部絕緣薄膜twenty four. . . Top insulating film
25．．．層疊層25. . . Laminated layer
26．．．擴散區域26. . . Diffusion zone
Claims (10)
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| JP2007308094A JP5491694B2 (en) | 2007-11-28 | 2007-11-28 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030032243A1 (en) * | 2001-08-13 | 2003-02-13 | Seiki Ogura | Twin NAND device structure, array operations and fabrication method |
| US20030160280A1 (en) * | 2002-02-27 | 2003-08-28 | Akira Yoshino | Nonvolatile semiconductor memory device, manufacturing method thereof, and operating method thereof |
| US20040197995A1 (en) * | 2003-04-01 | 2004-10-07 | Lee Yong-Kyu | Method of manufacturing twin-ONO-type SONOS memory using reverse self-alignment process |
| US20060202263A1 (en) * | 2005-03-14 | 2006-09-14 | Chang-Hyun Lee | Nonvolatile semiconductor memory device and method of fabricating the same |
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| JP3233998B2 (en) * | 1992-08-28 | 2001-12-04 | 株式会社東芝 | Manufacturing method of nonvolatile semiconductor memory device |
| JP4834897B2 (en) * | 2000-05-02 | 2011-12-14 | ソニー株式会社 | Nonvolatile semiconductor memory device and operation method thereof |
| JP3983094B2 (en) * | 2002-04-25 | 2007-09-26 | Ｎｅｃエレクトロニクス株式会社 | Method for manufacturing nonvolatile semiconductor memory device |
| JP4041076B2 (en) * | 2004-02-27 | 2008-01-30 | 株式会社東芝 | Data storage system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030032243A1 (en) * | 2001-08-13 | 2003-02-13 | Seiki Ogura | Twin NAND device structure, array operations and fabrication method |
| US20030160280A1 (en) * | 2002-02-27 | 2003-08-28 | Akira Yoshino | Nonvolatile semiconductor memory device, manufacturing method thereof, and operating method thereof |
| US20040197995A1 (en) * | 2003-04-01 | 2004-10-07 | Lee Yong-Kyu | Method of manufacturing twin-ONO-type SONOS memory using reverse self-alignment process |
| US20060202263A1 (en) * | 2005-03-14 | 2006-09-14 | Chang-Hyun Lee | Nonvolatile semiconductor memory device and method of fabricating the same |
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| WO2009070336A1 (en) | 2009-06-04 |
| JP5491694B2 (en) | 2014-05-14 |
| JP2009135155A (en) | 2009-06-18 |
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