JP2004319586A - Nonvolatile semiconductor storage device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device provided with floating electrodes having good charge holding characteristics. <P>SOLUTION: In the nonvolatile semiconductor storage device, an insulating slit 18A is formed between the floating electrodes 18 of two nonvolatile storage elements adjoining each other with an element isolation region 17 in between, and a slit insulating layer 19-2 is embedded in the slit 18A. In addition, a control electrode 20 is formed astride the floating electrodes 18 of the adjoining nonvolatile storage elements through the slit insulating layer 19-2 and an inter-electrode insulating film 19-1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile semiconductor memory device having a slit insulated by an insulating film between floating electrodes of adjacent nonvolatile memory elements.
[0002]
[Prior art]
As a conventional nonvolatile semiconductor memory device having a floating electrode, there is one as shown in FIG. 17 (for example, see Patent Document 1). The nonvolatile semiconductor memory device shown in FIG. 17 includes a silicon substrate 111, a gate oxide film 112, a first polycrystalline silicon film 113 serving as a lower floating electrode, a silicon oxide film 116, and an STI filling material for an element isolation region. A certain silicon oxide film 117, a second polycrystalline silicon film 118 serving as an upper floating electrode, an ONO insulating film (a three-layer film of a silicon oxide film, a silicon nitride film, and a silicon oxide film) 119, and a lower control electrode. It comprises a third polycrystalline silicon film 120, a WSi film 121 serving as an upper control electrode, and a silicon oxide film 122 serving as an insulating protective film.
[0003]
The first polycrystalline silicon film 113, which is a lower floating electrode, is insulated from the corresponding lower floating electrode of an adjacent cell by the silicon oxide films 116, 117 in the element isolation region, and the second, which is an upper floating electrode. The polycrystalline silicon film 118 is separated from the corresponding upper floating electrode of the adjacent cell by a slit 126 on the silicon oxide film 117. The floating electrode 118 and the control electrode 120 are insulated by an ONO insulating film 119 which is an inter-electrode insulating film.
[0004]
However, the conventional nonvolatile semiconductor memory device has a structure in which the control electrode 120 and the ONO insulating film 119 enter the slit 126 between the adjacent cells at the floating electrode corner 125.
[0005]
As a result, an electric field concentrates on the floating electrode corner 125, and the insulation characteristics of the ONO insulating film 119 at the corner 125 deteriorate. Therefore, the charge retention characteristics injected into the floating electrodes 113 and 118 corresponding to the stored information are reduced. There was a problem of bad.
[0006]
[Patent Document 1]
JP, 2002-016154, A
[0007]
[Problems to be solved by the invention]
As described above, the conventional nonvolatile semiconductor memory device has a structure in which a control electrode enters into an insulating slit between floating electrodes of adjacent cells on an element isolation region.
[0008]
Therefore, an electric field is concentrated at the corner of the floating electrode in the slit, and there is a problem that the charge retention characteristics of stored information are poor.
[0009]
The present invention has been made in view of the above circumstances, and has as its object to provide a nonvolatile semiconductor memory device having good charge retention characteristics and a method of manufacturing the same.
[0010]
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of nonvolatile memory elements formed in element regions each separated by an element isolation region on a main surface of a semiconductor substrate of a first conductivity type; Each of the nonvolatile memory elements includes a gate insulating film formed on a main surface of the semiconductor substrate, a plurality of floating electrodes formed on the gate insulating film along a first direction, and a floating electrode. A second conductivity type impurity diffusion region formed along the second direction so as to sandwich the control electrode, and a control electrode formed on the plurality of floating electrodes via an inter-electrode insulating film; A plurality of slits are formed between a plurality of floating electrodes adjacent to each other along a direction, and a slit insulating layer is embedded in each of the plurality of slits. The first through the layer Along to be formed across the floating electrode of the plurality of nonvolatile storage elements adjacent along said first direction to direction, configured as characterized.
[0011]
According to another aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising: forming first and second element formation regions separated by an element isolation region on a main surface of a semiconductor substrate of a first conductivity type; First and second gate insulating films are respectively formed in first and second element forming regions, and are respectively formed on the first and second gate insulating films while being separated by slits on the element separating regions. First and second floating electrodes are formed, and a slit insulating layer having substantially the same thickness as the first and second floating electrodes is formed in the slit. An inter-electrode insulating film is formed on the second floating electrode, and a common control electrode is formed on the inter-electrode insulating film over the first and second floating electrodes.
[0012]
According to the above configuration, the control electrode does not enter the slit between the adjacent floating electrodes. Therefore, an electric field is not concentrated on the corner of the floating electrode in the slit, and a nonvolatile semiconductor memory device with good charge retention and a method for manufacturing the same can be provided.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment in which the present invention is applied to a nonvolatile semiconductor memory device having a floating electrode formed on a main surface of a silicon substrate will be described below with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings.
[0014]
[First Embodiment]
Hereinafter, a nonvolatile semiconductor memory device having a floating electrode according to the first embodiment of the present invention will be described with reference to FIGS. Here, FIG. 1 is a sectional view taken along line II in the plan view of FIG. FIG. 2 is a sectional view taken along line II-II in the plan view of FIG. 3 and viewed in the direction of the arrow. FIG. 3 is a plan view of the nonvolatile semiconductor memory device according to one embodiment of the present invention.
[0015]
As shown in FIG. 1, a silicon oxide film 12 serving as a gate insulating film and a polycrystalline silicon film 13 serving as a first floating electrode layer are formed on a main surface of a silicon substrate 11 by STI trenches forming element isolation regions. The silicon oxide films 16 are sequentially laminated while being separated by the outer wall of the silicon oxide film 16 formed inside 17A. The inside of the STI trench 17A surrounded by the silicon oxide film 16 is filled with a silicon oxide film 17 as an STI filling material.
[0016]
On the polycrystalline silicon film 13, a polycrystalline silicon film 18 is formed as a second floating electrode layer. This polycrystalline silicon film 18 is separated by a slit 18A at a substantially central portion of the upper surface of the silicon oxide film 17 as the STI filling material. In the slit 18A and on the polycrystalline silicon oxide film 18 serving as the second floating electrode layer, an ONO insulating film (a silicon oxide film, a silicon nitride film, and a silicon oxide film) is formed as an interelectrode insulating film. ) 19-1 is deposited.
[0017]
On this ONO insulating film 19-1, a polycrystalline silicon film 20 serving as a first control electrode layer and a WSi film 21 serving as a second control electrode layer are sequentially formed. As shown in FIG. 3, the first and second control electrode layers 20 and 21 form control electrodes CG <0> and CG <1>.
[0018]
As shown in FIGS. 2 and 3, a silicon oxide film 12 serving as a gate insulating film and a polycrystalline silicon film 13 serving as a first floating electrode layer are formed on a main surface of a silicon substrate 11 by a silicon oxide film 17. It is formed in an isolated element region. In the silicon substrate 11 under the silicon oxide film 12, impurity diffusion layers 24-1, 24-2, and 24-3 serving as a source region and a drain region are formed across adjacent polycrystalline silicon films 13. You.
[0019]
On the polycrystalline silicon film 13, a polycrystalline silicon film 18 is formed as a second floating electrode layer. On the polycrystalline silicon film 18, an ONO insulating film (consisting of three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film) 19-1 is deposited as an inter-electrode insulating film. The two nonvolatile memory elements MC <01> and MC <11> adjacent to these polycrystalline silicon films 13 and 18 form floating electrodes FG <01> and FG <11> having a two-layer structure, respectively.
[0020]
On this ONO insulating film 19-1, a polycrystalline silicon film 20 serving as a first control electrode layer and a WSi film 21 serving as a second control electrode layer are sequentially formed. Similarly, control electrodes CG <0> and CG <1> of two adjacent nonvolatile memory elements MC <01> and MC <11> are formed by the first and second control electrode layers 20 and 21. . Gate side wall insulating films 23 are formed on the side surfaces of the nonvolatile memory elements MC <00> to MC <11> including these, and a silicon oxide film 22 is formed on the upper surface, respectively.
[0021]
Here, a plan layout of the nonvolatile semiconductor memory device of this embodiment having the cross-sectional structure shown in FIGS. 1 and 2 will be described with reference to the plan view of FIG. That is, a plurality of non-volatile semiconductors formed along the control electrodes CG <0> and CG <1> are formed in the element formation region separated from the silicon substrate 11 by the silicon oxide film 17 (STI filling material) serving as the element isolation film. A nonvolatile semiconductor memory device having storage elements MC <00> to MC <11> is formed. Here, MC is a nonvolatile memory element, CG is a control electrode, FG is a floating electrode, and <nm> (nm: integer) represents <row, column> in the matrix arrangement of MC. FIG. 3 shows four nonvolatile memory elements MC <00> to MC <11>.
[0022]
Further, a silicon oxide film 12 serving as a gate insulating film is formed on the silicon substrate 11, straddles between the floating electrodes FG of the adjacent nonvolatile memory elements below the silicon oxide film 12, and controls the control electrodes CG <0> and CG < Impurity diffusion layers 24-1, 24-2, and 24-3 to be source and drain are formed in a direction orthogonal to 1>.
[0023]
Further, the nonvolatile memory elements MC <00> to MC <11> have floating electrodes FG <00> to FG <11> and control electrodes CG <0> and CG <1>, respectively.
[0024]
The floating electrodes FG <00> to FG <11> are formed in the regions of the nonvolatile memory elements MC <00> to MC <11>, respectively, and a polycrystalline silicon film is formed on the silicon oxide film 12 serving as a gate insulating film. 13 and the polycrystalline silicon film 18.
[0025]
Between the floating electrodes FG <00> to FG <11> and the control electrodes CG <0> and CG <1>, ONO insulating films 19-1 <0> and 19-1 <1 serving as inter-electrode insulating films. > Is formed.
[0026]
On the other hand, the control electrode CG includes a polycrystalline silicon film 20 and a WSi film 21. That is, the control electrode CG <0> is formed above the floating electrodes FG <00> and FG <01> via the inter-electrode insulating film 19-1 <0>. Similarly, the control electrode CG <1> is formed above the floating electrodes FG <10> and FG <11> via the inter-electrode insulating film 19-1 <1>.
[0027]
A slit 18A <0> is formed between the floating electrodes FG <00> and FG <01> adjacent to each other along the control electrode CG <0>. Similarly, a slit 18A <1> is formed between the floating electrodes FG <10> and FG <11> adjacent to each other along the control electrode CG <1>.
[0028]
As shown in FIG. 1, an ONO insulating film 19-2 is formed inside the slit 18A, and is formed so as to completely fill the slit 18A between the floating electrodes 18 adjacent to each other along the control electrode CG. . For example, an ONO insulating film 19-2 <0> is formed inside the slit 18A <0>, and an ONO insulating film 19-2 <1> is similarly formed inside the slit 18A <1>.
[0029]
With the above configuration, the inter-electrode insulating film ONO insulating film 19-1 completely fills and fills the inside of the slit 18A. Therefore, the control electrode CG formed above the inter-electrode insulating film ONO insulating film 19-1 does not enter the inside of the slit 18A.
[0030]
Next, the operation of each element will be described using the case of the nonvolatile memory element MC <11> as an example.
[0031]
The write operation will be described. First, the silicon substrate 11 is set to the ground potential. Then, a high voltage is applied between the impurity diffusion layers 24-2 and 24-3 to be source and drain regions. For example, when the impurity diffusion layer 24-2 is a source region and the impurity diffusion layer 24-3 is a drain region, a ground potential is applied to the impurity diffusion layer 24-2 of the source region, and an impurity diffusion layer 24-3 of the drain region is provided. A certain high potential is applied.
[0032]
Further, when a high potential is applied to the control electrode CG <1>, hot electrons generated by the high potential applied between the source and the drain, that is, between the impurity diffusion layers 24-2 to 24-3, generate control electrons CG <1>. The high voltage of 1> is injected into the floating electrode FG <11>. Alternatively, an FN current is generated by the high voltage of the control electrode CG <1>, and electrons are injected into the floating electrode FG <11>.
[0033]
Thus, the nonvolatile memory element MC <11> is selectively written. Further, the electrons injected into the floating electrode FG <11> are kept as they are. Therefore, the written information is maintained without a rewrite operation.
[0034]
Next, a read operation will be described. First, the silicon substrate 11 is set to the ground potential. Then, the impurity diffusion layer 24-2 serving as the source region is also set to the ground potential. Further, a potential is applied to the impurity diffusion layer 24-3 serving as a drain region. Next, a voltage is applied to control electrode CG <1>. At this time, if electrons are injected into the floating electrode <11> of the nonvolatile memory element MC <11>, a channel is less likely to be formed between the source and the drain, and the threshold voltage increases. That is, the memory element MC <11> is turned off, and no current flows between the impurity diffusion layers 24-2 to 24-3 between the source and the drain.
[0035]
On the other hand, assuming that no electrons have been injected into the floating electrode <11>, a channel is easily formed between the source and the drain, a current flows, and the storage element MC <11> is turned on. In this manner, the presence / absence of a current in the drain region of the nonvolatile memory element MC <11>, that is, in the impurity diffusion layer 24-3, is read by a sense amplifier or the like connected to the memory element MC <11>. Read the information written in.
[0036]
Next, the erasing operation will be described. The erasing operation is a collective erasing of all the nonvolatile memory elements MC <00> to MC <11>. That is, a positive potential is applied to all the impurity diffusion layers 24 which are to be the drain region and the source region. Further, a negative potential is applied to all control electrodes CG <0> and CG <1>. As a result, the retained electrons are pulled out from all the floating electrodes FG <00> to FG <11> to the silicon substrate 11, and the storage information of the nonvolatile memory elements MC <00> to MC <11> is erased. The above operation is the same for the other nonvolatile memory elements MC <00>, MC <01>, and MC <10>.
[0037]
As described above, the ONO insulating film 19-2 is formed inside the slit 18A to be a groove of the floating electrode FG adjacent to the control electrode CG so as to completely fill the groove. With the above configuration, the interelectrode insulating film ONO insulating film 19-1 completely enters the inside of the slit 18A, and the slit 18A is embedded. Therefore, the control electrode CG formed above the inter-electrode insulating film ONO insulating film 19-1 does not enter the inside of the slit 18A. Thus, it is possible to prevent the electrons injected into the floating electrode FG after the writing operation from leaking to the control electrode CG due to the electric field concentration at the corner 25 of the floating electrode. That is, charge retention characteristics can be improved.
[0038]
As described above, according to this embodiment, no matter how wide the slit 18A is, the control electrode 20 does not hang down inside the slit 18A as in the related art. This can be prevented from occurring. Therefore, the charge retention characteristics of the nonvolatile memory element are significantly improved.
[0039]
In the embodiment shown in FIGS. 1 to 3, the slit insulating film 19-2 filling the inside of the slit 18 </ b> A is formed first, and then the inter-electrode insulation formed between the floating electrode 18 and the control electrode 20 is formed. It can be manufactured by a method of depositing the film 19-1, but when the slit insulating film 19-2 and the inter-electrode insulating film 19-1 are formed of the same ONO film, both can be formed simultaneously. It is.
[0040]
On the other hand, the width of the slit 18A is a factor that determines the interval between two adjacent nonvolatile memory elements. If the nonvolatile memory elements are to be arranged at a high density within a limited area, the width of the slit 18A is inevitably reduced. It is getting narrower.
[0041]
Even in such a case, in order to sufficiently exhibit the effect of the present embodiment, the width d of the slit 18A is required. _F And the thickness d of the inter-electrode insulating film 19-1 _ONO It is desirable that the following conditions be satisfied. This condition will be described with reference to FIG.
[0042]
FIG. 4 shows the slit width d against the charge retention characteristic failure rate. _F / Thickness d _ONO, 3 is a graph showing the dependence of the above. Here, the slit width d _F Is the distance between the slits 18A between the adjacent floating electrodes 18, and the film thickness d _ONO Is the thickness of the inter-electrode insulating film 19-1 deposited between the polycrystalline silicon film 20 and the polycrystalline silicon film 18.
[0043]
As shown in FIG. 4, for example, in a conventional nonvolatile semiconductor memory element having a structure as shown in FIG. _F / Thickness d _ONO = 4. Therefore, a charge retention characteristic defect rate of about 8% occurs.
[0044]
On the other hand, in the present embodiment, when the slit insulating film 19-2 and the inter-electrode insulating film 19-1 are simultaneously deposited with the same material, the slit width d _F / Thickness d _ONO It can be seen from FIG. 4 that it is desirable to be <1.6. In this case, the defect rate of the charge retention characteristics is almost 0%, and extremely good charge retention characteristics are exhibited.
[0045]
This inequality, slit width d _F / Thickness d _ONO <1.6 shows that the thickness d _ONO Slit width d using an insulating film having _F This is a condition under which the slit 18A having the above can be filled with the same insulating film.
[0046]
That is, in general, the film thickness in the slit width direction deposited on the slit 18A depends on the kind of the deposited insulating film, but the inter-electrode insulating film 19 deposited between the floating electrode 18 and the control electrode 20. The film thickness d which is −1 _ONO This is because it is about 1.6 times as large as. This is because the thickness of the inter-slit insulating film 19-2 deposited on the side surface of the floating electrode 18 is the same as that of the inter-electrode insulating film 19-1 deposited between the polycrystalline silicon film 18 and the polycrystalline silicon film 20. This is because the thickness is about 0.8 times as large as the thickness.
[0047]
On the other hand, when the inter-electrode insulating film 19-1 is ideally deposited on the side surface of the slit 18A, the thickness deposited on the upper surface of the floating electrode layer 18 is the same, and the slit width d _F Is the film thickness d _ONO It is thought that it becomes about 2.0 times. However, when actually deposited under these conditions, the slits are not completely filled, and a slight depression is formed on the surface of the inter-electrode insulating film 19-1. As a result, the control electrode enters the inside of the slit 18A as in the related art, and the electric field concentration occurs at the corner of the floating electrode. As a result, the conventional disadvantage that the charge retention characteristics are deteriorated due to the electric field concentration cannot be solved.
[0048]
However, the floating electrode slit width d _F Is the film pressure d _ONO If it is smaller than 1.6 times, the inside of the slit 18A is completely buried by, for example, the ONO insulating film 19, and the entry of the control electrode 20 into the slit 18A can be completely avoided. As a result, the control electrode 20 does not cover the corner portion 25 of the floating electrode, so that the electric field concentration is hardly generated, and the charge retention characteristics are improved.
[0049]
Further, according to this condition, an effect of suppressing variation in the threshold distribution for each cell, that is, for each nonvolatile memory element can be expected. That is, since the radius of curvature of the corner of the floating electrode on the side facing the control electrode differs for each cell, if the corner is used for holding charges, the writing / erasing speed also changes for each cell. As a result, the threshold distribution of each cell varies. However, in this embodiment, the floating electrode corner 25 is not used for holding electric charges, and only the flat insulating film is used for writing / erasing, so that the variation between cells is reduced.
[0050]
In this embodiment, the case where the ONO insulating film is used as the inter-electrode insulating film and the inter-slit insulating film has been described. Can obtain the same effect.
[0051]
Hereinafter, an example of a manufacturing process of the nonvolatile semiconductor memory device of the embodiment shown in FIGS. 1 to 3 will be described with reference to FIGS.
[0052]
First, referring to FIGS. 5A and 6A, an O.sub. ₂ The first silicon oxide film 12 is formed in a thickness of about 10 nm by heating in an atmosphere. Next, a polycrystalline silicon film 13 having a thickness of about 60 nm, a silicon nitride film 14 having a thickness of about 100 nm, and a silicon oxide film 15 having a thickness of about 150 nm are deposited by, for example, low pressure CVD. Next, a desired pattern is formed by using a photoresist by a normal photo-etching method, and the silicon oxide film 15 and the silicon nitride film 14 are processed by a RIE method using the photoresist as a mask. Then O ₂ The silicon substrate is exposed to plasma, the photoresist is removed, and the polycrystalline silicon film 13 is processed using the silicon oxide film 15 as a mask.
[0053]
Next, in FIGS. 5B and 6B, the silicon oxide film 12 and the silicon substrate 11 are processed using the silicon oxide film 15 as a mask to form a groove 17A in the silicon substrate 11. Next, O at about 1000 ° C. ₂ By heating in an atmosphere, a silicon oxide film 16 of about 6 nm is formed on the outer wall of the groove 17A. Next, a silicon oxide film 17 of about 600 nm as an STI filling material is deposited by HDP (high density plasma).
[0054]
Next, in FIG. 5C and FIG. 6C, the silicon oxide film 17 is flattened by a CMP (chemical mechanical polishing) method, and is heated in a nitrogen atmosphere at about 900 ° C. Further, the silicon nitride film 14 is immersed in a buffered (Buffered) HF solution for about 10 seconds and treated with phosphoric acid at about 150 ° C. to remove the silicon nitride film 14. Next, the silicon oxide film 17 is etched by about 20 nm with a Dilute HF solution.
[0055]
Further, phosphorus is added by a low pressure CVD method to deposit a polycrystalline silicon film 18 serving as a floating electrode. Further, the polycrystalline silicon film 18 is processed by a RIE method using a photoresist mask at a substantially central portion on the upper surface of the silicon oxide film 17 to form a slit 18A.
[0056]
5D and 6D, the ONO insulating films 19-1 and 19-2 (a silicon oxide film of about 5 nm, a silicon nitride film of about 5 nm, and a silicon oxide film of about 5 nm are formed by a low pressure CVD method. A polycrystalline silicon film 20 of about 100 nm to which phosphorus is added as a control electrode, a WSi film 21 of about 100 nm, and a silicon oxide film 22 of about 200 nm are deposited. Next, the photoresist is patterned into a desired shape by the photolithography method, and the silicon oxide film 22 is processed by, for example, the RIE method using the photoresist as a mask.
[0057]
Next, in FIG. 6E, using the silicon oxide film 22 as a mask, the WSi film 21, the polycrystalline silicon film 20, the ONO insulating films 19-1, 19-2, the polycrystalline silicon film 18, the polycrystalline silicon film 13, Are sequentially processed by, for example, the RIE method. Further, using the processed control electrode and the pattern of the silicon oxide film 17 serving as the STI filling material as a mask, the impurity diffusion layers 24-1 and 24-2 serving as source / drain regions in a self-aligned manner by, for example, ion implantation. , 24-3. Furthermore, O at about 1000 ° C. ₂ By heating in an atmosphere, a silicon oxide film 23 is formed on the side wall of each nonvolatile memory element MC.
[0058]
Through the above manufacturing steps, the nonvolatile memory elements MC <00> to MC <11> are formed.
[0059]
As shown in FIG. 5D, the inside of the slit 18A <1> between the floating electrodes is filled with the ONO insulating film 19-2 <1>. Therefore, the structure is such that the polycrystalline silicon film 20 and the WSi film 21 constituting the control electrode CG <1> cannot enter the slit 18A <1>. Therefore, electric field concentration does not occur at the floating electrode corner 25, and the charge retention characteristics are improved.
[0060]
Further, the manufacturing method according to the present embodiment includes an ONO insulating film 19-1, which is an inter-electrode insulating film of the control electrodes CG <0>, CG <1> and the floating electrodes FG <00> to FG <11>, and a slit. The ONO insulating film 19-2, which is a slit insulating film embedded in the slit 18A <0> and the slit 18A <1>, is simultaneously deposited using the same insulating film. At this time, the relational expression shown in this embodiment,
Slit width d _F / Thickness d _ONO <1.6
So that the slit width d _F , Membrane pressure d _ONO Is formed.
[0061]
Therefore, the insides of the slits 18A <0> and 18A <1> can be completely filled with the insulating film 19-2, so that no electric field concentration occurs at the floating electrode corner 25 with respect to the control electrode. Therefore, the charge retention characteristics are improved, and the charge retention failure rate can be reduced to almost 0%.
[0062]
In addition, since the same insulating film can be used to fill the gap between the electrodes and the slit at the same time, the manufacturing cost can be reduced and the manufacturing speed can be improved.
[0063]
As described above, the inter-electrode insulating film and the slit insulating film embedded in the slit are simultaneously manufactured using the same insulating film. However, only for the purpose of filling the slits 18A <0> and 18A <1>, an insulating film such as an oxide film or a silicon nitride film is first deposited, and the entire surface is etched by RIE, or the floating An insulating film other than the insulating film is removed, and thereafter, the inter-electrode insulating films of the control electrodes CG <0>, CG <1> and the floating electrodes FG <00> to FG <11> are formed using different insulating films. It is also possible to deposit.
[0064]
As described above, when the inter-electrode insulating film and the slit insulating film are deposited in different steps, the slit width d shown in the above-described embodiment is used. _F And the film thickness d between the electrodes _ONO Even if the slit has a large width that does not satisfy the relational expression, the charge retention rate is not reduced. In such a separate deposition process, the inside of the slits 18A <0> and 18A <1> can be completely filled with the insulating film regardless of the width of the slits. Therefore, no electric field concentration occurs at the floating electrode corner 25 facing the control electrode. Therefore, charge retention characteristics can be improved.
[0065]
[Second embodiment]
A second embodiment according to the present invention will be described with reference to FIGS. In the following description of the embodiment, the description of the same parts as in the first embodiment will be omitted.
[0066]
FIG. 7 is a cross-sectional view of a plurality of nonvolatile memory elements MC formed along the wiring longitudinal direction of control electrodes CG (polycrystalline silicon film 20 and WSi film 21) corresponding to FIG. FIG. 8 is a cross-sectional view for explaining an example of a method for manufacturing the nonvolatile memory element MC shown in FIG.
[0067]
As shown in FIG. 7, for example, a slit width d is formed at a substantially central portion of the upper surface of the silicon oxide film 17 as the STI filling material. _F Is formed about 80 nm. Inside the slit 18A, a silicon oxide film 31 having a low dielectric constant is formed.
[0068]
Between the polycrystalline silicon film 18 and the polycrystalline silicon film 20 along the longitudinal direction of the control electrode CG, alumina (Al ₂ O ₃ ) A film 32 is formed. The alumina film 32 is an insulating material having a higher dielectric constant than at least the silicon oxide film 31 having a low dielectric constant.
[0069]
As described above, in this embodiment, the insulating film formed inside the slit 18A and the insulating film formed between the floating electrode FG and the control electrode CG are formed of different materials, and the dielectric constant of each insulating film is It is formed differently.
[0070]
First, since the insulating film formed inside the slit 18A and the insulating film formed between the floating electrode FG and the control electrode CG are formed separately, the inside of the slit 18A is completely insulated even if the slit width is wide. Can be embedded with a film. Therefore, the control electrode CG does not enter the inside of the slit 18A. As a result, similarly to the first embodiment, concentration of the electric field on the floating electrode corner 25 can be avoided, and the charge retention characteristics can be improved.
[0071]
Further, the insulating films are formed so that the dielectric constants thereof are different. That is, the inside of the slit 18A is formed so as to be filled with the silicon oxide film 32 which is an insulating material having a low dielectric constant. Therefore, the data interference effect due to the capacitive coupling between the floating electrodes FG adjacent along the control electrode CG can be minimized. Here, the data interference effect due to the capacitive coupling between the floating electrodes FG refers to an effect in which the threshold voltage of the adjacent floating electrode FG is affected by the electrical state of the floating electrode FG. For example, it means that a threshold voltage of an adjacent floating electrode FG is influenced by whether or not electrons are injected into the floating electrode FG. Therefore, if this effect is large, the controllability of the threshold voltage of each nonvolatile memory element MC is reduced. However, a silicon oxide film 32, which is an insulating material having a low dielectric constant, is formed inside the slit 18A. Therefore, the electric action between the adjacent floating electrodes FG can be minimized. As a result, the data interference effect can be minimized, and the reliability of each nonvolatile memory element MC can be improved.
[0072]
Further, an insulating film formed between the polycrystalline silicon layer 18 and the polycrystalline silicon layer 20 is formed of an alumina film 32 which is an insulating material having a high dielectric constant. Therefore, the capacitive coupling between the floating electrode FG and the control electrode CG increases. As a result, the control voltage applied to the control electrode CG at the time of writing and reading can be reduced.
[0073]
The slit insulating film formed inside the slit 18A is preferably made of an insulating material having a low dielectric constant as much as possible. Therefore, it is preferable that the silicon oxide film is formed by, for example, a silicon oxide film deposited by a coating method, rather than a silicon oxide film formed by normal thermal oxidation. However, the material is not limited to the silicon insulating film 31 as long as the material has a low dielectric constant, and can be applied to other insulating materials.
[0074]
Further, the insulating material formed between the polycrystalline silicon film 20 and the polycrystalline silicon film 18 is Al ₂ O ₃ In addition to the (alumina) film 32, for example, Ta ₂ O ₅ (Tantalum oxide) film or the like can be used. Considering that it is required that the floating electrode FG has a sufficient insulating property so as not to leak to the control electrode CG, the current technology requires Al. ₂ O ₃ The (alumina) film 32 is more preferable. Further, considering that it is sufficient that the leakage current is not more than a certain value in a high dielectric constant film, for example, a silicon nitride film or the like can be applied. In this case, for example, a silicon nitride film using a deposition method with a small leak current using a JVD (Jet Vapor Deposition) method is applied. Further, as compared with the case where a single-layer film having a high dielectric constant is used, the capacitive coupling between the floating electrode FG and the control electrode CG is small, It is also possible to use a layered film.
[0075]
Hereinafter, an example of a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 7 will be described with reference to FIGS. 8A to 8C.
[0076]
First, in FIG. 8A, a silicon oxide film 12, a polycrystalline silicon film 13, a silicon nitride film 14, and a silicon oxide film 15 are formed on a main surface of a silicon substrate 11 in the same manner as in the first embodiment. , A silicon oxide film 16 and a silicon oxide film 17 serving as an STI filling material are formed.
[0077]
Next, in FIG. 8B, a polycrystalline silicon film 18 serving as a floating electrode is formed by adding phosphorus by a low pressure CVD method. Further, the polycrystalline silicon film 18 is processed by RIE using a photoresist mask, and a slit 18A is formed substantially at the center of the upper surface of the silicon oxide film 17. At this time, the slit width of the slit 18A is, for example, about 80 nm. Further, a silicon oxide film 31 having a low dielectric constant and a low dielectric constant is formed inside the slit 18A by using, for example, a coating method.
[0078]
Next, in FIG. 8C, an alumina film 32 is formed by, for example, a CVD method. Hereinafter, the nonvolatile semiconductor memory device shown in FIG. 7 can be formed by the same manufacturing steps as in the first embodiment.
[0079]
[Third Embodiment]
A third embodiment according to the present invention will be described with reference to FIGS.
[0080]
FIG. 9 is a cross-sectional view of a plurality of nonvolatile memory elements MC formed along the wiring longitudinal direction of the control electrode CG. FIG. 10 is a cross-sectional view for explaining an example of a method for manufacturing the nonvolatile memory element MC shown in FIG.
[0081]
As shown in FIG. 9, a slit width d is formed substantially at the center of the upper surface of the silicon oxide film 17 as the STI filling material. _F For example, a slit 18A of about 10 nm is formed. A silicon oxide film 33 having a low dielectric constant is formed inside the slit 18A, and the same silicon oxide film 33 is formed between the polycrystalline silicon film 20 and the polycrystalline silicon film 18 with a small thickness. Are integrally formed. Here, the thickness of the silicon oxide film 33 formed between the polycrystalline silicon film 20 and the polycrystalline silicon film 18 is, for example, about 5 to 6 nm.
[0082]
An alumina film 34 is formed on the upper surface of the silicon oxide film 33. As described above, the alumina film 34 is an insulating material having a high dielectric constant.
[0083]
A thin silicon oxide film 33 is formed inside the slit 18A and between the polycrystalline silicon film 20 and the polycrystalline silicon film 18, and both are formed integrally. Thus, the inside of the slit 18A is filled with the silicon oxide film 20 which is an insulating material having a low dielectric constant. As a result, the charge retention characteristics can be improved, and the data interference effect between the floating electrodes FG can be minimized.
[0084]
A low dielectric constant silicon oxide film 33 is also formed between the polycrystalline silicon film 20 and the polycrystalline silicon film 18 with a small thickness. As a result, electric field concentration at the floating electrode corner 25 can be avoided, and the charge retention characteristics can be further improved.
[0085]
An alumina film 34 having a high dielectric constant is formed on the upper surface of the thin silicon oxide film 33. As a result, the operating voltage applied to the control electrode CG at the time of writing and reading can be reduced by increasing the capacitive coupling between the floating electrode FG and the control electrode CG.
[0086]
Further, the thickness of the silicon oxide film 33 formed between the polycrystalline silicon 20 and the polycrystalline silicon 18 is smaller than the thickness of the alumina film 34. As a result, both the effect of reducing the operating voltage and the effect of improving the charge retention characteristics can be achieved.
[0087]
Further, the thickness of the silicon oxide film 33 formed between the polycrystalline silicon film 20 and the polycrystalline silicon film 18 is, for example, about 5 to 6 nm. Therefore, the width d of the slit 18A _F Can be embedded in the slit 18A even if the size is extremely small, for example, about 10 nm. As a result, the nonvolatile memory elements can be arranged at a high density, the charge retention characteristics are improved, and the data interference effect between adjacent floating electrodes FG can be minimized. Thus, the structure is effective even in extremely small dimensions.
[0088]
Note that, similarly to the above, the silicon oxide film 33 is desirably an insulating material having a low dielectric constant as much as possible. For example, a silicon oxide film deposited and formed by a coating method can be applied. Other insulating materials can also be used as long as they have a lower dielectric constant.
[0089]
Similarly, the alumina film 34 formed on the upper surface of the thinly formed silicon oxide film 33 is made of, for example, Ta. ₂ O ₅ (Tantalum oxide) film, silicon nitride film, ONO insulating film and the like can be used.
[0090]
Hereinafter, an example of a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 9 will be described with reference to FIGS. 10A to 10C.
[0091]
First, in FIG. 10A, a trench 17A serving as an element isolation region is formed on the main surface of a silicon substrate 11 by the same method as in the first embodiment, and then a silicon oxide film 12, a polycrystalline silicon film is formed. 13, a silicon nitride film 14, a silicon oxide film 15, a silicon oxide film 16, and a silicon oxide film 17 serving as an STI filling material are sequentially formed.
[0092]
Next, in FIG. 10B, the silicon oxide film 17 is flattened by the CMP method, and heated in a nitrogen atmosphere at about 900 ° C. Further, the silicon nitride film 14 is immersed in a buffered HF solution for about 10 seconds and treated with phosphoric acid at about 150 ° C. to remove the silicon nitride film 14. Next, the silicon oxide film 17 is etched by about 20 nm with a dilute HF solution. Further, phosphorus is added by a low pressure CVD method to deposit a polycrystalline silicon film 18 serving as a floating electrode. Further, the polycrystalline silicon film 18 is processed by RIE using a photoresist mask, and a slit 18A is formed substantially at the center of the upper surface of the silicon oxide film 17. At this time, the slit width of the slit 18A is, for example, about 10 nm. Further, a silicon oxide film 33 having a low dielectric constant and a low dielectric constant is simultaneously formed on the inside of the slit 18A and on the upper surface of the polycrystalline silicon film 18 by using, for example, a CVD method without a step of embedding the inside of the slit 18A.
[0093]
Next, in FIG. 10C, an alumina film 34 is formed by, for example, a CVD method. Hereinafter, the nonvolatile semiconductor memory device shown in FIG. 9 can be formed by the same manufacturing process as in the first embodiment.
[0094]
In the manufacturing method according to the embodiment, the inside of the slit 18A is buried in the inside of the slit 18A and the upper surface of the polycrystalline silicon film 18 by using, for example, a CVD method, and at the same time, a silicon oxide film having a low dielectric constant and a low dielectric constant is used. 33 are formed. Therefore, the step of separately embedding the inside of the slit 18A can be omitted.
[0095]
In the first to third embodiments, the floating electrode FG is formed by the polycrystalline silicon film 13 and the polycrystalline silicon film 18 formed on the upper surface thereof and having both ends projecting up to the slit 18A on the silicon oxide film 16. Is done. Since the polycrystalline silicon film 18 extends to the slit 18A, the area facing the control electrode CG can be increased. As a result, the capacitance coupling ratio can be increased.
[0096]
[Fourth embodiment]
A fourth embodiment according to the present invention will be described with reference to FIGS.
[0097]
FIG. 11 is a cross-sectional view of a plurality of nonvolatile memory elements formed along the wiring longitudinal direction of the control electrode CG. FIG. 12 is a cross-sectional view for explaining an example of a method for manufacturing the nonvolatile memory element MC shown in FIG.
[0098]
As shown in FIG. 11, a polycrystalline silicon film 13 serving as a floating electrode FG is formed on a silicon oxide film 12 in the element region. The floating electrode FG is formed only of the polycrystalline silicon film 13. Further, a silicon oxide film 35 having a low dielectric constant, which is an STI filling material, is formed inside the trench 17A serving as an element isolation region. The width of the groove 17A serving as the element isolation region is, for example, about 60 nm. Further, an alumina film 36 is formed on the upper surfaces of the polycrystalline silicon film 13 and the silicon oxide film 35 along the control electrode CG. As described above, the alumina film 36 is an insulating material having a high dielectric constant.
[0099]
As shown in FIG. 11, floating electrode FG is formed only by polycrystalline silicon film 13. On the other hand, the floating electrode FG according to the first to third embodiments is composed of the polycrystalline silicon 13 and the polycrystalline silicon 18 formed on the upper surface thereof and having both ends projecting up to the slit 18A of the silicon oxide film 16. It is formed. However, if the distance between the adjacent nonvolatile memory elements CM along the control electrode CG is reduced due to miniaturization, it may be difficult to adopt the above configuration. This is because if the distance is small, sufficient insulation between the nonvolatile memory elements adjacent to the control electrode CG may not be ensured.
[0100]
However, in the present embodiment, the polycrystalline silicon film 13 is separated by the low-dielectric-constant silicon oxide film 35 serving as an element region, and does not overhang the upper surface of the silicon oxide film 35. Therefore, even when the distance between the adjacent nonvolatile memory elements MC is reduced due to miniaturization, sufficient insulation between the adjacent nonvolatile memory elements can be ensured.
[0101]
A low-dielectric-constant silicon oxide film 35 as an STI filling material is formed inside the trench 17A serving as an element isolation region. Therefore, not only between adjacent floating electrodes, but also between the floating electrode and a source / drain region (not shown) serving as an active region, and a coupling capacitance between a source region and a drain region (not shown) can be reduced. . As a result, the above-described interference effect between adjacent nonvolatile memory elements can be reduced.
[0102]
Similarly to the above, the silicon oxide film 35 having a low dielectric constant is desirably an insulating material having a dielectric constant as low as possible. For example, a silicon oxide film deposited and formed by a coating method can be used. Other insulating materials can also be used as long as they have a lower dielectric constant.
[0103]
Similarly, the alumina film 36 formed on the upper surface of the silicon oxide film 35 is also desirably an insulating material having a high dielectric constant. Thus, for example, Ta ₂ O ₅ (Tantalum oxide) film, silicon nitride film, ONO insulating film and the like can be used.
[0104]
Hereinafter, an example of a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 11 will be described with reference to FIGS. 12A to 12C.
[0105]
First, in FIG. 12A, a trench 17A serving as an element isolation region is formed on the main surface of a silicon substrate 11 by the same method as in the first embodiment, and then a silicon oxide film 12, a polycrystalline silicon film is formed. 13, a silicon nitride film 14, a silicon oxide film 15, and a silicon oxide film 16 are sequentially formed. Thereafter, a low dielectric constant silicon oxide film 35 serving as an STI filling material is formed by, for example, a coating method (or a CVD method).
[0106]
Next, in FIG. 12B, the silicon oxide film 35 having a low dielectric constant is flattened to the surface of the silicon nitride film 14 by, for example, a CMP method, and then heated in a nitrogen atmosphere at about 900 ° C. Further, the silicon nitride film 14 is immersed in a buffered (Buffered) HF solution and treated with phosphoric acid at about 150 ° C. to remove the silicon nitride film 14. Next, the silicon oxide film 35 having a low dielectric constant is receded with a dilute HF solution.
[0107]
Next, in FIG. 12C, an alumina film 36 is formed on the upper surface of the polycrystalline silicon 13 and the silicon oxide film 35 having a low dielectric constant by, for example, a CVD method. Hereinafter, the nonvolatile semiconductor memory device shown in FIG. 11 can be formed by the same manufacturing process as in the first embodiment.
[0108]
In the manufacturing method according to this embodiment, the insulating film for separating the STI filling material and the adjacent floating electrode FG is simultaneously formed of the silicon oxide film 35 having a low dielectric constant. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced.
[0109]
Floating electrode FG is formed only of polycrystalline silicon 13. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced.
[0110]
[Fifth Embodiment]
A fifth embodiment according to the present invention will be described with reference to FIGS.
[0111]
FIG. 13 is a cross-sectional view of a plurality of nonvolatile memory elements formed along the wiring longitudinal direction of the control electrode CG. FIG. 14 is a cross-sectional view for explaining an example of a method for manufacturing the nonvolatile memory element shown in FIG.
[0112]
As shown in FIG. 13, a silicon oxide film 35 having a low dielectric constant is formed inside a trench 17A serving as an element region isolation region. As described above, the silicon oxide film 35 is an insulating material having a low dielectric constant. On the surface of the polycrystalline silicon film 13, a polycrystalline silicon film 37 having both ends projecting along the direction of the control electrode CG is formed inside the silicon oxide film 3. A floating electrode is formed by the two layers of the polycrystalline silicon film 37 and the polycrystalline silicon film 13. Further, an alumina film 36 is formed on the surfaces of the low dielectric constant silicon oxide film 35 and the polycrystalline silicon film 37 along the direction of the control electrode CG. As described above, the alumina film 36 is an insulating material having a high dielectric constant.
[0113]
The polycrystalline silicon film 37 is formed on the surface of the polycrystalline silicon film 13 such that both end portions protrude inside the silicon oxide film 3 along the direction of the control electrode CG. Therefore, the area facing the control electrode CG can be increased. As a result, the threshold voltage applied to the control electrode CG can be reduced by increasing the capacitance coupling ratio.
[0114]
A silicon oxide film 35 having a low dielectric constant is formed inside trench 17A serving as an element region isolation region. Therefore, the coupling capacitance of the adjacent floating electrode FG can be reduced.
[0115]
An alumina film 36 having a high dielectric constant is formed on the surfaces of the silicon oxide film 35 and the polycrystalline silicon film 37 along the direction of the control electrode CG. As a result, the coupling capacitance between the control electrode CG and the floating electrode FG increases, so that the threshold voltage applied to the control electrode CG can be reduced.
[0116]
Note that, similarly to the above, the low dielectric constant silicon oxide film 35 is desirably an insulating material having a low dielectric constant. For example, a silicon oxide film deposited and formed by a coating method can be used. Other insulating materials can also be used as long as they have a lower dielectric constant.
[0117]
Similarly, the alumina film 36 formed on the upper surface of the silicon oxide film 35 is also desirably an insulating material having a high dielectric constant. Thus, for example, Ta ₂ O ₅ (Tantalum oxide) film, silicon nitride film, ONO insulating film and the like can be used.
[0118]
Hereinafter, an example of a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 13 will be described with reference to FIGS.
[0119]
First, in FIG. 14A, a groove 17A serving as an element isolation region is formed on the main surface of a silicon substrate 11 by the same method as in the first embodiment, and then the silicon oxide film 12, polycrystalline silicon A film 13, a silicon nitride film 14, a silicon oxide film 15, and a silicon oxide film 16 are sequentially formed. Thereafter, a low dielectric constant silicon oxide film 35 serving as an STI filling material is formed by, for example, a coating method.
[0120]
Next, in FIG. 14B, using the silicon nitride film 14 as a stopper, for example, by CMP, the low-dielectric-constant silicon oxide film 35 is planarized, and the surface of the silicon nitride film 14 is planarized. It is heated in a nitrogen atmosphere. Further, the silicon nitride film 14 is immersed in a buffered (Buffered) HF solution and treated with phosphoric acid at about 150 ° C. to remove the silicon nitride film 14.
[0121]
Next, in FIG. 14 (c), the silicon oxide film 35 having a low dielectric constant is isotropically recessed with a dilute HF solution.
[0122]
Further, a polycrystalline silicon film 37 is deposited and formed on the entire surface by, for example, a CVD method. Further, the silicon oxide film 35 and the polycrystalline silicon film 37 are flattened by, for example, a CMP method.
[0123]
Next, in FIG. 14D, an alumina film 36 is formed on the upper surface of the polycrystalline silicon and the low dielectric constant silicon oxide film 35 by, for example, a CVD method. Hereinafter, the nonvolatile semiconductor memory device shown in FIG. 13 can be formed by the same manufacturing steps as in the first embodiment.
[0124]
In the manufacturing method according to this embodiment, both end portions of the silicon oxide film 35 are removed so that the central portion of the silicon oxide film 35 remains. Further, a polycrystalline silicon film 37 is deposited and formed on the entire surface by, for example, a CVD method. Further, the silicon oxide film 35 and the polycrystalline silicon film 37 are flattened by, for example, a CMP method. In this way, a structure in which both ends of the polycrystalline silicon 37 project can be formed in a self-aligned manner. As a result, even when the width of the groove 17A separating the floating electrode FG is narrow, a structure in which the polycrystalline silicon 37 extends can be formed. With the structure in which the polycrystalline silicon 37 extends as described above, the capacitive coupling between the floating electrode FG and the control electrode CG can be increased.
[0125]
[Sixth Embodiment]
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIGS.
[0126]
FIG. 15 is a cross-sectional view of a plurality of nonvolatile memory elements formed along the wiring longitudinal direction of the control electrode CG. FIG. 16 is a cross-sectional view for explaining an example of a method for manufacturing the nonvolatile memory element shown in FIG.
[0127]
As shown in FIG. 15, the upper surface of the low-dielectric-constant silicon oxide film 38 is formed inside the trench 17A serving as the element region isolation region so as to be higher than the upper surface of the adjacent polycrystalline silicon film 18. The silicon oxide film 38 is an insulating material having a low dielectric constant. An alumina film 39 is formed on the surfaces of silicon oxide film 38 and polycrystalline silicon film 18 along the direction of control electrode CG. The alumina film 39 is an insulating material having a high dielectric constant.
[0128]
The upper surface of the low-dielectric-constant silicon oxide film 38 is formed inside the trench 17A serving as the element region isolation region so as to be higher than the upper surface of the adjacent polycrystalline silicon film 18. Therefore, the control electrode CG does not enter the inside of the groove 17A. As a result, concentration of the electric field at the corner of the floating electrode can be avoided. Further, the silicon oxide film 37 is formed of an insulating material having a low dielectric constant. Therefore, the coupling capacitance between the adjacent floating electrodes FG can be reduced. With the structure of the silicon oxide film 38 as described above, the reliability of the nonvolatile memory element can be further improved. Therefore, the present invention can be applied even when the width of the groove 17A is, for example, about 100 nm or less.
[0129]
Further, an alumina film 36 having a high dielectric constant is formed on the surfaces of the silicon oxide film 38 and the polycrystalline silicon film 18 along the direction of the control electrode CG. As a result, the voltage applied to the control electrode CG can be reduced by increasing the coupling capacitance between the control electrode CG and the floating electrode FG.
[0130]
Note that, similarly to the above, the low dielectric constant silicon oxide film 35 is desirably an insulating material having a low dielectric constant. For example, a silicon oxide film deposited and formed by a coating method can be used. Other insulating materials can also be used as long as they have a lower dielectric constant.
[0131]
Similarly, the alumina film 36 formed on the upper surface of the silicon oxide film 35 is also desirably an insulating material having a high dielectric constant. Thus, for example, Ta ₂ O ₅ (Tantalum oxide) film, silicon nitride film, ONO insulating film and the like can be used.
[0132]
Hereinafter, an example of a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 15 will be described with reference to FIGS. 16A to 16C.
[0133]
First, in FIG. 16A, a trench 17A serving as an element isolation region is formed on the main surface of a silicon substrate 11 by the same method as that of the first embodiment, and then the silicon oxide film 12, polycrystalline silicon A film 13, a silicon nitride film 14, a silicon oxide film 15, and a silicon oxide film 16 are sequentially formed. Then, a low dielectric constant silicon oxide film 38 serving as an STI filling material is formed by, for example, a coating method.
[0134]
Next, in FIG. 16B, the silicon oxide film 35 having a low dielectric constant is flattened by, for example, the CMP method using the silicon nitride film 14 as a stopper, and the surface of the silicon nitride film 14 is flattened. It is heated in a nitrogen atmosphere. Further, the silicon nitride film 14 is immersed in a buffered (Buffered) HF solution and treated with phosphoric acid at about 150 ° C. to remove the silicon nitride film 14.
[0135]
Next, in FIG. 16C, a polycrystalline silicon film 18 is deposited and formed on the entire surface by, for example, a CVD method. Further, the silicon oxide film 38 and the polycrystalline silicon film 18 are flattened by, for example, a CMP method using the silicon oxide film 38 as a stopper. For example, a part of the upper portion of the polycrystalline silicon film 18 is removed and dropped by the entire surface RIE method. Thus, a structure in which the upper surface of silicon oxide film 38 is higher than the upper surface of polycrystalline silicon film 18 is formed.
[0136]
Next, in FIG. 16D, an alumina film 36 is formed on the polycrystalline silicon film 18 and the silicon oxide film 38 having a low dielectric constant by, for example, a CVD method. Hereinafter, the nonvolatile semiconductor memory device shown in FIG. 15 can be formed by the same manufacturing process as in the first embodiment.
[0137]
As described above, the present invention has been described using the first to sixth embodiments. However, the present invention is not limited to each of the above-described embodiments. It is possible to transform to Also, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. For example, even if some components are deleted from all the components shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. In a case where at least one of the effects described above is obtained, a configuration in which this component is deleted can be extracted as an invention.
[0138]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a nonvolatile semiconductor memory device having a floating electrode with good charge retention and a method of manufacturing the same.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a cross-sectional structure of a nonvolatile semiconductor memory device having a floating electrode according to a first embodiment of the present invention, taken along line II of FIG.
FIG. 2 is a sectional view of the nonvolatile semiconductor memory device having a floating electrode according to the first embodiment of the present invention, taken along line II-II in FIG.
FIG. 3 is a plan view schematically showing a layout of a nonvolatile semiconductor memory device having a floating electrode according to the first embodiment of the present invention.
FIG. 4 is a graph showing the dependency of the charge retention characteristic failure rate on the slit width / film thickness according to the first embodiment of the present invention.
FIG. 5 is a process chart for explaining an example of a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention with reference to the cross-sectional structure shown in FIG.
FIG. 6 is a process chart for explaining an example of a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention with reference to the cross-sectional structure shown in FIG. 2;
FIG. 7 is a cross-sectional view of a nonvolatile semiconductor memory device having a floating electrode according to a second embodiment of the present invention.
FIG. 8 is a process chart for explaining an example of a method for manufacturing a nonvolatile semiconductor memory device according to the second embodiment of the present invention with reference to the cross-sectional structure of FIG. 7;
FIG. 9 is a sectional view of a nonvolatile semiconductor memory device having a floating electrode according to a third embodiment of the present invention.
FIG. 10 is a process chart for describing an example of a method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention with reference to the cross-sectional structure of FIG. 9;
FIG. 11 is a sectional view of a nonvolatile semiconductor memory device having a floating electrode according to a fourth embodiment of the present invention.
FIG. 12 is a process chart for explaining an example of a method for manufacturing a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention with reference to the cross-sectional structure of FIG. 11;
FIG. 13 is a sectional view of a nonvolatile semiconductor memory device having a floating electrode according to a fifth embodiment of the present invention.
FIG. 14 is a process chart for explaining an example of a method for manufacturing a nonvolatile semiconductor memory device according to the fifth embodiment of the present invention with reference to the cross-sectional structure of FIG. 14;
FIG. 15 is a sectional view of a nonvolatile semiconductor memory device having a floating electrode according to a sixth embodiment of the present invention.
FIG. 16 is a process chart for explaining an example of a method for manufacturing a nonvolatile semiconductor memory device according to the sixth embodiment of the present invention with reference to the cross-sectional structure of FIG. 15;
FIG. 17 is a cross-sectional view of a conventional nonvolatile semiconductor memory device having a floating electrode.
[Explanation of symbols]
11 silicon substrate, 12 silicon oxide film, 13 polycrystalline silicon film, 16 silicon oxide film, 17 silicon oxide film, 17A groove serving as element isolation region, 18 polycrystalline silicon film, 18A slit 19-1, 19-2: ONO insulating film, 20: polycrystalline silicon film, 21: WSi film, 22: silicon oxide film.

Claims (22)

A plurality of non-volatile memory elements formed on element regions each separated by an element isolation region on a main surface of a semiconductor substrate of the first conductivity type;
Each of the non-volatile storage elements,
A gate insulating film formed on a main surface of the semiconductor substrate,
A plurality of floating electrodes formed on the gate insulating film along a first direction;
A second conductivity type impurity diffusion region formed along the second direction so as to sandwich the floating electrode;
And a control electrode formed on the plurality of floating electrodes via an inter-electrode insulating film,
A plurality of slits are formed between a plurality of floating electrodes adjacent along the first direction, a slit insulating layer is embedded in each of the plurality of slits, and the inter-electrode insulating film and the control electrode are A nonvolatile semiconductor memory device formed along the first direction over a floating electrode of a plurality of nonvolatile memory elements adjacent to each other with a slit insulating layer interposed therebetween. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the slit insulating layer embedded in the slit is formed of the same insulating material as the inter-electrode insulating film. 2. The non-volatile semiconductor memory device according to claim 1, wherein the slit insulating layer embedded in the slit is formed of an insulating material different from the inter-electrode insulating film. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a width of the slit is 1.6 times or less a thickness of the inter-electrode insulating film. 5. 5. The method according to claim 1, wherein the inter-electrode insulating film or the slit insulating film includes at least one of an ONO insulating film, a silicon oxide film, and a silicon nitride film. The nonvolatile semiconductor memory device according to claim 1. 2. The slit insulating film is formed from a first insulating film having a low dielectric constant, and the inter-electrode insulating film is formed from a second insulating film having a high dielectric constant. The nonvolatile semiconductor memory device according to claim 3 or 4. The first insulating film, the nonvolatile semiconductor memory device according to claim 6, characterized in that it is formed to include at least one of SiO ₂ SiO ₂ or a low dielectric constant. The second insulating _{film, Al 2 O 3, Ta 2} O 5, or ONO insulating film nonvolatile semiconductor memory device according to claim 6, characterized in that it is formed to include at least one of . The slit insulating film and the inter-electrode insulating film are formed from the first insulating film, and the second insulating film is formed on the first insulating film along the first direction. The nonvolatile semiconductor memory device according to claim 6, wherein: The element isolation film is formed by the first insulating film, has a plurality of floating electrodes separated by the first insulating film, and the second insulating film is formed by the first insulating film and the plurality of floating electrodes. 9. The nonvolatile semiconductor memory device according to claim 6, wherein the nonvolatile semiconductor memory device is formed on an upper surface of the floating electrode. Further, the plurality of floating electrodes have a two-layer structure formed by a first floating electrode layer formed on the gate insulating film and a second floating electrode layer formed on the first floating electrode. The nonvolatile semiconductor memory device according to claim 1, wherein: 12. The nonvolatile semiconductor memory device according to claim 11, wherein both ends of said second floating electrode layer are formed so as to protrude inside said element isolation film along said first direction. 12. The nonvolatile semiconductor memory device according to claim 11, wherein an upper surface of said first insulating film is formed above an upper surface of said second floating electrode layer. Forming first and second element formation regions separated by an element isolation region on a main surface of a semiconductor substrate of a first conductivity type;
Forming first and second gate insulating films in the first and second element formation regions, respectively;
Forming first and second floating electrodes on the first and second gate insulating films in a state where the first and second gate insulating films are separated from each other by the slit on the element isolation region;
Forming a slit insulating layer having substantially the same thickness as the first and second floating electrodes in the slit,
Forming an inter-electrode insulating film on the slit insulating film and on the first and second floating electrodes;
A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a common control electrode on the inter-electrode insulating film over the first and second floating electrodes. Depositing a gate insulating film material on the main surface of the semiconductor substrate,
Depositing a first floating electrode material on the gate insulating film material;
Patterning the first floating electrode material and the gate insulating film material to form a gate insulating film and a first floating electrode, and forming an element isolation groove in the semiconductor substrate;
An element isolation insulating film is buried in the element isolation trench to form an element isolation region,
Forming a second floating electrode material on the first floating electrode and on the element isolation insulating film;
Patterning the second floating electrode material, forming two second floating electrodes insulated from each other via an insulating slit on the element isolation insulating film on the first floating electrode;
Forming a slit insulating film to fill the insulating slit,
An inter-electrode insulating film material and a control electrode material are sequentially deposited on the slit insulating film and the second floating electrode,
A method for manufacturing a nonvolatile semiconductor memory device, comprising: patterning the control electrode material to form a control electrode in common on the slit insulating film and the second floating electrode. 16. The non-volatile memory according to claim 15, wherein a gate sidewall insulating film is formed on a side surface of the control electrode, the inter-electrode insulating film, the second floating electrode, and the first floating electrode exposed by the patterning. Of manufacturing a nonvolatile semiconductor memory device. After patterning the second floating electrode material and forming two second floating electrodes insulated from each other via an insulating slit on the element isolation insulating film on the first floating electrode,
17. The method according to claim 15, wherein the slit insulating film and the inter-electrode insulating film are formed simultaneously so as to fill the insulating slit. After patterning the second floating electrode material and forming two second floating electrodes insulated from each other via an insulating slit on the element isolation insulating film on the first floating electrode,
Forming a first insulating film having a low dielectric constant so as to fill the insulating slit;
17. The method of manufacturing a nonvolatile semiconductor memory device according to claim 15, wherein a second insulating film having a high dielectric constant is formed on the first insulating film and the second floating electrode. . After patterning the second floating electrode material and forming two second floating electrodes insulated from each other via an insulating slit on the element isolation insulating film on the first floating electrode,
The slit insulating film and the inter-electrode insulating film are simultaneously formed by the first insulating film so that the insulating slit is filled,
17. The method according to claim 15, wherein the second insulating film is formed on the first insulating film. After forming an element isolation groove in the semiconductor substrate,
Burying the first insulating film in the element isolation groove to form an element isolation region;
17. The method according to claim 15, wherein the second insulating film is formed on the first floating electrode and the first insulating film. After burying the first insulating film in the element isolation groove and forming an element isolation region,
Removing both ends of the first insulating film,
A second floating electrode material is deposited on the first insulating film and the first floating electrode, and a second floating electrode formed so as to protrude inside the missing portion of the first insulating film is formed. Self-aligned,
17. The method according to claim 15, wherein the second insulating film is formed on the first insulating film and the second floating electrode. After burying the first insulating film in the element isolation groove and forming an element isolation region,
Forming a second floating electrode on the first floating electrode so as to sandwich the first insulating film;
Forming the second floating electrode so that an upper surface of the first insulating film is higher than an upper surface of the second floating electrode;
17. The method according to claim 15, wherein the second insulating film is formed on the first insulating film and the second floating electrode.

Images