JP2009059987A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily manufacture a semiconductor device in which a charge storage layer is separated under a gate electrode. <P>SOLUTION: In the semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate electrode 16 provided above a semiconductor substrate 10, a gate insulating film 12 provided at the center of the gate electrode 16 and on the semiconductor substrate 10, a first insulating film 14 which is provided from above of the gate insulating film 12 to both ends of the gate electrode 16 and is made of a different material from that of the gate insulating film 12, a tunnel insulating film 21 provided on both sides of the gate insulating film 12 and on the semiconductor substrate 10, and a charge storage layer 26 interposed between the tunnel insulating film 21 and the first insulating film 14. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a nonvolatile memory and a manufacturing method thereof.

  In recent years, nonvolatile memories, which are semiconductor devices that can retain data even when the power is turned off, have been widely used. In a flash memory which is a typical non-volatile memory, a transistor constituting a memory cell has a floating gate or an insulating film called a charge storage layer. Data is stored by accumulating charges in the charge accumulation layer. As a flash memory using an insulating film as a charge storage layer, there is a flash memory having a SONOS (Silicon Oxide Nitride Oxide silicon) type structure that stores charges in a trap layer in an ONO (oxide film / nitride film / oxide film) film. Patent Document 1 discloses a flash memory having virtual ground type memory cells that operate symmetrically by switching the source and drain as one of the SONOS type flash memories.

Patent Documents 2 and 3 disclose a technique in which a charge storage layer is formed in a part under a gate electrode.
US Pat. No. 6,011,725 JP 2000-004014 A JP 2004-343014 A

  According to the invention of Patent Document 1, two bits can be stored in one memory cell. As the memory cell becomes finer, interference between two bits occurs. In order to suppress this, the charge storage layers each storing 2 bits are separated. However, it is not easy to manufacture a semiconductor device in which the charge storage layer formed under the gate electrode is divided into two.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of easily manufacturing a semiconductor device in which a charge storage layer is separated under a gate electrode and a manufacturing method thereof.

  The present invention includes a gate electrode provided above a semiconductor substrate, a gate insulating film provided on the semiconductor substrate below the center of the gate electrode, and from above the gate insulating film to below both ends of the gate electrode. A first insulating film made of a material different from the gate insulating film, a tunnel insulating film provided on the semiconductor substrate on both sides of the gate insulating film, the tunnel insulating film, and the first insulating film; And a charge storage layer provided so as to be sandwiched between the semiconductor device and the semiconductor device. According to the present invention, a semiconductor device in which a charge storage layer is separated under a gate electrode can be easily manufactured. Furthermore, the film thicknesses of the first insulating film and the tunnel insulating film can be set independently.

  In the above structure, the first insulating film may be thicker than the tunnel insulating film. According to this configuration, the charge retention characteristics of the charge storage layer can be improved.

  In the above structure, a second insulating film provided below the first insulating film and on the charge storage layer may be provided.

  In the above configuration, the second insulating film and the tunnel insulating film may be made of the same material.

  In the above structure, the total thickness of the first insulating film and the second insulating film may be larger than the thickness of the tunnel insulating film. According to this configuration, the charge retention characteristics of the charge storage layer can be improved.

  In the above structure, the first insulating film may be directly provided on the charge storage layer.

  In the above structure, the gate insulating film can be made of a silicon oxide film, and the first insulating film can be made of an aluminum oxide film.

  In the above structure, the charge storage layer may be made of hafnium oxide, and the tunnel insulating film may be made of aluminum oxide.

  In the above structure, the first insulating film may be made of aluminum oxide, and the gate insulating film and the tunnel insulating film may be made of a silicon oxide film.

  In the above structure, the first insulating film may be made of aluminum oxide, and the gate oxide film, the second insulating film, and the tunnel insulating film may be made of a silicon oxide film.

  In the above structure, the charge storage layer may be formed of a silicon film.

  The present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a first insulating film on the gate insulating film, a step of forming a gate electrode on the first insulating film, and the gate A step of selectively removing the gate electrode, the first insulating film, and the gate insulating film stacked so that the electrode and the first insulating film are anisotropically etched and the gate insulating film is side-etched; And a step of forming a tunnel insulating film on a region of the semiconductor substrate on which the gate insulating film is side-etched, and a step of forming a charge storage layer on the tunnel insulating film. It is a manufacturing method of an apparatus. According to the present invention, a semiconductor device in which a charge storage layer is separated under a gate electrode can be easily manufactured. Furthermore, the film thicknesses of the first insulating film and the tunnel insulating film can be set independently.

  In the above configuration, the method includes forming a second insulating film in the side-etched region under the first insulating film, and forming the tunnel insulating film and forming the second insulating film It can be configured to be performed simultaneously.

  According to the present invention, a semiconductor device in which a charge storage layer is separated under a gate electrode can be easily manufactured. Furthermore, the film thicknesses of the first insulating film and the tunnel insulating film can be set independently.

  FIG. 1 is a plan view of a flash memory according to a comparative example, Examples 1 to 3. FIG. A bit line made of a diffusion region 30 extends in the silicon semiconductor substrate 10. A word line 34 extending so as to intersect the diffusion region 30 is provided on the semiconductor substrate 10. The semiconductor substrate 10 between the diffusion regions 30 is a channel region 44, and the charge storage layer 26 is provided on the channel region 44. In FIG. 1, the charge storage layer 26 is shown by hatching through the word line 34. On the channel region 44, charge storage layers 26 are formed on the ends E1 and E2 in the extending direction of the word line 34, respectively. Thus, since the charge storage layer 26 is separated, interference between two bits stored in one memory cell is suppressed. The charge storage layer 26 may be provided continuously in the extending direction of the diffusion region 30.

  Next, a method for manufacturing a semiconductor device according to a comparative example will be described. 2 (a) to 3 (c) are cross-sectional views corresponding to the AA cross section of FIG. Referring to FIG. 2A, the gate insulating film 12 is formed on the semiconductor substrate 10, and the dummy layer 36 is formed thereon. The predetermined regions of the dummy layer 36 and the gate insulating film 12 are etched. Referring to FIG. 2B, the gate insulating film 12 is side-etched from the end of the dummy layer. Thereby, the undercut part 18 is formed. With reference to FIG. 2C, the insulating film 20 is formed on the side surface of the gate insulating film 12, the upper surface of the semiconductor substrate 10, and the lower surface of the dummy layer 36. The insulating film 20 on the semiconductor substrate 10 becomes the tunnel insulating film 21, and the insulating film 20 below the dummy layer 36 becomes the second insulating film 23.

  With reference to FIG. 3A, a charge storage layer 26 is formed between the second insulating film 23 and the tunnel insulating film 21. A diffusion region 30 is formed in the semiconductor substrate 10 using the dummy layer 36 as a mask. An insulating layer 32 is formed so as to cover the dummy layer 36. The insulating layer 32 is polished until the upper surface of the dummy layer 36 is exposed. Referring to FIG. 3B, the dummy layer 36 is removed. A first insulating film 38 is formed on the gate insulating film 12, the second insulating film 23, and the insulating layer 32. A top insulating film 40 is formed from the first insulating film 38 and the second insulating film 23. Referring to FIG. 3C, a word line 34 that also serves as a gate electrode is formed on the first insulating film 38. Thus, the semiconductor device according to the comparative example is completed.

  According to Comparative Example 1, two charge storage layers 26 are formed under the gate electrode. However, since the dummy layer 36 is used, the manufacturing process is complicated. As described above, the reason for using the dummy layer 36 is to form the top insulating film 40 thicker than the tunnel insulating film 21. That is, when the tunnel insulating film 21 and the second insulating film 23 are formed using the undercut portion 18 as shown in FIG. 2C, the film thickness of the tunnel insulating film 21 and the second insulating film 23 is as follows. It will be almost the same. Therefore, as shown in FIG. 3B, after the dummy layer 36 is removed, a first insulating film 38 is formed on the second insulating film 23, and the top insulation is formed from the first insulating film 38 and the second insulating film 23. A film 40 is formed. Thereby, the top insulating film 40 can be formed thicker than the tunnel insulating film 21.

  The reason why the top insulating film 40 is formed thicker than the tunnel insulating film 21 is as follows. The tunnel insulating film 21 is required to be thin so that a tunnel current flows between the charge storage layer 26 and the channel region 44 to store or erase charges (electrons) in the charge storage layer 26. On the other hand, the top insulating film 40 is required to be thick in order to maintain the charge retention characteristics of the charge storage layer 26. That is, when erasing is performed, the top insulating film 40 is required to be thick in order to suppress the movement of charges from the gate electrode 16 to the charge storage layer 26. Therefore, the top insulating film 40 is formed thicker than the tunnel insulating film 21.

  In the following, as shown in FIG. 1, the charge storage layer 26 provided under the gate electrode is separated, the tunnel insulating film 21 and the top insulating film 40 are each set to the optimum film thickness, and the dummy layer An embodiment that provides a semiconductor device that can be manufactured easily without using 36 will be described.

  A method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 4A to 6 are cross-sectional views corresponding to the AA cross section and the BB cross section of FIG. 1, and FIG. 7A is a view corresponding to the AA cross section of FIG. FIG. 7B is a view corresponding to the BB cross section of FIG.

  Referring to FIG. 4A, a gate insulating film 12 made of a silicon oxide film is formed on a P-type silicon semiconductor substrate (or a P-type region in the silicon semiconductor substrate) 10 using a thermal oxidation method. A first insulating film 14 made of aluminum oxide is formed on the gate insulating film 12 by using an ALD (Atomic Layer Deposition) method. A gate electrode 16 made of polysilicon is formed on the first insulating film 14 using a CVD (Chemical Vapor Deposition) method. The film thicknesses of the gate insulating film 12, the first insulating film 14, and the gate electrode 16 can be set to, for example, 20 nm, 10 nm, and 150 nm, respectively. Referring to FIG. 4B, the gate electrode 16, the first insulating film 14, and the gate insulating film 12 are removed by anisotropic etching so that the bit line has a stripe shape extending in the direction to be extended. Referring to FIG. 4C, the gate insulating film 12 is side etched using, for example, a hydrofluoric acid aqueous solution. As a result, an undercut portion 18 that is a side-etched region under both ends of the gate electrode 16 is formed.

  With reference to FIG. 5A, the inner surface of the undercut portion 18 (that is, the side surface of the gate insulating film 12 on the semiconductor substrate 10 and under the first insulating film 14 of the undercut portion 18) and the gate electrode 16 are covered. An insulating film 20 made of aluminum oxide is formed using the ALD method. The film thickness of the insulating film 20 can be 5 nm, for example. A tunnel insulating film 21 is formed from the insulating film 20 on the semiconductor substrate 10 in the undercut portion 18. A second insulating film 22 is formed from the insulating film 20 under the first insulating film 14 in the undercut portion 18. The first insulating film 14 and the second insulating film 22 form a top insulating film 24. Referring to FIG. 5B, the charge storage layer 26 made of hafnium oxide is formed using the ALD method so as to be embedded in the undercut portion 18 and cover the insulating film 20. As a result, a laminate 28 composed of the tunnel insulating film 21, the charge storage layer 26 and the top insulating film 24 is formed in the undercut portion 18. Referring to FIG. 5C, the charge storage layer 26 and the insulating film 20 are etched using the gate electrode 16 as a mask.

  Referring to FIG. 6, arsenic ions are implanted into semiconductor substrate 10 using gate electrode 16 as a mask to form a bit line made of N-type diffusion region 30. An insulating layer 32 made of silicon oxide is formed so as to cover diffusion region 30 and gate electrode 16. The insulating layer 32 is polished using a CMP (Chemical Mechanical Polish) method so that the gate electrode 16 is exposed. Thereby, the upper surfaces of the gate electrode 16 and the insulating layer 32 are planarized.

  With reference to FIGS. 7A and 7B, a polysilicon layer is formed on the gate electrode 16 and the insulating layer 32. Referring to FIG. 7B, in the region between the word lines (corresponding to BB in FIG. 1), the polysilicon layer and the gate electrode 16 are removed. Referring to FIG. 7A, in the region that becomes the word line, the polysilicon layer remains and is electrically connected to the gate electrode 16 to form the word line 34 that intersects the diffusion region 30. Thereafter, an interlayer insulating film, a plug metal, a wiring layer, and the like are formed, and the semiconductor device according to the first embodiment is completed.

  In FIG. 4A, the gate insulating film 12 and the first insulating film 14 are formed using different materials. In FIG. 4C, the side etching of the gate insulating film 12 is performed using a chemical solution that the first insulating film 14 is hardly etched and the gate insulating film 12 is etched. For example, the gate insulating film 12 is made of a silicon oxide film, the first insulating film 14 is made of an aluminum oxide film, and side etching of the gate insulating film 12 is performed using a hydrofluoric acid aqueous solution. By such a process, the gate electrode 16 and the first insulating film 14 are anisotropically etched by the etching of FIG. 4C, the gate insulating film 12 is selectively side-etched using the gate electrode 16 as a mask. In this manner, the stacked gate electrode 16, first insulating film 14, and gate insulating film 12 are selectively removed.

  As described above, the first insulating film 14 of the undercut portion 18 remains as shown in FIG. 4C, so that the top insulating film 24 and the second insulating film 14 are separated from the first insulating film 14 as shown in FIG. It can be formed from the film 22. By forming the insulating film 20 using the ALD method, the tunnel insulating film 21 and the second insulating film 22 can be formed with substantially the same film thickness. For this reason, the film thickness of the top insulating film 24 (the total film thickness of the first insulating film and the second insulating film) can be made larger than the film thickness of the tunnel insulating film 21. Therefore, the film thicknesses of the top insulating film 24 and the tunnel insulating film 21 can be set to optimum thicknesses, respectively. Furthermore, since the dummy layer is not used in Example 1 as in the comparative example, the manufacturing process can be simplified as compared with the comparative example.

  In the semiconductor device manufactured in this way, a gate electrode 16 is provided above the semiconductor substrate 10 as shown in FIG. As shown in FIGS. 7A and 1, the gate insulating film 12 is provided on the semiconductor substrate 10 below the center of the gate electrode 16 (the center of the gate electrode 16 in the extending direction of the word line 34). A first insulating film 14 is provided so as to extend from above the gate insulating film 12 to both ends of the gate electrode 16 (both ends of the gate electrode 16 in the extending direction of the word line 34). The first insulating film 14 is made of a material different from that of the gate insulating film 12. A tunnel insulating film 21 is provided on the semiconductor substrate 10 on both sides of the gate insulating film 12. A charge storage layer 26 is provided so as to be sandwiched between the tunnel insulating film 21 and the first insulating film 14. A second insulating film 22 is provided below the first insulating film 14 and on the charge storage layer 26. The second insulating film 22 and the tunnel insulating film 21 are made of the same material.

  The tunnel insulating film 21 functions as a tunnel barrier of the charge storage layer 26. Therefore, it is preferable that the tunnel insulating film 21 has a large energy gap with respect to the charge storage layer 26. For example, when an aluminum oxide film is used as the tunnel insulating film 21, the charge storage layer 26 can use hafnium oxide.

  In FIG. 5A, a thin silicon oxide film having a thickness of about 1 nm may be formed on the semiconductor substrate 10 before the insulating film 20 is formed using the ALD method. Thereby, the film quality of the tunnel oxide film 21 formed of the insulating film 20 can be improved.

  Example 2 is an example in which the top insulating film is formed of the first insulating film. Referring to FIG. 8A, the steps from FIG. 4A to FIG. 4C of Example 1 are performed. Referring to FIG. 8B, an insulating film 20a made of a silicon oxide film is formed on the semiconductor substrate 10 and so as to cover the gate electrode 16 by using a thermal oxidation method. Since the thermal oxidation method is used, the insulating film 20 a is not formed under the first insulating film 14 and on the side surfaces of the gate insulating film 12. The film thickness of the insulating film 20a can be 5 nm, for example. A tunnel insulating film 21a is formed on the semiconductor substrate 10 in the undercut portion 18 from the insulating film 20a.

  Referring to FIG. 8C, a charge storage layer 26a made of a silicon nitride film is formed using a CVD method so as to be embedded in the undercut portion 18 and cover the insulating film 20a. Thereby, the first insulating film 14 is directly provided on the charge storage layer 26a. A stack 28a is formed from the tunnel insulating film 21a, the charge storage layer 26a, and the top insulating film 24a.

  Referring to FIG. 9, the semiconductor device according to the second embodiment is completed by performing the steps from FIG. 5C to FIG. 7B of the first embodiment.

  As shown in FIG. 8B of the second embodiment, when the tunnel insulating film 21a is formed, the second insulating film may not be formed, and as shown in FIG. 5A of the first embodiment, the tunnel insulating film is formed. The formation of 21 may be performed simultaneously with the formation of the second insulating film 22.

  In Example 1, when the gate insulating film 12 is a silicon oxide film, the first insulating film 14 is an aluminum oxide film in order to obtain the side etching selectivity shown in FIG. If the top insulating film 24 is formed of the same material, the insulating film 20 (that is, the tunnel insulating film 21) is formed of an aluminum oxide film. On the other hand, in Example 2, the material of the tunnel insulating film 21a can be arbitrarily selected. Thus, a silicon oxide film capable of forming a tunnel insulating film with better film quality can be used as the tunnel insulating film 21a.

  In Example 1, since the aluminum oxide film is used as the tunnel insulating film 21, the charge storage layer 26 uses hafnium oxide having an energy gap smaller than that of aluminum oxide. In Example 2, since the silicon oxide film is used as the tunnel insulating film 21, a silicon nitride film that is easier to manufacture can be used as the charge storage layer 26a.

  In the second embodiment, the film thicknesses of the top insulating film 24a and the tunnel insulating film 21a can be set independently. Further, by making the first insulating film 14a (that is, the top insulating film 24a) thicker than the tunnel insulating film 21, the tunnel insulating film 21a allows a tunnel current to flow, and the top insulating film 24a has a charge retention characteristic of the charge storage layer 26a. The film thickness can be maintained.

  Example 3 is an example in which materials of the first insulating film and the second insulating film are different. Referring to FIG. 10A, the steps from FIG. 4A to FIG. 4C of Example 1 are performed. Referring to FIG. 10B, an insulating film 20b made of silicon oxide is formed using the ALD method so as to cover the inner surface of the undercut portion 18 and the gate electrode 16. The film thickness of the insulating film 20b can be 5 nm, for example. A tunnel insulating film 21b is formed on the semiconductor substrate 10 in the undercut portion 18 from the insulating film 20b. Further, a second insulating film 22b is formed from the insulating film 20b under the first insulating film 14 of the undercut portion 18. The first insulating film 14 and the second insulating film 22b form a top insulating film 24b. A charge storage layer 26b made of a silicon nitride film is formed using a CVD method so as to be embedded in the undercut portion 18 and cover the insulating film 20b. As a result, in the undercut portion 18, a stacked layer 28b composed of the tunnel insulating film 21b, the charge storage layer 26b, and the top insulating film 24b is formed. Referring to FIG. 10C, the semiconductor device according to the third embodiment is completed by performing the steps of FIGS. 5C to 7B of the first embodiment.

  According to the third embodiment, the first insulating film 14 is formed using an aluminum oxide film, the gate insulating film 12, the second insulating film 22b, and the tunnel insulating film 21b are formed using a silicon oxide film. Accordingly, as shown in FIG. 10A, the first insulating film 14 is hardly etched when the gate oxide film 12 is side-etched. The gate insulating film 12 and the tunnel insulating film 21b can be formed of a silicon oxide film with good film quality.

  In the first to third embodiments, the charge storage layer 26 may be a conductor such as polysilicon. When the charge storage layer 26 is a conductor, as shown in FIG. 7B, if the charge storage layer 26 is provided between the word lines 34, the charge storage of the memory cell adjacent in the extending direction of the diffusion region 30 is performed. Layer 26 is electrically connected. When a conductor is used as the charge storage layer, a step of removing the charge storage layer 26 between the word lines is performed. As described above, the charge storage layer 26 can be made of any one of hafnium oxide, a silicon nitride film, and a silicon film (for example, a polysilicon film). By using a conductive silicon film as the charge storage layer, a large amount of charge can be stored. Further, by using an insulating film such as hafnium oxide or a silicon nitride film as the charge storage layer, the step of removing the charge storage layer between the word lines can be omitted.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

FIG. 1 is a plan view of a flash memory according to a comparative example, Examples 1 to 3. FIG. FIG. 2A to FIG. 2C are views showing the manufacturing process of the flash memory according to the comparative example, and are sectional views (No. 1) corresponding to the AA section of FIG. FIG. 3A to FIG. 3C are views showing the manufacturing process of the flash memory according to the comparative example, and are sectional views (No. 2) corresponding to the AA section of FIG. FIG. 4A to FIG. 4C are views showing the manufacturing process of the flash memory according to the first embodiment, and are sectional views (No. 1) corresponding to the AA section of FIG. FIG. 5A to FIG. 5C are diagrams showing the manufacturing process of the flash memory according to the first embodiment, and are sectional views (No. 2) corresponding to the AA section of FIG. FIG. 6 is a view showing the manufacturing process of the flash memory according to the embodiment 1, and is a sectional view (No. 3) corresponding to the AA section of FIG. FIGS. 7A and 7B are diagrams showing a manufacturing process of the flash memory according to the first embodiment, and FIG. 7A is a cross-sectional view corresponding to the AA cross-sectional view of FIG. FIG. 7B is a cross-sectional view corresponding to the BB cross section of FIG. FIG. 8A to FIG. 8C are diagrams showing the manufacturing process of the flash memory according to the second embodiment, and are sectional views (No. 1) corresponding to the AA section of FIG. FIG. 9 is a diagram illustrating the manufacturing process of the flash memory according to the second embodiment, and is a cross-sectional view (No. 2) corresponding to the AA cross-section of FIG. 1. FIG. 10A to FIG. 10C are diagrams showing the manufacturing process of the flash memory according to the third embodiment, and are sectional views corresponding to the AA section of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Gate insulating film 14 1st insulating film 16 Gate electrode 18 Undercut part 20 Insulating film 21 Tunnel insulating film 22 2nd insulating film 24 Top insulating film 26 Charge storage layer 30 Diffusion area 34 Word line

Claims (13)

A gate electrode provided above the semiconductor substrate;
A gate insulating film provided on the semiconductor substrate under the center of the gate electrode;
A first insulating film that is provided from above the gate insulating film to below both ends of the gate electrode and made of a material different from the gate insulating film;
A tunnel insulating film provided on the semiconductor substrate on both sides of the gate insulating film;
A charge storage layer provided to be sandwiched between the tunnel insulating film and the first insulating film;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first insulating film is thicker than the tunnel insulating film.   The semiconductor device according to claim 1, further comprising a second insulating film provided under the first insulating film and on the charge storage layer.   4. The semiconductor device according to claim 3, wherein the second insulating film and the tunnel insulating film are made of the same material.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the total thickness of the first insulating film and the second insulating film is larger than the thickness of the tunnel insulating film.   3. The semiconductor device according to claim 1, wherein the first insulating film is provided directly on the charge storage layer. The gate insulating film is made of a silicon oxide film,
The semiconductor device according to claim 1, wherein the first insulating film is made of an aluminum oxide film. The charge storage layer is made of hafnium oxide,
8. The semiconductor device according to claim 7, wherein the tunnel insulating film is made of aluminum oxide.   7. The semiconductor device according to claim 6, wherein the first insulating film is made of aluminum oxide, and the gate insulating film and the tunnel insulating film are made of a silicon oxide film.   4. The semiconductor device according to claim 3, wherein the first insulating film is made of aluminum oxide, and the gate insulating film, the second insulating film, and the tunnel insulating film are made of a silicon oxide film.   The semiconductor device according to claim 1, wherein the charge storage layer is made of a silicon film. Forming a gate insulating film on the semiconductor substrate;
Forming a first insulating film on the gate insulating film;
Forming a gate electrode on the first insulating film;
The gate electrode, the first insulating film, and the gate insulating film are selectively removed so that the gate electrode and the first insulating film are anisotropically etched and the gate insulating film is side-etched. And the process of
Forming a tunnel insulating film on a region where the gate insulating film of the semiconductor substrate is side-etched;
Forming a charge storage layer on the tunnel insulating film;
A method for manufacturing a semiconductor device, comprising: Forming a second insulating film in the side-etched region under the first insulating film;
13. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming the tunnel insulating film and the step of forming the second insulating film are performed simultaneously.

Images