JP5792759B2 - Memory system having a switch element - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a separated charge storage layer and a manufacturing method thereof.

  Nonvolatile memories, which are semiconductor devices that can rewrite data and retain stored data even when the power is turned off, are widely used. In a flash memory, which is a typical nonvolatile memory, a transistor constituting a memory cell has a floating gate or an insulating film called a charge storage layer. Data is stored by accumulating charges in the charge accumulation layer. There is a SONOS (Silicon Oxide Nitride Oxide Silicon) type flash memory that accumulates charges in a charge storage layer in an ONO (Oxide Nitride Oxide) film as a flash memory having an insulating film as a charge storage layer. Patent Document 1 discloses a flash memory (conventional example 1) having virtual ground type memory cells that operate symmetrically by switching the source and drain as one of the SONOS type flash memories.

  FIG. 1 is a cross-sectional view of a flash memory according to Conventional Example 1. Referring to FIG. 1, a tunnel insulating film 12, a charge storage layer 14, and a top insulating film 16 are sequentially provided on a semiconductor substrate 10. A bit line 18 serving as a source and a drain extends in the semiconductor substrate 10. A gate electrode 24 is provided on the top insulating film 16 between the bit lines 18. An interval L between the bit lines 18 is a channel length.

  By operating the bit line 18 (BL1) and the bit line 18 (BL2) by switching between the source and the drain, charges can be stored in the charge storage region C1 and the charge storage region C2. Thereby, 2-bit data can be stored in one transistor.

  For example, in Patent Document 2 and Patent Document 3, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a part of the side wall of the gate electrode or a part of the side wall of the gate electrode and a part of the gate insulating film are disclosed. A manufacturing method is disclosed in which a charge storage layer is formed by removing the substrate and forming a charge storage layer in the removed region.

US Pat. No. 6,011,725 JP 2005-108915 A JP 2004-343014 A

  In recent years, demands for high integration and miniaturization of memory cells are increasing. As the memory cells are highly integrated and miniaturized and the channel length is shortened, the charge storage regions C1 and C2 approach each other. As a result, the effect of a phenomenon called CBD (Complementary bit disturb) in which the charges accumulated in the charge accumulation region interfere with each other is increased, making it difficult to separate the charges from each other (that is, to read the data).

  For example, a method of suppressing the influence of CBD by adopting a structure as shown in FIG. 2 and suppressing the movement of charges accumulated in the charge accumulation region in the channel direction has been proposed. Referring to FIG. 2, a gate insulating film 22 is provided on the semiconductor substrate 10 between the bit lines 18 and below the center of the gate electrode 24. The charge storage layer 14 is provided separately on both sides of the gate insulating film 22. Thus, by providing the charge storage layer 14 separately with the gate insulating film 22 interposed therebetween, the movement of the charge stored in the charge storage region in the channel direction can be suppressed, and the influence of CBD can be suppressed.

  Further, when the channel length is shortened, charges are likely to be accumulated in the charge accumulation layer at the center of the channel, leading to a decrease in reliability during continuous reading and writing. However, in the structure shown in FIG. 2, since the gate insulating film 22 is provided in the center of the channel, it is possible to suppress the accumulation of charges in the center of the channel. Thereby, it is possible to prevent a decrease in reliability at the time of continuous reading and writing.

  Here, an example of a manufacturing method for forming the separated charge storage layer 14 will be described with reference to FIGS. For simplification, illustration and description of the tunnel insulating film 12 and the top insulating film 16 are omitted. Referring to FIG. 3A, a gate electrode 24 is formed on the semiconductor substrate 10 via a gate insulating film 22. Referring to FIG. 3B, the gate insulating film 22 is etched from both side surfaces so that the gate insulating film 22 remains below the center of the gate electrode 24. Referring to FIG. 3C, the charge storage layer 14 is formed in the region where the gate insulating film 22 is etched. Thereby, the charge storage layer 14 separated with the gate insulating film 22 interposed therebetween can be formed.

  However, when the gate insulating film 22 is etched from both sides as shown in FIG. 3B, the width of the gate insulating film 22 becomes narrow as shown in FIG. May end up.

  The present invention has been made in view of the above problems, and provides a semiconductor device capable of suppressing the collapse of the gate electrode when the gate insulating film is formed below the center of the gate electrode, and a method for manufacturing the same. With the goal.

  The present invention provides a bit line provided so as to extend into a semiconductor substrate, a gate electrode provided above the semiconductor substrate between the bit lines, and a lower center of the gate electrode on the semiconductor substrate. A gate insulating film provided, a charge storage layer provided on the semiconductor substrate under the gate electrode so as to sandwich the gate insulating film in the bit line width direction, and the bit line extending direction A first insulating film provided between the gate electrodes and on the semiconductor substrate, wherein the width of the first insulating film in the bit line width direction is wider than the width of the gate insulating film. This is a featured semiconductor device. According to the present invention, the first insulating film having a large width in the bit line width direction and the gate insulating film having a small width are formed so as to be alternately arranged in the extending direction of the bit line. For this reason, when the gate insulating film having a narrow width in the bit line width direction is formed below the center of the gate electrode, the gate electrode can be prevented from falling. In addition, the charge storage layer is provided separately so as to sandwich the gate insulating film in the bit line width direction. For this reason, the influence of CBD can be suppressed.

  In the above configuration, the first insulating film may be embedded in a groove provided in the semiconductor substrate between the gate electrodes in the bit line extending direction. According to this configuration, the fringe current flowing in the semiconductor substrate around the gate electrode can be suppressed.

  In the above structure, a protective film may be provided on a side surface of the first insulating film, and the material of the protective film may be different from the material of the gate insulating film and the material of the first insulating film. According to this configuration, the first insulating film having a width wider than that of the gate insulating film can be easily formed.

  In the above structure, the gate insulating film and the first insulating film may be a silicon oxide film, and the protective film may be a silicon nitride film.

  In the above structure, the upper surface of the first insulating film may be provided farther from the surface of the semiconductor substrate than the upper surface of the gate insulating film. According to this configuration, the fall of the gate electrode can be further suppressed.

  In the above structure, a word line that is electrically connected to the gate electrode, is provided on the gate electrode, and extends across the bit line can be provided. In the above structure, the charge storage layer may be one of a polysilicon film and a silicon nitride film.

  The present invention includes a step of forming a second insulating film on a semiconductor substrate, and removing the second insulating film formed on the semiconductor substrate in a region other than regions where bit lines and gate electrodes are to be formed. Forming a first opening in the second insulating film; forming a first insulating film in the first opening; forming a conductive layer on the second insulating film; A second opening is formed by removing the conductive layer and the second insulating film formed on the semiconductor substrate in a region where a line is to be formed, and the conductive layer is formed between the second openings. Forming the gate electrode; removing the second insulating film formed under the gate electrode from the second opening; and forming a gate insulating film made of the second insulating film under the center of the gate electrode And forming under the gate electrode Forming a charge storage layer in a region from which the second insulating film has been removed; and forming the bit line defined by the second opening in the semiconductor substrate. Device manufacturing method. According to the present invention, the first insulating film having a large width in the bit line width direction and the gate insulating film having a small width can be formed so as to be alternately arranged in the extending direction of the bit line. For this reason, when the gate insulating film having a narrow width in the bit line width direction is formed below the center of the gate electrode, the gate electrode can be prevented from falling. Further, the charge storage layer can be formed separately so as to sandwich the gate insulating film in the bit line width direction. For this reason, the influence of CBD can be suppressed.

  In the above configuration, the method includes a step of forming a groove portion in the semiconductor substrate below the first opening, and the step of forming the first insulating film includes a step of forming the first insulating film in the groove portion. It can be configured. According to this configuration, the fringe current flowing in the semiconductor substrate around the gate electrode can be suppressed.

  In the above configuration, the material of the first insulating film is a material that is difficult to remove from the second insulating film when the second insulating film formed under the gate electrode is removed to form the gate insulating film. There can be a certain configuration. According to this configuration, the first insulating film having a width wider than the width of the gate insulating film in the bit line width direction can be easily formed.

  In the above configuration, before the step of forming the first insulating film, the method includes a step of forming a protective film on a side surface of the first opening, and the material of the protective film is formed under the gate electrode When the gate insulating film is formed by removing the second insulating film, the material may be a material that is difficult to remove from the second insulating film. According to this configuration, the first insulating film having a width wider than the width of the gate insulating film in the bit line width direction can be easily formed.

  In the above configuration, the step of forming the protective film on the exposed portion of the side surface of the first insulating film after the step of forming the first insulating film and before the step of forming the conductive layer It can be. According to this configuration, the first insulating film having a width wider than the width of the gate insulating film in the bit line width direction can be more easily formed.

  In the above configuration, the first insulating film and the second insulating film may be silicon oxide films, and the protective film may be a silicon nitride film.

  In the above configuration, the step of forming the first opening includes the step of forming the first opening by removing the second insulating film using a mask layer formed on the second insulating film. And after the step of forming the first opening, and before the step of forming the first insulating film, a step of narrowing the width of the mask layer can be provided.

  In the above configuration, the step of forming the first insulating film includes the step of forming the first insulating film such that the upper surface of the first insulating film is separated from the surface of the semiconductor substrate from the upper surface of the second insulating film. It can be set as the structure containing. According to this configuration, the fall of the gate electrode can be further suppressed.

  In the above structure, the step of forming the gate insulating film may be a step of forming the gate insulating film by etching the second insulating film using isotropic etching. According to this configuration, the gate insulating film can be easily formed below the center of the gate electrode.

  The above structure may include a step of forming a word line extending over the bit line so as to be electrically connected to the gate electrode. In the above structure, the charge storage layer may be one of a polysilicon film and a silicon nitride film.

  According to the present invention, the first insulating film having a large width in the bit line width direction and the gate insulating film having a small width can be formed so as to be alternately arranged in the extending direction of the bit line. Thereby, when the gate insulating film having a narrow width in the bit line width direction is formed below the center of the gate electrode, the gate electrode can be prevented from falling.

FIG. 1 is a cross-sectional view of a flash memory according to Conventional Example 1. FIG. 2 is a cross-sectional view for explaining a method of suppressing charge interference. FIG. 3 is a cross-sectional view for explaining an example of a method for manufacturing a separated charge storage layer. FIG. 4 is a cross-sectional view for explaining a problem that occurs when a separated charge storage layer is manufactured. FIG. 5 is a top view of the flash memory according to the first embodiment. 6A is a cross-sectional view taken along the line AA in FIG. 5, FIG. 6B is a cross-sectional view taken along the line BB in FIG. 5, and FIG. 6C is a cross-sectional view taken along the line CC in FIG. FIG. 6D is a cross-sectional view taken along the line D-D in FIG. 5. FIG. 7A to FIG. 7C are views (No. 1) showing the method for manufacturing the flash memory according to the first embodiment, and FIG. 7A is a cross-sectional view corresponding to AA in FIG. 7B is a cross-sectional view corresponding to the line BB in FIG. 5, and FIG. 7C is a cross-sectional view corresponding to the line CC in FIG. FIG. 8A to FIG. 8C are views (No. 2) showing the manufacturing method of the flash memory according to the first embodiment, and FIG. 8A is a cross-sectional view corresponding to AA in FIG. 8B is a cross-sectional view corresponding to the line BB in FIG. 5, and FIG. 8C is a cross-sectional view corresponding to the line CC in FIG. FIGS. 9A to 9C are views (No. 3) illustrating the method for manufacturing the flash memory according to the first embodiment, and FIG. 9A is a cross-sectional view corresponding to AA in FIG. FIG. 9B is a cross-sectional view corresponding to BB in FIG. 5, and FIG. 9C is a cross-sectional view corresponding to CC in FIG. FIGS. 10A to 10C are views (No. 4) illustrating the method for manufacturing the flash memory according to the first embodiment, and FIG. 10A is a cross-sectional view corresponding to AA in FIG. FIG. 10B is a cross-sectional view corresponding to the line BB in FIG. 5, and FIG. 10C is a cross-sectional view corresponding to the line CC in FIG. 11A to 11C are views (No. 5) illustrating the method for manufacturing the flash memory according to the first embodiment, and FIG. 11A is a cross-sectional view corresponding to AA in FIG. 11 (b) is a cross-sectional view corresponding to the line BB in FIG. 5, and FIG. 11 (c) is a cross-sectional view corresponding to the line CC in FIG. 12A to 12D are views (No. 6) illustrating the method for manufacturing the flash memory according to the first embodiment, and FIG. 12A is a cross-sectional view corresponding to the line AA in FIG. 12 (b) is a cross-sectional view corresponding to B-B in FIG. 5, FIG. 12 (c) is a cross-sectional view corresponding to C-C in FIG. 5, and FIG. It is sectional drawing corresponded between DD. FIG. 13A to FIG. 13D are views (No. 1) showing a manufacturing method of a flash memory according to the second embodiment, and FIGS. 13A and 13B are AA of FIG. FIG. 13C and FIG. 13D are cross-sectional views corresponding to BB in FIG. 5. FIGS. 14A to 14D are views (No. 2) showing the method for manufacturing the flash memory according to the second embodiment, and FIGS. 14A and 14B are AA of FIG. FIG. 14C and FIG. 14D are cross-sectional views corresponding to BB in FIG. 5. FIG. 15A to FIG. 15D are views (No. 3) showing the manufacturing method of the flash memory according to the second embodiment, and FIG. 15A and FIG. FIG. 15C and FIG. 15D are cross-sectional views corresponding to BB in FIG. 5. FIG. 16A to FIG. 16D are views (No. 1) showing the manufacturing method of the flash memory according to the third embodiment, and FIG. 16A and FIG. FIG. 16C and FIG. 16D are cross-sectional views corresponding to BB in FIG. 5. FIGS. 17A to 17D are views (No. 2) illustrating the manufacturing method of the flash memory according to the third embodiment. FIGS. 17A and 17B are cross-sectional views taken along line AA in FIG. FIG. 17C and FIG. 17D are cross-sectional views corresponding to BB in FIG. 5.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 5 is a top view of the flash memory according to the first embodiment. 6A is a cross-sectional view taken along the line AA in FIG. 5, FIG. 6B is a cross-sectional view taken along the line BB in FIG. 5, and FIG. 6C is a cross-sectional view taken along the line CC in FIG. FIG. 6D is a cross-sectional view taken along the line D-D in FIG. 5. In FIG. 5, the bit line 18 and the like are shown through the first silicon oxide film 34, the interlayer insulating film 36, and the like.

  Referring to FIGS. 5 and 6B, a bit line 18 that is an N-type diffusion region is provided so as to extend into the semiconductor substrate 10 that is a P-type silicon substrate. A gate insulating film 22 made of a silicon oxide film is provided on the semiconductor substrate 10 between the bit lines 18, and the tunnel insulating film 12, the charge storage layer, and the gate insulating film 22 are sandwiched in the width direction of the bit line 18. 14 and a top insulating film 16 are sequentially provided. The tunnel insulating film 12 and the top insulating film 16 are made of a silicon oxide film, and the charge storage layer 14 is made of a polysilicon film. As a result, an OPO (Oxide Poly-Silicon Oxide) film 26 is formed on the semiconductor substrate 10. A gate electrode 24 made of a polysilicon film is provided on the gate insulating film 22 and the OPO film 26. A second silicon oxide film 39 is provided on the side surface of the gate electrode 24. A word line 20 made of a polysilicon film is provided on the gate electrode 24 and is electrically connected to the gate electrode 24 and extends across the bit line 18. Referring to FIGS. 6B and 6C, the gate insulating film 22 is provided on the semiconductor substrate 10 below the center of the gate electrode 24.

  Referring to FIGS. 5, 6A, 6C, and 6D, a groove (not shown) is provided in the semiconductor substrate 10 between the gate electrodes 24 in the extending direction of the bit line 18. That is, a groove is provided in the semiconductor substrate 10 around the gate electrode 24 between the bit lines 18. A first insulating film 30 made of a silicon oxide film is provided so as to be embedded in the groove. A protective film 32 made of a silicon nitride film that is a different material from the gate insulating film 22 and the first insulating film 30 is provided on the side and bottom surfaces of the first insulating film 30. With reference to FIG. 6A and FIG. 6B, the width of the first insulating film 30 in the width direction of the bit line 18 is formed wider than the width of the gate insulating film 22. With reference to FIG. 6C, the upper surface of the first insulating film 30 is provided farther from the surface of the semiconductor substrate 10 than the upper surface of the gate insulating film 22. That is, the upper surface of the first insulating film 30 protrudes from the upper surface of the gate insulating film 22. The upper surface of the first insulating film 30 and the upper surface of the gate electrode 24 are provided on the same plane.

  With reference to FIGS. 6A and 6B, a first silicon oxide film 34 is provided on the bit line 18. Referring to FIGS. 6A, 6C, and 6D, an interlayer insulating film 36 made of a silicon oxide film is provided between word lines 20.

  Next, a manufacturing method of the flash memory according to the first embodiment will be described with reference to FIGS. 7A to 12D. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, and FIG. 12A are cross-sectional views corresponding to AA in FIG. It is. 7 (b), FIG. 8 (b), FIG. 9 (b), FIG. 10 (b), FIG. 11 (b) and FIG. 12 (b) are cross-sectional views corresponding to the line BB in FIG. . 7C, FIG. 8C, FIG. 9C, FIG. 10C, FIG. 11C, and FIG. 12C are cross-sectional views corresponding to CC in FIG. . FIG. 12D is a cross-sectional view corresponding to the line DD in FIG.

  Referring to FIGS. 7A to 7C, a second insulating film 37 made of a silicon oxide film is formed on the semiconductor substrate 10 which is a P-type silicon substrate by using a thermal oxidation method. A mask layer 38 made of a silicon nitride film is formed on the second insulating film 37 using a CVD (chemical vapor deposition) method. The mask layer 38 has an opening in a region other than the region where the bit line 18 and the gate electrode 24 are to be formed. Using the mask layer 38 as a mask, the second insulating film 37 and a part of the semiconductor substrate 10 are etched using RIE (reactive ion etching). As a result, the first opening 40 is formed in the second insulating film 37 formed in a region other than the region where the bit line 18 and the gate electrode 24 are to be formed, and the semiconductor substrate 10 in the semiconductor substrate 10 below the first opening 40 is formed. A groove portion 28 is formed in the groove. Thereafter, a silicon nitride film is deposited on the entire surface by CVD, and a protective film 32 made of a silicon nitride film is formed on the side surface of the first opening 40 and the inner surface of the groove 28.

  With reference to FIG. 8A to FIG. 8C, the first insulating film 30 made of a silicon oxide film is formed by using a high-density plasma CVD method so as to be embedded in the first opening 40 and the groove 28. To do. The first insulating film 30 is formed so that the upper surface of the first insulating film 30 is farther from the surface of the semiconductor substrate 10 than the upper surface of the second insulating film 37. That is, the upper surface of the first insulating film 30 is formed so as to protrude from the upper surface of the second insulating film 37. Thereafter, the mask layer 38 and the protective film 32 formed on the side surfaces of the mask layer 38 are removed. Thereby, the side surface of the first insulating film 30 in the portion embedded in the first opening 40 and the groove 28 is covered with the protective film 32.

  With reference to FIGS. 9A to 9C, a conductive layer 42 made of a polysilicon film is formed on the first insulating film 30 and the second insulating film 37 by CVD. The conductive layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched using the RIE method. Thereby, a second opening 44 penetrating the conductive layer 42 and the second insulating film 37 is formed. Of the conductive layer 42 formed between the second openings 44, the conductive layer 42 formed on the second insulating film 37 becomes the gate electrode 24. The length of the gate electrode 24 corresponding to the channel length is about 90 nm.

  Referring to FIGS. 10A to 10C, the gate electrode is formed from the second opening 44 using a wet etching method using hydrofluoric acid so that the second insulating film 37 remains below the center of the gate electrode 24. 24, the second insulating film 37 formed below is removed. As a result, an undercut portion 35 having a depth of about 30 nm from the side surface of the gate electrode 24 is formed in the region where the second insulating film 37 has been removed under both ends of the gate electrode 24. Below the center of the gate electrode 24, a gate insulating film 22 made of the second insulating film 37 and having a width of about 30 nm is formed. The first insulating film 30 is not etched because it is covered with the protective film 32.

  11A to 11C, the tunnel insulating film 12 and the top insulating film 16 made of a silicon oxide film are formed in the undercut portion 35 by using a thermal oxidation method. At this time, the side surfaces and top surfaces of the gate electrode 24 and the conductive layer 42 are also oxidized, and a second silicon oxide film 39 is formed. Thereafter, a polysilicon film is formed on the semiconductor substrate 10 so as to cover the gate electrode 24 and the first insulating film 30 by LP-CVD (low pressure chemical vapor deposition). Since the LP-CVD method has excellent wraparound characteristics, a polysilicon film is also formed in the undercut portion 35 between the tunnel insulating film 12 and the top insulating film 16. Thereafter, the polysilicon film is oxidized to form a second silicon oxide film 39 using a thermal oxidation method. Since the polysilicon film formed in the undercut portion 35 between the tunnel insulating film 12 and the top insulating film 16 is in a deep region and hardly oxidizes, the polysilicon film remains as it is, and the charge storage layer 14 It becomes. The second silicon oxide film 39 formed on the semiconductor substrate 10 in the second opening 44 is removed. Arsenic ions are implanted into the semiconductor substrate 10 from the second opening 44. Thereby, the inside of the semiconductor substrate 10 is extended, and the bit line 18 which is an N-type diffusion region defined by the second opening 44 is formed.

  Referring to FIGS. 12A to 12D, the first silicon oxide film 34 is formed by using a high-density plasma CVD method so as to be embedded in the second opening 44. Thereafter, the conductive layer 42 and the like formed on the first insulating film 30 are polished using a CMP (Chemical Mechanical Polishing) method so that the upper surface of the first insulating film 30 is exposed. On the gate electrode 24, a word line 20 made of a polysilicon film is formed which is electrically connected to the gate electrode 24 and extends across the bit line 18. An interlayer insulating film 36 made of a silicon oxide film is formed between the word lines 20. Thus, the flash memory according to the first embodiment is completed.

  According to the first embodiment, as shown in FIGS. 7A to 7C, the second insulating film 37 is formed on the semiconductor substrate 10, and the bit line 18 and the gate electrode 24 are to be formed. The second insulating film 37 formed on the semiconductor substrate 10 in the other region is removed to form the first opening 40. As shown in FIGS. 8A to 8C, the first insulating film 30 is formed in the first opening 40. As shown in FIGS. 9A to 9C, the conductive layer 42 is formed on the second insulating film 37. The conductive layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are removed to form a second opening 44, and the conductive layer 42 is formed between the second openings 44. A gate electrode 24 made of is formed. As shown in FIGS. 10A to 10C, the second insulating film 37 formed under the gate electrode 24 is removed from the second opening 44, and the second insulation is formed under the center of the gate electrode 24. A gate insulating film 22 made of the film 37 is formed. With this manufacturing method, the first insulating film 30 having a large width in the width direction of the bit line 18 and the gate insulating film 22 having a small width are formed alternately in the extending direction of the bit line 18. For this reason, even when the narrow gate insulating film 22 is formed below the center of the gate electrode 24, the wide first insulating film 30 is formed next to the gate insulating film 22, so that the gate insulating film 22 is formed. The fall of the gate electrode 24 formed thereon can be suppressed.

  Further, as shown in FIGS. 8A to 8C, the first insulating film 30 formed in the first opening 40 and the groove 28 is formed such that the upper surface of the first insulating film 30 is the second insulating film 37. The case where it forms so that it may leave | separate from the semiconductor substrate 10 surface from an upper surface is preferable. That is, as shown in FIG. 6C, it is preferable that the upper surface of the first insulating film 30 is provided farther from the surface of the semiconductor substrate 10 than the upper surface of the gate insulating film 22. In this case, the gate electrode 24 formed on the gate insulating film 22 is formed so as to be sandwiched between the first insulating films 30. Thereby, even when the width of the gate insulating film 22 is narrow, the fall of the gate electrode 24 formed on the gate insulating film 22 can be further suppressed.

  Further, as shown in FIGS. 10A to 10C, the second insulating film 37 formed under the gate electrode 24 is removed from the second opening 44, and under the both ends of the gate electrode 24, underscores are formed. The cut portion 35 is formed, and the gate insulating film 22 is formed below the center of the gate electrode 24. As shown in FIGS. 11A to 11C, the charge storage layer 14 is formed in the undercut portion 35 formed under both ends of the gate electrode 24. Thereby, the charge storage layer 14 separated with the gate insulating film 22 interposed therebetween can be formed. For this reason, the influence of CBD can be suppressed.

  Further, as shown in FIGS. 7A to 7C, a groove 28 is formed in the semiconductor substrate 10 in a region other than the region where the bit line 18 and the gate electrode 24 are to be formed. That is, the groove 28 is formed in the semiconductor substrate 10 below the first opening 40. With reference to FIG. 8A to FIG. 8C, the first insulating film 30 is formed so as to be embedded in the groove 28. Thus, the first insulating film 30 is formed in the semiconductor substrate 10 in a region other than the region where the bit line 18 and the gate electrode 24 are to be formed. In other words, the first insulating film 30 is formed in the semiconductor substrate 10 between the gate electrodes 24 in the extending direction of the bit line 18. That is, the first insulating film 30 is formed in the semiconductor substrate 10 around the gate electrode 24 between the bit lines 18. For this reason, the fringe current flowing through the semiconductor substrate 10 around the gate electrode 24 can be suppressed. The fringe current causes a malfunction when reading data. Therefore, data read characteristics and the like can be improved by suppressing the fringe current.

  Further, as shown in FIGS. 7A to 7C, a protective film 32 is formed on the side surface of the first opening 40, and thereafter, as shown in FIGS. 8A to 8C. The first insulating film 30 is formed in the first opening 40. Thereby, the protective film 32 is formed on the side surface of the first insulating film 30. The material of the first insulating film 30 and the second insulating film 37 is a silicon oxide film, and the material of the protective film 32 is a silicon nitride film. Therefore, when the gate insulating film 22 is formed by removing the second insulating film 37 formed under the gate electrode 24 from the second opening 44, as shown in FIGS. In addition, the protective film 32 is difficult to remove from the second insulating film 37. Therefore, when forming the gate insulating film 22, the first insulating film 30 covered with the protective film 32 can be left as it is. Therefore, the first insulating film 30 having a width wider than that of the gate insulating film 22 can be easily formed. Therefore, the material of the protective film 32 is a material that is difficult to remove from the second insulating film 37 when the second insulating film 37 formed under the gate electrode 24 is removed to form the gate insulating film 22. The case is preferred.

  When the material of the first insulating film 30 is a material that is difficult to remove from the second insulating film 37 when the second insulating film formed under the gate electrode 24 is removed to form the gate insulating film 22. But you can. In this case, the first insulating film 30 having a width wider than that of the gate insulating film 22 can be easily formed without forming the protective film 32 on the side surface of the first insulating film 30. For this reason, a manufacturing process can be shortened and simplified.

  Further, as shown in FIGS. 10A to 10C, the second insulating film 37 formed under the gate electrode 24 is removed, and the gate insulating film 22 is formed under the center of the gate electrode 24. The step is preferably performed by removing the second insulating film 37 by using isotropic etching such as wet etching with hydrofluoric acid. In this case, since the second insulating film 37 is similarly removed from both side surfaces, the gate insulating film 22 made of the second insulating film 37 can be easily formed below the center of the gate electrode 24.

  Further, as shown in FIGS. 12A to 12D, the word line 20 is formed on the gate electrode 24 so as to be electrically connected to the gate electrode 24 and extending across the bit line 18. Although the case is shown as an example, the present invention is not limited to this. For example, without forming the word line 20, a wiring layer is formed on the gate electrode 24 so as to extend across the bit line 18 via an interlayer insulating film or the like, and the wiring layer and the gate electrode 24 are connected to the interlayer insulating film. It may be electrically connected with a plug metal or the like formed in a similar manner. Further, instead of the gate electrode 24, a dummy film is formed in a region where the gate electrode 24 is to be formed, the dummy film is removed before the word line 20 is formed, and then the dummy film is removed. The word line 20 that also serves as the gate may be formed so as to be embedded.

  Further, as shown in FIGS. 10A to 10C, when the second insulating film 37 formed under the gate electrode 24 is removed from the second opening 44, the first insulating film 30 is a protective film. Since it is covered with 32, it is difficult to remove, and the undercut portion 35 is difficult to be formed under both ends of the first insulating film 30. That is, it is difficult to form the charge storage layer 14 below both ends of the first insulating film 30. Therefore, among the charge storage layers 14 formed below both ends of the gate electrode 24, the charge storage layers 14 adjacent in the extending direction of the bit line 18 are formed separately from each other. Thereby, even when the charge storage layer 14 is made of a polysilicon film, charges can be stored locally under the gate electrode 24. In addition, the charge storage layer 14 is not limited to a polysilicon film, and may be formed of other materials as long as it is a material capable of storing charges, such as a silicon nitride film.

  In the second embodiment, after forming the first opening 40 in the second insulating film 37 and before forming the first insulating film 30 in the first opening 40, there is a step of reducing the width of the mask layer 38. It is. A method for manufacturing the flash memory according to the second embodiment will be described with reference to FIGS. 13 (a), FIG. 13 (b), FIG. 14 (a), FIG. 14 (b), FIG. 15 (a), and FIG. 15 (b) are cross-sectional views corresponding to A-A in FIG. . 13 (c), 13 (d), 14 (c), 14 (d), 15 (c) and 15 (d) are cross-sectional views corresponding to BB in FIG. .

  With reference to FIGS. 13A and 13C, a second insulating film 37 is formed on the semiconductor substrate 10. On the second insulating film 37, a mask layer 38 having an opening in a region other than the region where the bit line 18 and the gate electrode 24 are to be formed is formed. The second insulating film 37 and the semiconductor substrate 10 are etched using the mask layer 38 as a mask. As a result, the first opening 40 is formed in the second insulating film 37, and the groove 28 is formed in the semiconductor substrate 10. Etchback is performed on the mask layer 38 to reduce the width of the mask layer 38, and then a protective film 32 is deposited over the entire surface.

  With reference to FIG. 13B and FIG. 13D, the first insulating film 30 is formed so as to be embedded in the first opening 40 and the groove 28. Since the width of the mask layer 38 is narrower than that of the first embodiment, the width T1 of the upper portion of the first insulating film 30 is wider than that of the first embodiment. Thereafter, the mask layer 38 and the like are removed.

  With reference to FIGS. 14A and 14C, a conductive layer 42 is formed on the first insulating film 30 and the second insulating film 37. The conductive layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched to form the second opening 44. Since the width T1 of the upper portion of the first insulating film 30 is wider than that of the first embodiment, the width of the conductive layer 42 formed on the side surface of the upper portion of the first insulating film 30 after the second opening 44 is formed. T2 is smaller than that in the first embodiment. Of the conductive layer 42 formed between the second openings 44, the conductive layer 42 formed on the second insulating film 37 becomes the gate electrode 24.

  14B and 14D, the second insulating film 37 under the gate electrode 24 is removed from the second opening 44 so that the second insulating film 37 remains below the center of the gate electrode 24. To do. As a result, an undercut portion 35 that is a region where the second insulating film 37 is removed is formed under both ends of the gate electrode 24, and the gate insulating film 22 made of the second insulating film 37 is formed under the center of the gate electrode 24. Is done.

  Referring to FIGS. 15A and 15C, tunnel insulating film 12 and top insulating film 16 are formed in undercut portion 35 using a thermal oxidation method. At this time, the gate electrode 24 and the conductive layer 42 are also oxidized, and a second silicon oxide film 39 is formed on the surfaces of the gate electrode 24 and the conductive layer 42. A charge storage layer 14 is formed between the tunnel insulating film 12 and the top insulating film 16. The bit line 18 defined by the second opening 44 is formed to extend into the semiconductor substrate 10.

  Referring to FIGS. 15B and 15D, a first silicon oxide film 34 is formed so as to be embedded in the second opening 44. Thereafter, the conductive layer 42 and the like formed on the first insulating film 30 are polished so that the upper surface of the first insulating film 30 is exposed. A word line 20 is formed on the gate electrode 24 and is electrically connected to the gate electrode 24 and extends across the bit line 18. An interlayer insulating film 36 is formed between the word lines 20. Thus, the flash memory according to the second embodiment is completed.

  In Example 1, for example, in the step of forming the second opening 44 shown in FIGS. 9A to 9C, the width of the conductive layer 42 is taken into account in consideration of the positional deviation of the second opening 44. May be formed to be wide. That is, the width of the conductive layer 42 formed on the side surface of the first insulating film 30 may be increased. In this case, when the side surface and the upper surface of the conductive layer 42 shown in FIGS. 11A to 11C are oxidized, the conductive layer 42 formed on the side surface of the first insulating film 30 is not completely oxidized. In addition, a part of the conductive layer 42 may remain. Even in this case, in the step of forming the word line 20 shown in FIG. 12A to FIG. 12D, etching is performed for patterning the word line 20 so that the side surface of the first insulating film 30 is formed. The formed conductive layer 42 can be removed, and the gate electrode 24 can be prevented from being connected in the extending direction of the bit line 18. According to the second embodiment, as shown in FIGS. 13A and 13C, the width of the mask layer 38 is narrowed after the first opening 40 is formed, so that FIGS. As shown in (d), the width T1 of the upper part of the first insulating film 30 can be increased. Therefore, as shown in FIGS. 14A and 14C, the width T2 of the conductive layer 42 formed on the upper side surface of the first insulating film 30 after the formation of the second opening 44 is narrowed. can do. Therefore, as shown in FIGS. 15A and 15C, when the tunnel insulating film 12 and the top insulating film 16 are formed using the thermal oxidation method, they are formed on the side surfaces of the first insulating film 30. The conductive layer 42 is easily oxidized and can prevent the conductive layer 42 from remaining on the side surface of the first insulating film 30.

  Example 3 is an example in which a step of forming a protective film on the exposed portion of the side surface of the first insulating film 30 is formed after the first insulating film 30 is formed and before the conductive layer 42 is formed. . A method for manufacturing a flash memory according to the third embodiment will be described with reference to FIGS. 16 (a), 16 (b), 17 (a) and 17 (b) are cross-sectional views corresponding to the line AA in FIG. 16C, FIG. 16D, FIG. 17C, and FIG. 17D are cross-sectional views corresponding to the line BB in FIG.

  With reference to FIGS. 16A and 16C, a second insulating film 37 is formed on the semiconductor substrate 10. A mask layer (not shown) having an opening in a region other than the region where the bit line 18 and the gate electrode 24 are to be formed is formed on the second insulating film 37. The second insulating film 37 and the semiconductor substrate 10 are etched using the mask layer as a mask. As a result, a first opening (not shown) is formed in the second insulating film 37, and a groove (not shown) is formed in the semiconductor substrate 10. A protective film 32a is formed on the side surface of the first opening and the inner surface of the groove. A first insulating film 30 is formed so as to be embedded in the first opening and the groove. The mask layer is removed. After that, the protective film 32b is formed in the portion that has been in contact with the mask layer and where the side surface of the first insulating film 30 is exposed. The protective film 32b can be formed by depositing the entire surface of the silicon nitride film and then etching back the silicon nitride film.

  With reference to FIG. 16B and FIG. 16D, the conductive layer 42 is formed on the first insulating film 30 and the second insulating film 37. The conductive layer 42 and the second insulating film 37 formed on the semiconductor substrate 10 in the region where the bit line 18 is to be formed are etched to form the second opening 44. Of the conductive layer 42 formed between the second openings 44, the conductive layer 42 formed on the second insulating film 37 becomes the gate electrode 24. Due to the protective film 32b formed on the side surface of the first insulating film 30, the width T2 of the conductive layer 42 formed on the side of the first insulating film 30 is narrowed. The second insulating film 37 formed under the gate electrode 24 is removed from the second opening 44 so that the second insulating film 37 remains under the center of the gate electrode 24. As a result, an undercut portion 35 that is a region where the second insulating film 37 is removed is formed under both ends of the gate electrode 24, and the gate insulating film 22 made of the second insulating film 37 is formed under the center of the gate electrode 24. Is done.

  Referring to FIGS. 17A and 17C, tunnel insulating film 12 and top insulating film 16 are formed in undercut portion 35 using a thermal oxidation method. At this time, the gate electrode 24 and the conductive layer 42 are also oxidized, and a second silicon oxide film 39 is formed on the surfaces of the gate electrode 24 and the conductive layer 42. A charge storage layer 14 is formed between the tunnel insulating film 12 and the top insulating film 16. The bit line 18 defined by the second opening 44 is formed to extend into the semiconductor substrate 10.

  Referring to FIGS. 17B and 17D, a first silicon oxide film 34 is formed so as to be embedded in the second opening 44. Thereafter, the conductive layer 42 and the like formed on the first insulating film 30 are polished so that the upper surface of the first insulating film 30 is exposed. A word line 20 is formed on the gate electrode 24 and is electrically connected to the gate electrode 24 and extends across the bit line 18. An interlayer insulating film 36 is formed between the word lines 20. Thus, the flash memory according to the third embodiment is completed.

  According to the third embodiment, as shown in FIGS. 16A and 16C, after the first insulating film 30 is formed, the side surface of the first insulating film 30 is formed before the conductive layer 42 is formed. A protective film 32b is formed on the exposed portion. Thereby, the side surface of the first insulating film 30 is completely covered with the protective film 32a and the protective film 32b. Therefore, as shown in FIGS. 16B and 16D, when the second insulating film 37 formed under the gate electrode 24 is removed from the second opening 44, the first insulating film 30 is It can suppress more that it is removed. Therefore, the first insulating film 30 having a width wider than that of the gate insulating film 22 can be formed more easily.

  As shown in FIGS. 16B and 16D, the width T2 of the conductive layer 42 formed on the side of the first insulating film 30 is thin. For this reason, as shown in FIGS. 17A and 17C, the conductive layer 42 formed on the side of the first insulating film 30 is easily oxidized. Thereby, it is possible to suppress the conductive layer 42 from remaining on the side of the first insulating film 30 as in the second embodiment.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Tunnel insulating film 14 Charge storage layer 16 Top insulating film 18 Bit line 20 Word line 22 Gate insulating film 24 Gate electrode 26 OPO film 28 Groove part 30 1st insulating film 32 Protective film 32a Protective film 32b Protective film 34 1st Silicon oxide film 35 Undercut portion 36 Interlayer insulating film 37 Second insulating film 38 Mask layer 39 Second silicon oxide film 40 First opening 42 Conductive layer 44 Second opening

Claims (10)

Forming a second insulating film on the semiconductor substrate;
Removing the second insulating film formed on the semiconductor substrate in a region other than a region where the bit line and the gate electrode are to be formed, and forming a first opening in the second insulating film;
Forming a first insulating film in the first opening;
Forming a conductive layer on the second insulating film;
A second opening is formed by removing the conductive layer and the second insulating film formed on the semiconductor substrate in a region where the bit line is to be formed, and the second opening is formed between the second opening and the conductive layer. Forming the gate electrode,
Removing the second insulating film formed under the gate electrode from the second opening, and forming a gate insulating film made of the second insulating film under the center of the gate electrode;
Forming a charge storage layer in a region where the second insulating film formed under the gate electrode is removed;
Forming the bit line defined by the second opening in the semiconductor substrate;
Forming an insulating layer on the bit line including a portion extending along the bit line and having the same width as the bit line;
I have a,
In the step of forming the first insulating film, the first insulating film is formed so that an upper surface of the first insulating film is higher than an upper surface of the second insulating film when the surface of the semiconductor substrate is used as a reference. Including the step of forming,
A method for manufacturing a semiconductor device. Forming a groove in the semiconductor substrate below the first opening;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first insulating film includes a step of forming the first insulating film in the groove.   The material of the first insulating film is a material that is difficult to remove from the second insulating film when forming the gate insulating film by removing the second insulating film formed under the gate electrode. A method for manufacturing a semiconductor device according to claim 1 or 2. A step of forming a protective film on a side surface of the first opening before the step of forming the first insulating film;
The material of the protective film is a material that is difficult to remove from the second insulating film when the gate insulating film is formed by removing the second insulating film formed under the gate electrode. The method for manufacturing a semiconductor device according to claim 1.   After the step of forming the first insulating film, before the step of forming the conductive layer, the method includes a step of forming the protective film on an exposed portion of the side surface of the first insulating film. A method for manufacturing a semiconductor device according to claim 4.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the first insulating film and the second insulating film are silicon oxide films, and the protective film is a silicon nitride film. The step of forming the first opening is a step of forming the first opening by removing the second insulating film using a mask layer formed on the second insulating film,
7. The method according to claim 1, further comprising a step of narrowing a width of the mask layer after the step of forming the first opening and before the step of forming the first insulating film. The manufacturing method of the semiconductor device of description. The step of forming the gate insulating film, by etching the second insulating film by isotropic etching, any of claims 1 to 7, characterized in that the step of forming the gate insulating film A method for manufacturing a semiconductor device according to claim 1. Electrically connected to the gate electrode on the gate electrode, of any one of claims 1 to 8, characterized in that it comprises a step of forming a word line which extends to intersect with the bit lines A method for manufacturing a semiconductor device. Manufacturing method of the charge storage layer is a semiconductor device according to any one of claims 1, wherein 9 that is one of a polysilicon film and a silicon nitride film.

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