JP2010118596A - Nonvolatile semiconductor storage device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of stably holding a potential of a shield electrode arranged between the adjacent gate electrodes to relieve a proximity effect by the shield electrode, and a method of manufacturing the same. <P>SOLUTION: The shield electrode 25 is arranged between the gate electrodes G1, G2 which are arranged adjacent to each other on a semiconductor substrate 1 and have a floating gate 11 and a control gate 16 via a gate sidewall insulating film 22. Then, at least a part of the shield electrode 25 is constituted of a silicide layer consisting of metal and silicon. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a memory cell transistor having a stacked structure of a floating gate and a control gate, and a method of manufacturing the same.

  In a flash memory which is a nonvolatile semiconductor memory device, capacitive coupling between floating gates of adjacent memory cell transistors increases as the memory cell transistor becomes finer. For this reason, it is known that the threshold value of the memory cell transistor to be read fluctuates (hereinafter referred to as proximity effect) under the influence of the potential fluctuation of the floating gate of the adjacent memory cell transistor. That is, according to the writing or erasing state of the floating gate of the adjacent memory cell transistor, the threshold of the memory cell transistor to be read is (change in the writing state of the adjacent memory cell transistor) and (floating gate of the adjacent memory cell transistor) The problem of fluctuating as a function of the product of the capacitance coupling ratio) becomes apparent.

  In order to reduce this problem, a nonvolatile semiconductor memory device has been proposed in which a shield electrode is disposed between gate electrodes along the gate electrode in order to reduce capacitive coupling between floating gates of adjacent gate electrodes (for example, , See Patent Document 1).

However, in the memory cell transistor described in Patent Document 1 described above, the shield electrode is formed of polycrystalline silicon. When miniaturization is considered, the pitch between the gate electrodes is narrowed, and thin polycrystalline silicon is embedded therein. In order to use polycrystalline silicon as a shield electrode, it is necessary to form a p-type semiconductor by doping polycrystalline silicon, for example, with a high concentration of B (Boron). However, if the polycrystalline silicon becomes thinner than a certain width, B is absorbed into a material adjacent to the polycrystalline silicon, for example, a silicon dioxide film, and the B concentration in the polycrystalline silicon is lowered. As a result, there is a problem that the polycrystalline silicon of the shield electrode is easily depleted depending on the potential state of the surrounding gate electrode and cannot function as the shield electrode because the potential of the shield electrode cannot be maintained.
Japanese Patent Laying-Open No. 2006-310564 (page 20, FIG. 3)

  In view of the above-described problems, the present invention provides a nonvolatile semiconductor memory device capable of stably holding the potential of the shield electrode and reducing the proximity effect by the shield electrode, and a method for manufacturing the same. It is aimed.

  In order to achieve the above object, a nonvolatile semiconductor device of one embodiment of the present invention includes a semiconductor substrate, a floating gate formed over the semiconductor substrate with a gate insulating film interposed therebetween, and an inter-gate insulating film over the floating gate A plurality of gate electrodes arranged adjacent to each other, a gate sidewall insulating film provided on each sidewall of each gate electrode, and between the adjacent gate electrodes And a shield electrode which is disposed through the gate side wall insulating film and which is at least partially composed of a silicide layer made of metal and silicon.

  According to another aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor device, comprising: forming a gate insulating film on a semiconductor substrate; forming a conductive film on the gate insulating film; After a polycrystalline silicon film is stacked via an insulating film, the conductive film, the inter-gate insulating film, and the polycrystalline silicon film are patterned to form a floating gate of the conductive film and a control gate of polycrystalline silicon. Forming a gate electrode disposed adjacent to each other, forming a gate sidewall insulating film on a sidewall of the gate electrode, and a shield electrode made of a polycrystalline silicon film on the gate sidewall insulating film And a step of siliciding the polycrystalline silicon film of the control gate and the polycrystalline silicon film of the shield electrode at the same time.

  ADVANTAGE OF THE INVENTION According to this invention, the non-volatile semiconductor memory device which can hold | maintain the electric potential of a shield electrode stably and can reduce a proximity effect by a shield electrode, and its manufacturing method can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the present invention is applied to a NAND flash memory.

(First embodiment)
FIG. 1 is a plan view of a memory cell array portion of a NAND flash memory according to the first embodiment of the present invention.

  As shown in FIG. 1, a plurality of element regions 2 are provided on the main surface of a p-type semiconductor substrate 1. Each of these element regions 2 is formed in a strip shape along a predetermined direction, that is, the X-axis direction, and is arranged apart from each other.

  These element regions 2 are insulated and isolated by an element isolation region 3. In the element region 2, a plurality of n-type diffusion regions 4 serving as the source / drain of the memory cell transistor C are formed separated from each other by the word line WL of the memory cell transistor. A plurality of memory cell transistors C are connected in series by sharing adjacent n-type diffusion regions 4 to form a NAND string.

  On the element region 2 and the element isolation region 3, the word lines WL of the plurality of memory cell transistors C are arranged along the direction orthogonal to the predetermined direction, that is, the Y-axis direction, and the selection gate line of the selection gate transistor S is selected. SL is arranged in parallel with the word line WL.

  The channel of the memory cell transistor C is formed below the word line WL that intersects each element region 2, and the channel of the selection gate transistor S is formed below the selection gate line SL that intersects each element region 2. Each is formed. The n-type diffusion region 4 of the select gate transistor S is connected to the source line contact 40 and the bit line contact 41, respectively.

  In addition, shield electrodes 25 are arranged between the plurality of word lines WL and between the plurality of word lines WL and the selection gate line SL so as to be parallel to the word lines WL and the selection gate line SL, respectively. The shield electrode 25 is connected to the shield electrode contact 42 around the memory cell array portion.

  The shield electrode contact is connected to the shield electrode control circuit 101 by wiring.

  FIG. 2 is a cross-sectional view of the NAND flash memory taken along the line BB in FIG. As shown in FIG. 2, a plurality of n-type diffusion regions 4 serving as source / drain are formed in the element region 2 on the main surface of the p-type semiconductor substrate 1 so as to be separated from each other.

  A gate insulating film 10 having a thickness of about 5 to 10 nm is formed on the upper surface of the element region 2 between the adjacent n-type diffusion regions 4. On the gate insulating film 10 of the memory cell transistor C, a floating gate 11 made of a polycrystalline silicon film is formed. On the gate insulating film 10 of the select gate transistor S, a lower gate electrode 12 made of a polycrystalline silicon film is formed.

  On the upper surfaces of the floating gate 11 and the lower gate electrode 12, an inter-gate insulating film 13 composed of an ONO (Oxide Nitride Oxide) film, a metal oxide film such as Al 2 O 3, HfO, or a laminated film thereof is formed. On the inter-gate insulating film 13 of the memory cell transistor C, a control gate 16 composed of a polycrystalline silicon film 14 and a silicide layer (CoSi) 15 is formed. That is, the gate electrode G1 in which the floating gate 11 and the control gate 16 are electrically insulated by the inter-gate insulating film 13 is configured.

  On the other hand, on the intergate insulating film 13 of the select gate transistor S, an upper gate electrode 17 composed of a polycrystalline silicon film 14 and a silicide layer 15 similar to the control gate 16 is formed. In the select gate transistor S, the lower gate electrode 12 and the upper gate electrode 17 are electrically connected through the opening 13 a formed in the inter-gate insulating film 13. That is, the gate electrode G2 in which the lower gate electrode 12 and the upper gate electrode 17 are electrically connected is configured.

  Further, the control gates 16 of adjacent memory cell transistors C are connected to each other in the X-axis direction, and are extended in the X-axis direction to form the word line WL. Further, the upper gate electrodes 17 of the adjacent selection gate transistors S are connected to each other and extended in the X-axis direction to form a selection gate line SL.

  A gate sidewall insulating film 22 such as a silicon dioxide film is provided on the sidewalls of the gate electrode G1 of the memory cell transistor C and the gate electrode G2 of the selection gate transistor S.

  A shield electrode 25 is formed on the gate sidewall insulating film 22. The shield electrode 25 is composed of a silicide layer in which a polycrystalline silicon film is silicided.

  An interlayer insulating film 30 is deposited between the gate electrodes G1 and G2 including the shield electrode 25 and on the gate electrodes G1 and G2, and a bit line or a source line (not shown) is formed on the interlayer insulating film 30. ing. The source line is connected to the n-type diffusion layer 4 via the source line contact 40, and the bit line is connected to the n-type diffusion layer 4 via the bit line contact 41.

  Next, a method for manufacturing the NAND flash memory according to the first embodiment of the present invention will be described with reference to FIG. 3-1 (a) to 6-15 (a) are process cross-sectional views along AA in FIG. 1, and FIGS. 3-1 (b) to 6-15 (b) are diagrams. It is process sectional drawing along BB of 1. FIG.

  First, FIG. 3-1 will be described. A gate insulating film 10 is formed on the semiconductor substrate 1. The gate insulating film 10 is an insulating film such as a silicon dioxide film, a silicon nitride film, a film obtained by adding nitrogen to a silicon dioxide film, or a silicon dioxide film or a silicon nitride film formed by a deposition process.

  Next, as shown in FIG. 3B, a polycrystalline silicon film 11 doped with an impurity such as P (phosphorus) or As (arsenic) is deposited on the gate insulating film 10, Then, a pad material 51 such as a silicon nitride film is deposited. The polycrystalline silicon film 11 may be formed by depositing a polycrystalline silicon film that is not doped with impurities, and then ion-implanting impurities such as P and As and activating them by heat treatment. The polycrystalline silicon film 11 later becomes the floating gate 11 in the memory cell transistor, and becomes the lower gate electrode 12 in the selection gate transistor.

  Next, as shown in FIG. 3C, a photoresist (not shown) is applied on the pad material 51, and a photoresist pattern for forming an element area (AA: Active Area) is formed by a photolithography technique. . Using this photoresist pattern as a mask, the pad material 51, the polycrystalline silicon film 11, the gate oxide film 10, and the semiconductor substrate 1 are etched by RIE (Reactive Ion Etching), respectively, and an element isolation region (Shallow Trench) is formed in the semiconductor substrate 1. Isolation: STI) 3 is formed to form a separation groove 5.

  Next, as shown in FIG. 3-4, an element isolation insulating film 6 such as a silicon oxide film is deposited in the isolation trench 5 by HDP (High Density Plasma) method. Next, the element isolation insulating film 6 is planarized by a CMP (Chemical Mechanical Polishing) method using the pad material 51 as a stopper. After planarizing the element isolation insulating film 6, the element isolation insulating film 6 is etched back to the height of the polycrystalline silicon film 2 by RIE. Subsequently, the pad material 51 is peeled off by a wet method such as phosphoric acid.

  Next, as shown in FIG. 4-5, in order to increase the capacitance between the floating gate 11 and the control gate 16, the upper portion of the element isolation insulating film 6 is etched by the RIE method. The side wall surface is exposed. The amount of etching at this time is targeted so that the gate insulating film 10 is not exposed, and the amount of etching needs to be controlled so that the variation in capacitance between the floating gate 11 and the control gate 16 does not increase.

  Next, as shown in FIG. 4-6, an intergate insulating film 13 is deposited on the polycrystalline silicon film 11 and the element isolation insulating film 6. The intergate insulating film 13 may be an ONO film, a metal oxide film such as Al 2 O 3 or HfO, or a high dielectric film made of a laminated film thereof.

  Next, a process for electrically connecting the upper gate electrode 17 (corresponding to the control gate 16 of the memory cell transistor) of the selection gate transistor S and the lower gate electrode 12 (corresponding to the floating gate 11 of the memory cell transistor) is performed. explain. First, a polycrystalline silicon film that is a part of the upper gate electrode 17, a BSG (Boron Silicate Glass) film that serves as a mask material (not shown) for etching the inter-gate insulating film, and the like are formed on the inter-gate insulating film 13. accumulate. A photoresist is applied to the upper surface of the BSG film, and a photoresist pattern for forming the opening 13a of the inter-gate insulating film 13 is formed by a photolithography technique. The opening 13 a is for electrically connecting the polycrystalline silicon film 11 that is the lower gate electrode 12 and the polycrystalline silicon film 14 that is a part of the upper gate electrode 17.

  Next, after etching the BSG film by the RIE method using the photoresist pattern as a mask, the photoresist pattern is peeled off, and the polycrystalline silicon film and the inter-gate insulating film 13 are etched by the RIE method using the BSG film as a mask. Thus, the opening 13a of the inter-gate insulating film 13 is formed, and the lower gate electrode 12 and the upper gate electrode 17 of the select gate transistor S are electrically connected as will be described later.

  Next, the BSG film is removed by a wet process such as hydrofluoric acid.

  Next, as shown in FIG. 4-7, the polycrystalline silicon film 14 and the pad material 52 doped with impurities such as P and As are deposited on the inter-gate insulating film 13. The polycrystalline silicon film 14 becomes the control gate 11 in the memory cell transistor C and the upper gate electrode 17 in the selection gate transistor S. This doped polycrystalline silicon film 14 is formed by depositing a polycrystalline silicon film not doped with impurities such as P and As, and then ion-implanting impurities such as P and As and activating them by a thermal process. Also good. The pad material 52 is preferably a silicon dioxide film in order to ensure an etching selectivity with respect to the polycrystalline silicon film 24 for forming a shield electrode 25 described later.

  Next, as shown in FIGS. 4-8, a photoresist (not shown) is apply | coated on the pad material 52, The photoresist pattern for forming a gate electrode is formed using a photolithographic technique. The pad material 52 is processed by the RIE method using this photoresist pattern as a mask. Next, after removing the photoresist pattern, the polycrystalline silicon film 14, the intergate insulating film 13, and the polycrystalline silicon film 11 are sequentially processed by the RIE method using the pad material 52 as a mask to form gate electrodes G1 and G2. To do.

  Next, as shown in FIGS. 5-9, a first silicon dioxide film 20 is formed on the sidewalls of the gate electrodes G1, G2 by thermal oxidation. The first silicon dioxide film 20 may not be formed.

  Next, as shown in FIG. 5-10, a silicon dioxide film is deposited on the gate electrodes G1 and G2 including the first silicon dioxide film 20, and RIE is performed to leave the sidewalls. A second silicon dioxide film 21 is formed on the silicon dioxide film 20. The first and second silicon dioxide films 20 and 21 become the gate sidewall insulating film 22 for electrically insulating and separating the shield electrode 25 and the gate electrodes G1 and G2. Here, only the gate sidewall insulating film 22 is illustrated.

  Next, as shown in FIG. 5-11, a polycrystalline silicon film 24 for forming the shield electrode 25 is formed on the gate sidewall insulating film 22 of the gate electrodes G1 and G2. This is formed by performing anisotropic etching after depositing a polycrystalline silicon film on the entire surface of the semiconductor substrate. This polycrystalline silicon film 24 serves as an offset for forming the source / drain 4 of the memory cell transistor C and select gate transistor S. Since the polycrystalline silicon film 24 becomes the shield electrode 25 in the cell array portion, the gate electrodes G 1 and G 2 need to be insulated and separated by the gate sidewall insulating film 22. After forming the polycrystalline silicon film 24, As ions are implanted into the semiconductor substrate 1 in the element region 2 to form the source / drain 4, and activated by high-temperature annealing, and the source / drain is formed on both sides of the gate electrodes G1 and G2. N-type diffusion regions 4 are formed as drains.

  Next, as shown in FIG. 5-12, the pad material 52 is removed by the RIE method to expose the upper surface of the polycrystalline silicon film 14 of the gate electrodes G1 and G2.

  Next, as shown in FIG. 6-13, a Co / Ti / TiN film 53 is deposited on the entire surface of the semiconductor substrate 1 and annealed at about 450 ° C. in order to perform a silicidation step. By this silicidation process, the upper portions of the polycrystalline silicon film 14 of the gate electrodes G1 and G2 are silicided, and a silicide layer 15 is formed. Since the polycrystalline silicon film 24 on the gate sidewall insulating film 22 is a thin film, it is completely silicided to form a shield electrode 25 made of a silicide layer. On the other hand, the Co / Ti / TiN film 53 on the insulating film is removed by a wet process without forming a silicide layer since there is no reactive polycrystalline silicon film.

  In this embodiment, Co is used as a metal for siliciding silicon. However, W, Ni, Ti, or a compound of these metals may be used. Metals other than these metals can be used as long as they react with silicon to form a low-resistance silicide.

  In this embodiment, the polycrystalline silicon film constituting the shield electrode is completely silicided. However, the shield electrode is constituted depending on the thickness of Co / Ti / TiN deposited for silicidation and annealing conditions. Only the surface portion of the polycrystalline silicon film may be silicided. Also in such a case, the resistance of the shield electrode is reduced as compared with the case of only the polycrystalline silicon film because the surface of the polycrystalline silicon film is silicided.

  Next, as shown in FIG. 6-15, an interlayer insulating film 30 is deposited on the gate electrode including the gate electrodes G1 and G2, and after the interlayer insulating film 30 is planarized by CMP, the source line contact 40, bit A formation process of the line contact 41 is performed. At this time, a shield electrode contact 42 for applying a constant potential to the shield electrode 25 is simultaneously formed.

  Thereafter, a NAND flash memory is formed through a normal wiring process after the bit line forming process.

  As described above, according to the first embodiment of the present invention, since the shield electrode 25 is composed of the silicide layer, the potential is stabilized up to the end of the shield electrode 25 (the end opposite to the shield electrode contact). . Therefore, the proximity effect from the adjacent memory cell transistor can be shielded up to the end of the shield electrode 25.

  In addition, there is an advantage that it is not necessary to add a new process as the shield electrode 25 is formed. This is because the side wall of the gate electrode G is an element that is commonly required for the memory cell transistor C and the peripheral transistor, and in order to reduce the resistance of the gate electrode, silicidation with Co or the like is an indispensable process. is there. This is because the silicide layer of the shield electrode 25 is formed by siliciding the polycrystalline silicon film 24 on the side wall of the gate electrode simultaneously with the polycrystalline silicon film 14 of the gate electrode.

  Further, since the shield electrode 25 is formed not only on the height of the floating gate but also on the entire side wall of the gate electrode G, not only the proximity effect from the floating gate 11 of the adjacent memory cell transistor C but also the control gate 16 Proximity effects can also be reduced.

  The shield electrode 25 is connected to the shield electrode control circuit 101 and given a potential. At this time, if a constant potential (for example, 0 V) is applied to the shield electrode 25, the proximity effect from the adjacent memory cell transistor C can be shielded.

  That is, a method of using the shield electrode 25 at 0 V (Vss) at the time of data writing and data reading can be considered.

  In addition, a method of use is also conceivable in which the potential applied to the shield electrode 25 is changed between data writing and data reading. That is, it is a usage method in which the potential of the shield electrode 25 is set to about 10 V when data is written and 0 V when data is read.

  This is because, when writing data, the control gate 16 used for writing is boosted to a high voltage of about 25V, so that when the shield electrode 25 is 0V, the breakdown voltage of the sidewall insulating film 22 may be a problem, but the voltage of the shield electrode This is because the voltage stress applied to the sidewall insulating film 22 is reduced when the voltage is set to about 10 V (about Vpass). There is also an advantage that the control gate 16 adjacent to the 10V shield electrode 25 can be boosted in a shorter time than the control gate 16 adjacent to the 0V shield electrode 25 is boosted to 25V.

  On the other hand, since the control gate 16 is only boosted to Vread (about 5V) at the time of data reading, the above breakdown voltage problem does not occur, and the potential of the shield electrode 25 may be set to 0V.

(Second Embodiment)
Next, a NAND flash memory according to the second embodiment of the present invention will be described. FIG. 7 is a plan view of a NAND flash memory according to the second embodiment of the present invention. 8 is a cross-sectional view in the BB direction of FIG.

  In the present embodiment, a single shield electrode 35 is provided between the gate electrode G1 of the adjacent memory cell transistor C and between the gate electrode G1 of the memory cell transistor C and the gate electrode G2 of the selection gate transistor S. It is formed so as to completely fill the space between the electrodes G. The shield electrode 35 is composed of a polycrystalline silicon film 33 and a silicide layer 34 in which the upper part of the polycrystalline silicon layer 33 is silicided. The shield electrode 35 has one side surface in contact with the gate sidewall insulating film 22 of one adjacent gate electrode G1 or G2, and the other side surface in contact with the gate side wall insulating film 22 of the other adjacent gate electrode G1 or G2. Is provided. Unlike the first embodiment, the rest of the configuration is the same in that the polysilicon film 14 of the control gate 16 or the upper gate electrode 17 is formed at substantially the same height. The same reference numerals are given and the description is omitted.

  Next, a method for manufacturing the NAND flash memory according to the second embodiment will be described with reference to FIGS.

  As shown in FIG. 9A, until the gate sidewall insulating film 22 is formed on the sidewalls of the gate electrode G1 of the memory cell transistor C and the gate electrode G2 of the select gate transistor S, the same as in the first embodiment. is there. In this embodiment, before forming the polycrystalline silicon film 33 on the gate sidewall insulating film 22, ion implantation for forming the source / drain is performed to form the n-type diffusion region 4.

  Next, as shown in FIG. 9B, a polycrystalline silicon film 33 for forming the shield electrode 35 is deposited between the gate electrodes G1 and G2, and the polycrystalline silicon film 33 is formed on the control gate 16 by the RIE method. Etch back to almost the same height as the crystalline silicon film 14.

  Next, as shown in FIG. 9C, the pad material 52 on the gate electrodes G1 and G2 is removed by RIE.

  Next, as shown in FIG. 9-4, a Co / Ti / TiN film 53 is deposited on the polycrystalline silicon film 14 of the gate electrodes G1 and G2 and the polycrystalline silicon film 33 between the gate electrodes G1 and G2.

  Next, as shown in FIG. 10-5, annealing is performed to silicide the polycrystalline silicon film 14 of the control gate 16 and the polycrystalline silicon film 33 between the gate electrodes G 1 and G 2. A silicide layer 15 is formed, a silicide layer 34 is formed on the polycrystalline silicon film 33 between the gate electrodes G1 and G2, and a shield electrode 35 composed of the polycrystalline silicon film 33 and the silicide layer 34 is formed.

  Next, as shown in FIG. 10-6, a photoresist is applied on the gate electrodes G1 and G2 and the shield electrode 35, and a resist pattern for forming the bit line contact 41 between the select gate transistors S by photolithography technology. 54 is formed. Next, using this resist pattern 54 as a mask, silicide layer 34 and polycrystalline silicon film 33 on n-type diffusion region 4 of select gate transistor S are etched by RIE.

  Next, as shown in FIG. 10-7, after removing the resist pattern 54, the interlayer insulating film 30 is deposited on the entire surface of the semiconductor substrate, and after the interlayer insulating film 30 is planarized, the source line contact 40, bit A formation process of the line contact 41 is performed. At this time, a shield electrode contact 42 for applying a constant potential to the shield electrode 35 is also formed at the same time.

  As described above, according to the second embodiment, the shield electrode 35 completely fills the space between the adjacent gate electrodes G1 and G2, so that the cross-sectional area of the shield electrode 35 is larger than that of the first embodiment. Become. Therefore, the resistance of the shield electrode 35 is further reduced as compared with the first embodiment, and the potential of the shield electrode 35 is stabilized, so that the proximity effect can be blocked.

  In the second embodiment, as shown in FIG. 11, the thickness of the Co / Ti / TiN film 53 deposited in FIG. 10-4 is increased and the annealing time in FIG. 10-5 is increased. The polysilicon film 14 of the control gate 16 and the upper gate electrode 17 is fully silicided to form the control gate 16 and the upper gate electrode 17 with the silicide layer 15, and the polysilicon film 33 of the shield electrode 45 is fully silicided. The shield electrode 45 may be only the silicide layer 34 by (Fully Silicided: FUSI). In this case, the resistance of the shield electrode 45 can be made smaller than that in the case of being partially silicided.

  Further, the metal used for silicidation is not limited to Co, as in the first embodiment.

  In the first and second embodiments, the case where the present invention is applied to a NAND flash memory has been described. However, the present invention can also be applied to other nonvolatile semiconductor memory devices such as a NOR flash memory. The present invention can also be applied to a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure in which a charge storage layer made of a silicon nitride film is used instead of the floating gate structure.

1 is a plan view of a NAND flash memory according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view of the NAND flash memory according to the first embodiment of the present invention, cut along the line BB in FIG. 1 and viewed in the direction of the arrow. FIG. 3A is a cross-sectional view of a NAND flash memory according to the first embodiment of the present invention (part 1), and FIGS. Process sectional views cut and viewed in the arrow direction, FIGS. 3-1 (b) to 3-4 (b) are process sectional views cut along the line BB in FIG. 1 and viewed in the arrow direction. is there. FIG. 4-5 (a) to FIG. 4-8 (a) are taken along line AA in FIG. 1 in process cross-sectional views (part 2) of the NAND flash memory according to the first embodiment of the present invention. 4-5 (b) to 4-8 (b) are sectional views taken along the line BB in FIG. 1 and viewed in the direction of the arrows. is there. FIG. 5-9 (a) to FIG. 5-12 (a) are taken along line AA in FIG. 5-9 (b) to 5-12 (b) are cross-sectional views cut along the line BB in FIG. 1 and viewed in the direction of the arrows. is there. FIGS. 6-13 (a) to 6-15 (a) are taken along line AA of FIG. 1 in process sectional views (No. 4) of the NAND flash memory according to the first embodiment of the present invention. 6-13 (b) to 6-15 (b) are process cross-sectional views cut along the line BB in FIG. 1 and viewed in the direction of the arrows. is there. FIG. 6 is a plan view of a NAND flash memory according to a second embodiment of the present invention. FIG. 8 is a cross-sectional view of a NAND flash memory according to a second embodiment of the present invention, cut along the line BB in FIG. 7 and viewed in the direction of the arrow. FIG. 9A to FIG. 9C are cross-sectional views taken along the line B-B in FIG. It is process sectional drawing seen. FIG. 10-4 to FIG. 10-7 are sectional views taken along the line BB in FIG. 7 in the process cross-sectional view (No. 2) of the NAND flash memory according to the second embodiment of the present invention. It is process sectional drawing seen. FIG. 10 is a cross-sectional view of a NAND flash memory according to a modification of the second embodiment of the present invention, cut along the line BB in FIG. 7 and viewed in the direction of the arrow.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element region 3 Element isolation region 4 Diffusion region 5 Isolation groove 6 Element isolation insulating film 10 Gate insulating film 11 Floating gate 12 Lower gate 13 Intergate insulating film 13a Openings 14, 24, 33 Polycrystalline silicon films 15, 34 Silicide layer 16 Control gate 17 Upper gate electrode 20 Silicon dioxide film 22 Gate sidewall insulating films 25, 35, 45 Shield electrode 30 Interlayer insulating film 40 Source line contact 41 Bit line contact 42 Shield electrode contact 51, 52 Pad material 53 Co / TiN / Ti film 54 resist pattern 101 shield electrode control circuit C memory cell transistor S selection gate transistor G1 gate electrode G2 of memory cell transistor gate electrode WL of selection gate transistor word line SL selection gate line

Claims (5)

A semiconductor substrate;
A plurality of gate electrodes having a floating gate formed on the semiconductor substrate through a gate insulating film and a control gate stacked on the floating gate through an inter-gate insulating film, and arranged adjacent to each other When,
A gate sidewall insulating film provided on each sidewall of each gate electrode;
A shield electrode disposed between the adjacent gate electrodes with the gate sidewall insulating film interposed therebetween, and at least a part of which is formed of a silicide layer made of metal and silicon;
A non-volatile semiconductor memory device comprising:   2. The nonvolatile semiconductor according to claim 1, wherein one side surface of the shield electrode is in contact with one of the opposing gate side wall insulating films, and the other side surface is in contact with the other opposing gate side wall insulating film. Storage device.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the shield electrode is provided on each of the opposing gate sidewall insulating films.   5. The nonvolatile semiconductor memory device according to claim 1, wherein a potential in a range including 0 V to 10 V is applied to the shield electrode. 6. Forming a gate insulating film on the semiconductor substrate;
A conductive film is formed on the gate insulating film, and a polycrystalline silicon film is stacked on the conductive film via an inter-gate insulating film, and then the conductive film, the inter-gate insulating film, and the polycrystalline silicon film are formed. Patterning to form a gate electrode having a floating gate of the conductive film and a control gate of polycrystalline silicon and disposed adjacent to each other;
Forming a gate sidewall insulating film on the sidewall of the gate electrode;
Forming a shield electrode made of a polycrystalline silicon film on the gate sidewall insulating film;
Simultaneously siliciding the polycrystalline silicon film of the control gate and the polycrystalline silicon film of the shield electrode;
A method of manufacturing a nonvolatile semiconductor memory device, comprising:

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