JP5491694B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP5491694B2
JP5491694B2 JP2007308094A JP2007308094A JP5491694B2 JP 5491694 B2 JP5491694 B2 JP 5491694B2 JP 2007308094 A JP2007308094 A JP 2007308094A JP 2007308094 A JP2007308094 A JP 2007308094A JP 5491694 B2 JP5491694 B2 JP 5491694B2
Authority
JP
Japan
Prior art keywords
insulating film
charge storage
layer
forming
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007308094A
Other languages
Japanese (ja)
Other versions
JP2009135155A (en
Inventor
文彦 井上
貴之 丸山
正幸 佐藤
Original Assignee
スパンション エルエルシー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by スパンション エルエルシー filed Critical スパンション エルエルシー
Priority to JP2007308094A priority Critical patent/JP5491694B2/en
Priority to PCT/US2008/013227 priority patent/WO2009070336A1/en
Priority to TW97146131A priority patent/TWI471936B/en
Publication of JP2009135155A publication Critical patent/JP2009135155A/en
Application granted granted Critical
Publication of JP5491694B2 publication Critical patent/JP5491694B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Description

本発明は、半導体装置およびその製造方法に関し、より詳細には、分離した電荷蓄積層を有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a separated charge storage layer and a manufacturing method thereof.

データの書き換えが可能で、電源をＯＦＦしても記憶データを保持し続ける半導体装置である不揮発性メモリが広く利用されている。代表的な不揮発性メモリであるフラッシュメモリにおいては、メモリセルを構成するトランジスタが電荷蓄積層と呼ばれるフローティングゲートもしくは絶縁膜を有している。この電荷蓄積層に電荷を蓄積させることによりデータを記憶する。   Nonvolatile memories, which are semiconductor devices that can rewrite data and retain stored data even when the power is turned off, are widely used. In a flash memory, which is a typical nonvolatile memory, a transistor constituting a memory cell has a floating gate or an insulating film called a charge storage layer. Data is stored by accumulating charges in the charge accumulation layer.

近年、１メモリセルに記憶させることが可能なデータ量を増やす為に様々な方法が提案されている。例えば、ソース領域とドレイン領域とを切り替えて動作させて、１つのメモリセル内の電荷蓄積層に２つの電荷蓄積領域を形成する仮想接地型フラッシュメモリがある。これによれば、１メモリセルに２ビットのデータを記憶することが可能となる。   In recent years, various methods have been proposed to increase the amount of data that can be stored in one memory cell. For example, there is a virtual ground flash memory that operates by switching between a source region and a drain region to form two charge storage regions in a charge storage layer in one memory cell. According to this, 2-bit data can be stored in one memory cell.

例えば、特許文献１には、ＳＴＩ領域により電荷蓄積層が分離されたフラッシュメモリが開示されている。例えば、非特許文献１には、窒化膜で形成されたマスク層を用いて、電荷蓄積層を分離するＳＴＩ領域を形成する技術が開示されている。
特開２００２−３１３９６７号公報 Non-Volatile Semiconductor Memory Workshop 2007 p110-p111 For example, Patent Document 1 discloses a flash memory in which a charge storage layer is separated by an STI region. For example, Non-Patent Document 1 discloses a technique of forming an STI region that separates a charge storage layer using a mask layer formed of a nitride film.
JP 2002-313967 A Non-Volatile Semiconductor Memory Workshop 2007 p110-p111

例えば、電荷蓄積層に絶縁膜を用いた仮想接地型フラッシュメモリの場合、メモリセル内において電荷蓄積層がチャネル方向で分離されていないと、ＣＢＤ（Complementary bit disturb）と呼ばれる、２つの電荷蓄積領域に蓄積された電荷が互いに干渉する影響が大きくなる。これにより、２つの電荷蓄積領域に蓄積された電荷の切り分けが難しくなる。特に、例えば、電荷蓄積層に導電膜を用いた仮想接地型フラッシュメモリの場合は、蓄積した電荷が電荷蓄積層内を移動するため、メモリセル内において電荷蓄積層をチャネル方向で分離させる必要がある。   For example, in a virtual ground type flash memory using an insulating film as a charge storage layer, if the charge storage layer is not separated in the channel direction in the memory cell, two charge storage regions called CBD (Complementary bit disturb) The influence of the charges accumulated in the interference with each other increases. This makes it difficult to separate the charges accumulated in the two charge accumulation regions. In particular, for example, in the case of a virtual ground type flash memory using a conductive film for the charge storage layer, the stored charge moves in the charge storage layer, so that it is necessary to separate the charge storage layer in the channel direction in the memory cell. is there.

また、隣接するメモリセル間で電荷蓄積層が繋がっている場合は、電荷蓄積層に蓄積された電荷が、電荷蓄積層を移動することにより、隣接するメモリセルの閾値電圧に影響を及ぼす場合がある。   If the charge storage layer is connected between adjacent memory cells, the charge stored in the charge storage layer may affect the threshold voltage of the adjacent memory cell by moving the charge storage layer. is there.

本発明は、上記課題に鑑みなされたものであり、メモリセル内においてチャネル方向で分離し、且つ隣接するメモリセル間で分離する電荷蓄積層を有する半導体装置およびその製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a charge storage layer that is isolated in the channel direction in a memory cell and that is separated between adjacent memory cells, and a method for manufacturing the same. And

本発明は、半導体基板上に電荷蓄積層を形成する工程と、前記電荷蓄積層上に形成されたマスク層をマスクにして、前記電荷蓄積層と前記半導体基板とに、延伸する第１溝部を形成する工程と、前記第１溝部に埋め込むように絶縁膜を形成する工程と、前記マスク層と前記絶縁膜とに、前記第１溝部に交差して延伸する第２溝部を形成する工程と、前記第２溝部下に形成された前記電荷蓄積層を酸化させてゲート絶縁膜を形成する工程と、前記第２溝部に埋め込むように第１導電層を形成する工程と、前記マスク層を除去する工程と、前記第１導電層幅方向における両側面に第２導電層を形成し、前記第１導電層と前記第２導電層とからなるワードラインを形成する工程と、前記ワードラインをマスクに前記電荷蓄積層を除去する工程と、を有することを特徴とする半導体装置の製造方法である。本発明によれば、メモリセル内においてチャネル方向で分離し、且つ隣接するメモリセル間で分離する電荷蓄積層を形成することができる。さらに、電荷蓄積層とワードラインとは自己整合的に形成することができる。   The present invention includes a step of forming a charge storage layer on a semiconductor substrate, and a first groove portion extending between the charge storage layer and the semiconductor substrate using the mask layer formed on the charge storage layer as a mask. Forming an insulating film so as to be embedded in the first groove, and forming a second groove extending in the mask layer and the insulating film so as to cross the first groove; Forming a gate insulating film by oxidizing the charge storage layer formed under the second groove, forming a first conductive layer so as to be embedded in the second groove, and removing the mask layer; Forming a second conductive layer on both sides in the width direction of the first conductive layer, forming a word line composed of the first conductive layer and the second conductive layer, and using the word line as a mask Removing the charge storage layer; A method of manufacturing a semiconductor device which is characterized in that. According to the present invention, it is possible to form a charge storage layer that is separated in the channel direction in a memory cell and separated between adjacent memory cells. Furthermore, the charge storage layer and the word line can be formed in a self-aligned manner.

上記構成において、前記第１導電層を形成する工程の後、前記第１導電層と前記マスク層とをマスクに、前記絶縁膜をエッチングする工程を有する構成とすることができる。この構成によれば、隣接するワードライン同士が電気的に接続することを抑制できる。   In the above structure, after the step of forming the first conductive layer, a step of etching the insulating film using the first conductive layer and the mask layer as a mask can be employed. According to this configuration, it is possible to suppress the adjacent word lines from being electrically connected.

上記構成において、前記絶縁膜を形成する工程は、前記絶縁膜の上面と前記マスク層の上面とが同一面になるよう、前記絶縁膜を形成する工程である構成とすることができる。この構成によれば、隣接するワードライン同士が電気的に接続することを抑制できる。   In the above configuration, the step of forming the insulating film may be a step of forming the insulating film such that the upper surface of the insulating film and the upper surface of the mask layer are flush with each other. According to this configuration, it is possible to suppress the adjacent word lines from being electrically connected.

上記構成において、前記第２溝部を形成する工程は、前記第２溝部の底面が前記半導体基板の上面より上方にあるよう、前記第２溝部を形成する工程である構成とすることができる。この構成によれば、ワードラインと半導体基板とが接触し、電気的に接続することを抑制できる。   In the above configuration, the step of forming the second groove portion may be a step of forming the second groove portion so that the bottom surface of the second groove portion is above the upper surface of the semiconductor substrate. According to this structure, it can suppress that a word line and a semiconductor substrate contact and are electrically connected.

上記構成において、前記第２溝部を形成する工程は、前記電荷蓄積層が露出するよう、前記第２溝部を形成する工程である構成とすることができる。この構成によれば、ゲート絶縁膜を形成する工程において、電荷蓄積層を容易に酸化させることができる。   In the above configuration, the step of forming the second groove may be a step of forming the second groove so that the charge storage layer is exposed. According to this configuration, the charge storage layer can be easily oxidized in the step of forming the gate insulating film.

上記構成において、前記ワードラインと前記絶縁膜とをマスクに、前記半導体基板内に拡散領域を形成する工程を有する構成とすることができる。   In the above structure, a step of forming a diffusion region in the semiconductor substrate using the word line and the insulating film as a mask can be employed.

上記構成において、前記ゲート絶縁膜を形成する工程は、前記マスク層の上面と側面とに酸化膜を形成する工程を含み、前記第１導電層を形成する工程の後、前記第１導電層の側面が露出するよう、前記酸化膜を除去する工程を有する構成とすることができる。この構成によれば、電荷蓄積層とマスク層とが同じ材料からなる場合において、第１導電層と第２導電層とを電気的に接続させることができる。   In the above configuration, the step of forming the gate insulating film includes a step of forming an oxide film on an upper surface and a side surface of the mask layer, and after the step of forming the first conductive layer, the step of forming the first conductive layer. The oxide film may be removed so that the side surface is exposed. According to this configuration, when the charge storage layer and the mask layer are made of the same material, the first conductive layer and the second conductive layer can be electrically connected.

本発明は、第１溝部が延伸して設けられた半導体基板と、前記第１溝部に埋め込まれるように設けられ、前記半導体基板の上面より突出する絶縁膜と、前記半導体基板上に設けられ、前記第１溝部に交差して延伸するワードラインと、前記ワードライン幅方向における中央部下の前記半導体基板上に設けられ、前記絶縁膜により前記ワードライン延伸方向で分離されたゲート絶縁膜と、前記ワードライン幅方向における両端部下の前記半導体基板上に、前記ゲート絶縁膜を挟むように設けられ、前記絶縁膜により前記ワードライン延伸方向で分離された電荷蓄積層と、を具備することを特徴とする半導体装置である。本発明によれば、メモリセル内においてチャネル方向で分離し、且つ隣接するメモリセル間で分離する電荷蓄積層を得ることができる。   The present invention is provided on the semiconductor substrate, a semiconductor substrate provided with the first groove portion extended, an insulating film provided so as to be embedded in the first groove portion, and protruding from an upper surface of the semiconductor substrate, A word line extending across the first groove, a gate insulating film provided on the semiconductor substrate below the center in the word line width direction and separated in the word line extending direction by the insulating film; A charge storage layer provided on the semiconductor substrate below both ends in a word line width direction so as to sandwich the gate insulating film and separated in the word line extending direction by the insulating film. It is a semiconductor device. According to the present invention, it is possible to obtain a charge storage layer that is separated in the channel direction in a memory cell and separated between adjacent memory cells.

上記構成において、前記ワードライン幅方向における中央部であって、前記ゲート絶縁膜上の前記ワードラインの高さと前記絶縁膜上の前記ワードラインの高さとは異なる構成とすることができる。   In the above configuration, the word line may have a central portion in the word line width direction, wherein the height of the word line on the gate insulating film is different from the height of the word line on the insulating film.

上記構成において、前記ワードライン幅方向における前記ゲート絶縁膜両端部上に、前記ワードラインに突出する酸化膜を具備する構成とすることができる。   In the above structure, an oxide film protruding to the word line may be provided on both ends of the gate insulating film in the word line width direction.

本発明によれば、メモリセル内においてチャネル方向で分離し、且つ隣接するメモリセル間で分離する電荷蓄積層を、ワードラインに自己整合的に形成することができる。   According to the present invention, the charge storage layer that is separated in the channel direction in the memory cell and that is separated between adjacent memory cells can be formed on the word line in a self-aligned manner.

以下、図面を参照に本発明の実施例を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は実施例１に係るＮＡＮＤ型フラッシュメモリの斜視図である。図１を参照に、半導体基板１０に延伸するように第１溝部１２が形成されている。第１溝部１２に埋め込まれるように絶縁膜１４が設けられ、絶縁膜１４は半導体基板１０の上面より突出している。絶縁膜１４が埋め込まれた第１溝部１２はＳＴＩ領域として機能する。半導体基板１０上に第１溝部１２に交差して延伸するワードライン１６が形成されている。ワードライン１６はゲート電極を兼ねている。ワードライン１６幅方向における中央部下であって、半導体基板１０上にゲート絶縁膜１８が形成されている。ゲート絶縁膜１８は、絶縁膜１４によりワードライン１６延伸方向で分離されている。ワードライン１６幅方向における両端部下であって、ゲート絶縁膜１８を挟むように、トンネル絶縁膜２０と電荷蓄積層２２とトップ絶縁膜２４とからなる積層膜２５が形成されている。積層膜２５は、絶縁膜１４によりワードライン１６延伸方向で分離されている。第１溝部１２間であって、ワードライン１６幅方向両側の半導体基板１０内に、ソース領域およびドレイン領域である拡散領域２６が形成されている。   FIG. 1 is a perspective view of a NAND flash memory according to the first embodiment. Referring to FIG. 1, a first groove portion 12 is formed so as to extend to the semiconductor substrate 10. An insulating film 14 is provided so as to be embedded in the first groove portion 12, and the insulating film 14 protrudes from the upper surface of the semiconductor substrate 10. The first trench portion 12 in which the insulating film 14 is embedded functions as an STI region. A word line 16 extending across the first groove 12 is formed on the semiconductor substrate 10. The word line 16 also serves as a gate electrode. A gate insulating film 18 is formed on the semiconductor substrate 10 below the center in the width direction of the word line 16. The gate insulating film 18 is separated in the extending direction of the word line 16 by the insulating film 14. A laminated film 25 including a tunnel insulating film 20, a charge storage layer 22, and a top insulating film 24 is formed below both ends in the word line 16 width direction so as to sandwich the gate insulating film 18. The laminated film 25 is separated in the extending direction of the word line 16 by the insulating film 14. Diffusion regions 26 that are a source region and a drain region are formed in the semiconductor substrate 10 between the first groove portions 12 and on both sides of the word line 16 in the width direction.

次に、図２（ａ）から図８（ｃ）を用い、実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を説明する。なお、説明の簡明化のため、１つのメモリセルについて製造方法を説明する。図２（ａ）から図２（ｃ）を参照に、ｐ型シリコン基板である半導体基板１０上に、酸化シリコン膜からなり厚さが５ｎｍ程度のトンネル絶縁膜２０、アモルファスシリコン膜からなり厚さが７ｎｍ程度の電荷蓄積層２２、酸化シリコン膜からなり厚さが１５ｎｍ程度のトップ絶縁膜２４を順次形成する。これにより、半導体基板１０上に積層膜２５が形成される。トンネル絶縁膜２０の形成は熱酸化法を用いることができ、電荷蓄積層２２およびトップ絶縁膜２４の形成はＣＶＤ（化学気相成長）法を用いることができる。   Next, a method for manufacturing the NAND flash memory according to the first embodiment will be described with reference to FIGS. Note that a manufacturing method for one memory cell will be described for simplicity of explanation. 2A to 2C, on the semiconductor substrate 10 which is a p-type silicon substrate, a tunnel insulating film 20 made of a silicon oxide film and having a thickness of about 5 nm, and an amorphous silicon film are formed. Is formed in sequence, a charge storage layer 22 having a thickness of about 7 nm and a top insulating film 24 having a thickness of about 15 nm made of a silicon oxide film. Thereby, the laminated film 25 is formed on the semiconductor substrate 10. The tunnel insulating film 20 can be formed by a thermal oxidation method, and the charge storage layer 22 and the top insulating film 24 can be formed by a CVD (chemical vapor deposition) method.

ＣＶＤ法を用いて、トップ絶縁膜２４上に、延伸する開口部を有するマスク層３０を形成する。マスク層３０は窒化シリコン膜からなり、厚さが１００ｎｍ程度である。マスク層３０をマスクに、ＲＩＥ法を用いて、積層膜２５と半導体基板１０とをエッチングする。これにより、積層膜２５と半導体基板１０とに、延伸する第１溝部１２が形成される。高密度プラズマＣＶＤ法を用いて、第１溝部１２に埋め込まれるように、酸化シリコン膜からなる絶縁膜１４を全面堆積する。その後、マスク層３０の上面が露出するよう、ＣＭＰ（化学機械研磨）法を用いて、絶縁膜１４を除去する。これにより、絶縁膜１４の上面とマスク層３０の上面とは同一面になる。   A mask layer 30 having an opening to be extended is formed on the top insulating film 24 using a CVD method. The mask layer 30 is made of a silicon nitride film and has a thickness of about 100 nm. Using the mask layer 30 as a mask, the laminated film 25 and the semiconductor substrate 10 are etched by RIE. Thereby, the extending first groove portion 12 is formed in the laminated film 25 and the semiconductor substrate 10. An insulating film 14 made of a silicon oxide film is deposited on the entire surface so as to be embedded in the first groove portion 12 by using a high-density plasma CVD method. Thereafter, the insulating film 14 is removed using a CMP (Chemical Mechanical Polishing) method so that the upper surface of the mask layer 30 is exposed. Thereby, the upper surface of the insulating film 14 and the upper surface of the mask layer 30 are flush with each other.

図３（ａ）から図３（ｃ）を参照に、マスク層３０および絶縁膜１４上に、厚さが１００ｎｍ程度のフォトレジスト（不図示）を塗布する。レジストシュリンクプロセスもしくは２重露光プロセスを用いて、フォトレジストに第１溝部１２に交差して延伸する開口部を形成する。開口部の幅は３０ｎｍ程度である。フォトレジストをマスクに、ＲＩＥ法を用いて、マスク層３０とトップ絶縁膜２４と絶縁膜１４とをエッチングする。これにより、マスク層３０とトップ絶縁膜２４と絶縁膜１４とに、第１溝部１２に交差して延伸する第２溝部３２が形成される。   Referring to FIGS. 3A to 3C, a photoresist (not shown) having a thickness of about 100 nm is applied on the mask layer 30 and the insulating film 14. Using a resist shrink process or a double exposure process, an opening that extends across the first groove 12 is formed in the photoresist. The width of the opening is about 30 nm. Using the photoresist as a mask, the mask layer 30, the top insulating film 24, and the insulating film 14 are etched by RIE. As a result, a second groove portion 32 extending across the first groove portion 12 is formed in the mask layer 30, the top insulating film 24, and the insulating film 14.

ここで、マスク層３０は窒化シリコン膜からなり、トップ絶縁膜２４と絶縁膜１４とは酸化シリコン膜からなる。このため、第２溝部３２を形成する工程は、まず、マスク層３０をエッチングし、トップ絶縁膜２４の表面を露出させる。その後、トップ絶縁膜２４と絶縁膜１４とを同時にエッチングする。ここで、絶縁膜１４をより深くエッチングするため、トップ絶縁膜２４が除去されて電荷蓄積層２２の表面が露出した後も、オーバーエッチングを行う。電荷蓄積層２２はアモルファスシリコン膜からなるため、オーバーエッチングを行っても、電荷蓄積層２２はほとんどエッチングされずに済む。なお、オーバーエッチングは、第２溝部３２の底面が半導体基板１０の上面より上方にあるように実施する。言い換えると、第２溝部３２の底面がトンネル絶縁膜２０の底面より上方にあるように実施する。   Here, the mask layer 30 is made of a silicon nitride film, and the top insulating film 24 and the insulating film 14 are made of a silicon oxide film. For this reason, in the step of forming the second groove portion 32, first, the mask layer 30 is etched to expose the surface of the top insulating film 24. Thereafter, the top insulating film 24 and the insulating film 14 are etched simultaneously. Here, in order to etch the insulating film 14 deeper, over etching is performed even after the top insulating film 24 is removed and the surface of the charge storage layer 22 is exposed. Since the charge storage layer 22 is made of an amorphous silicon film, the charge storage layer 22 is hardly etched even when overetching is performed. The overetching is performed so that the bottom surface of the second groove portion 32 is above the top surface of the semiconductor substrate 10. In other words, the process is performed so that the bottom surface of the second groove portion 32 is located above the bottom surface of the tunnel insulating film 20.

図４（ａ）から図４（ｃ）を参照に、第２溝部３２下に形成され、表面が露出した電荷蓄積層２２を、熱酸化法を用いて酸化する。これにより、酸化シリコン膜からなり厚さが２０ｎｍ程度のゲート絶縁膜１８が形成される。   Referring to FIGS. 4A to 4C, the charge storage layer 22 formed under the second groove 32 and exposed on the surface is oxidized using a thermal oxidation method. As a result, a gate insulating film 18 made of a silicon oxide film and having a thickness of about 20 nm is formed.

図５（ａ）から図５（ｃ）を参照に、第２溝部３２に埋め込まれるように、ＣＶＤ法を用いて、アモルファスシリコン膜（もしくはポリシリコン膜）からなる第１導電層３４を全面堆積する。その後、マスク層３０および絶縁膜１４の上面が露出するよう、ＣＭＰ法を用いて、第１導電層３４を除去する。これにより、第１導電層３４下にゲート絶縁膜１８が形成される。   Referring to FIGS. 5A to 5C, the first conductive layer 34 made of an amorphous silicon film (or polysilicon film) is deposited on the entire surface by using the CVD method so as to be embedded in the second groove portion 32. To do. Thereafter, the first conductive layer 34 is removed by CMP so that the upper surfaces of the mask layer 30 and the insulating film 14 are exposed. Thereby, the gate insulating film 18 is formed under the first conductive layer 34.

図６（ａ）から図６（ｃ）を参照に、第１導電層３４およびマスク層３０をマスクに、ＲＩＥ法を用いて、絶縁膜１４をエッチングする。これにより、絶縁膜１４の高さを小さくすることができる。言い換えると、絶縁膜１４がトップ絶縁膜２４の上面より突出する突出量を小さくすることができる。その後、リン酸によるウエットエッチング法を用いて、マスク層３０を除去する。   With reference to FIG. 6A to FIG. 6C, the insulating film 14 is etched using the first conductive layer 34 and the mask layer 30 as a mask, using the RIE method. Thereby, the height of the insulating film 14 can be reduced. In other words, the protruding amount of the insulating film 14 protruding from the upper surface of the top insulating film 24 can be reduced. Thereafter, the mask layer 30 is removed using a wet etching method using phosphoric acid.

図７（ａ）から図７（ｃ）を参照に、第１導電層３４を覆うように、ＣＶＤ法を用いて、アモルファスシリコン膜（もしくはポリシリコン膜）からなり、厚さが２５ｎｍ程度の第２導電層３６を全面堆積する。その後、ＲＩＥ法を用いて、第２導電層３６を全面エッチングする。これにより、第２導電層３６は第１導電層３４幅方向の両側面に残存し、第１導電層３４と第２導電層３６とからなるワードライン１６が形成される。また、第１導電層３４下にはゲート絶縁膜１８が形成されているため、ワードライン１６幅方向における中央部下に、ゲート絶縁膜１８が形成されていることになる。   Referring to FIGS. 7A to 7C, the first conductive layer 34 is covered with an amorphous silicon film (or polysilicon film) using a CVD method so as to cover the first conductive layer 34 and has a thickness of about 25 nm. Two conductive layers 36 are deposited over the entire surface. Thereafter, the entire surface of the second conductive layer 36 is etched using the RIE method. As a result, the second conductive layer 36 remains on both side surfaces of the first conductive layer 34 in the width direction, and the word line 16 composed of the first conductive layer 34 and the second conductive layer 36 is formed. Further, since the gate insulating film 18 is formed under the first conductive layer 34, the gate insulating film 18 is formed under the central portion in the word line 16 width direction.

図８（ａ）から図８（ｃ）を参照に、ワードライン１６をマスクに、ＲＩＥ法を用いて、トップ絶縁膜２４と電荷蓄積層２２とをエッチングにより除去する。これにより、電荷蓄積層２２はワードライン１６幅方向における両端部下に残存する。つまり、電荷蓄積層２２は、ワードライン１６幅方向における両端部下にゲート絶縁膜１８を挟むように形成される。その後、ワードライン１６と絶縁膜１４とをマスクに、半導体基板１０に砒素をイオン注入する。これにより、第１溝部１２間であって、ワードライン１６幅方向両側の半導体基板１０内に、ソース領域およびドレイン領域である拡散領域２６が形成される。   With reference to FIGS. 8A to 8C, the top insulating film 24 and the charge storage layer 22 are removed by etching using the RIE method with the word line 16 as a mask. As a result, the charge storage layer 22 remains below both ends in the width direction of the word line 16. That is, the charge storage layer 22 is formed so as to sandwich the gate insulating film 18 under both end portions in the word line 16 width direction. Thereafter, arsenic is ion-implanted into the semiconductor substrate 10 using the word line 16 and the insulating film 14 as a mask. As a result, diffusion regions 26 that are a source region and a drain region are formed in the semiconductor substrate 10 between the first groove portions 12 and on both sides of the word line 16 in the width direction.

実施例１の製造方法によれば、図２（ａ）から図２（ｃ）のように、トップ絶縁膜２４上に形成された、延伸する開口部を有するマスク層３０をマスクに、積層膜２５と半導体基板１０とをエッチングして、延伸する第１溝部１２を形成する。その後、第１溝部１２に埋め込まれるように絶縁膜１４を形成する。図３（ａ）から図３（ｃ）のように、マスク層３０と絶縁膜１４とに、第１溝部１２に交差して延伸する第２溝部３２を形成する。図４（ａ）から図４（ｃ）のように、第２溝部３２下に形成された電荷蓄積層２２を酸化させてゲート絶縁膜１８を形成する。図５（ａ）から図５（ｃ）のように、第２溝部３２に第１導電層３４を埋め込むように形成し、その後、図６（ａ）から図６（ｃ）のように、マスク層３０を除去する。図７（ａ）から図７（ｃ）のように、第１導電層３４幅方向における両側面に第２導電層３６を形成し、第１導電層３４と第２導電層３６とからなるワードライン１６を形成した後、図８（ａ）から図８（ｃ）のように、ワードライン１６をマスクに、トップ絶縁膜２４と電荷蓄積層２２とをエッチングにより除去する。   According to the manufacturing method of the first embodiment, as shown in FIGS. 2A to 2C, the laminated film is formed using the mask layer 30 formed on the top insulating film 24 and having an extending opening as a mask. 25 and the semiconductor substrate 10 are etched to form a first groove 12 that extends. Thereafter, an insulating film 14 is formed so as to be embedded in the first groove portion 12. As shown in FIG. 3A to FIG. 3C, a second groove portion 32 that extends across the first groove portion 12 is formed in the mask layer 30 and the insulating film 14. As shown in FIGS. 4A to 4C, the gate insulating film 18 is formed by oxidizing the charge storage layer 22 formed under the second groove portion 32. As shown in FIGS. 5A to 5C, the first conductive layer 34 is formed so as to be embedded in the second groove 32, and then the mask is formed as shown in FIGS. 6A to 6C. Layer 30 is removed. As shown in FIG. 7A to FIG. 7C, the second conductive layer 36 is formed on both side surfaces in the width direction of the first conductive layer 34, and the word composed of the first conductive layer 34 and the second conductive layer 36. After the line 16 is formed, as shown in FIGS. 8A to 8C, the top insulating film 24 and the charge storage layer 22 are removed by etching using the word line 16 as a mask.

このような製造方法により、図１のように、半導体基板１０に延伸するように第１溝部１２が設けられ、第１溝部１２に埋め込まれるように形成された絶縁膜１４は、半導体基板１０の表面より突出する。また、ワードライン１６幅方向における両端部下に、絶縁膜１４により、ワードライン１６延伸方向で分離された電荷蓄積層２２が形成される。つまり、電荷蓄積層２２は、ワードライン１６延伸方向で隣接するメモリセル間で分離し、且つ、ワードライン１６幅方向で隣接するメモリセル間でも分離する。さらに、ワードライン１６幅方向における中央部下に、絶縁膜１４によりワードライン１６延伸方向で分離されたゲート絶縁膜１８が形成され、電荷蓄積層２２はゲート絶縁膜１８を挟むように形成される。つまり、メモリセル内において、電荷蓄積層２２はチャネル方向で分離している。   With such a manufacturing method, as shown in FIG. 1, the first groove portion 12 is provided so as to extend to the semiconductor substrate 10, and the insulating film 14 formed to be embedded in the first groove portion 12 is formed on the semiconductor substrate 10. It protrudes from the surface. Further, the charge storage layer 22 separated in the extending direction of the word line 16 is formed by the insulating film 14 below both ends in the width direction of the word line 16. That is, the charge storage layer 22 is separated between adjacent memory cells in the extending direction of the word line 16 and also separated between adjacent memory cells in the width direction of the word line 16. Further, a gate insulating film 18 separated in the extending direction of the word line 16 by the insulating film 14 is formed below the center in the width direction of the word line 16, and the charge storage layer 22 is formed so as to sandwich the gate insulating film 18. That is, in the memory cell, the charge storage layer 22 is separated in the channel direction.

このように、実施例１によれば、電荷蓄積層２２は、メモリセル内においてチャネル方向で分離して形成される。このため、電荷蓄積層２２にアモルファスシリコン膜等の導電膜を用いた場合でも、１つのメモリセル内に２つの電荷蓄積領域を形成することができ、１メモリセルに２ビットのデータを記憶させることができる。特に、電荷蓄積層２２に導電膜を用いた場合は、絶縁膜を用いた場合に比べて、蓄積可能な電荷量を増大させることができる。また、例えば、電荷蓄積層２２に窒化シリコン膜等の絶縁膜を用いた場合は、メモリセル内において電荷蓄積層２２がチャネル方向で分離されていなくても、２つの電荷蓄積領域を形成することができる。しかしながら、電荷蓄積層２２がチャネル方向で分離している場合は、ＣＢＤと呼ばれる、２つの電荷蓄積領域に蓄積された電荷が互いに干渉する影響を抑制することができる。これにより、２つの電荷蓄積領域に蓄積された電荷の切り分けがより確実に行え、良好な特性を得ることができる。このため、電荷蓄積層２２に絶縁膜を用いた場合でも、メモリセル内において電荷蓄積層２２はチャネル方向で分離している場合が好ましい。特に、メモリセルの微細化が進み、チャネル長が短くなった場合に、このＣＢＤを抑制する効果は大きくなる。   Thus, according to the first embodiment, the charge storage layer 22 is formed separately in the channel direction in the memory cell. Therefore, even when a conductive film such as an amorphous silicon film is used for the charge storage layer 22, two charge storage regions can be formed in one memory cell, and 2-bit data is stored in one memory cell. be able to. In particular, when a conductive film is used for the charge storage layer 22, the amount of charge that can be stored can be increased as compared with the case where an insulating film is used. For example, when an insulating film such as a silicon nitride film is used for the charge storage layer 22, two charge storage regions are formed even if the charge storage layer 22 is not separated in the channel direction in the memory cell. Can do. However, when the charge storage layer 22 is separated in the channel direction, it is possible to suppress the influence of interference accumulated in two charge storage regions called CBD. Thereby, the charge accumulated in the two charge accumulation regions can be more surely separated, and good characteristics can be obtained. Therefore, even when an insulating film is used for the charge storage layer 22, it is preferable that the charge storage layer 22 is separated in the channel direction in the memory cell. In particular, when the memory cell is miniaturized and the channel length is shortened, the effect of suppressing the CBD is increased.

また、実施例１によれば、電荷蓄積層２２は隣接するメモリセル間で分離されている。例えば、電荷蓄積層２２が隣接するメモリセル間で繋がっている場合は、電荷蓄積層２２に導電膜を用いると、電荷蓄積層２２に蓄積された電荷が隣接するメモリセル間を移動し、隣接するメモリセルの閾値電圧に影響を及ぼす場合がある。また、例えば、電荷蓄積層２２に絶縁膜を用いた場合でも、メモリセルの微細化が進み、隣接するメモリセルの間隔が狭くなると、隣接するメモリセルの閾値電圧に影響を及ぼす場合がある。しかしながら、実施例１によれば、隣接するメモリセル間で電荷蓄積層２２は分離されている。このため、電荷蓄積層２２に導電膜を用いた場合でも、絶縁膜を用いた場合でも、隣接するメモリセルの閾値電圧に与える影響を抑制することができる。このように、実施例１によれば、メモリセル内において電荷蓄積層２２がチャネル方向で分離し、且つ隣接するメモリセル間でも分離していることで、電荷蓄積層２２に用いることができる材料の選択肢を広げることができる。   Further, according to the first embodiment, the charge storage layer 22 is separated between adjacent memory cells. For example, when the charge storage layer 22 is connected between adjacent memory cells, if a conductive film is used for the charge storage layer 22, the charge stored in the charge storage layer 22 moves between the adjacent memory cells. May affect the threshold voltage of the memory cell. For example, even when an insulating film is used for the charge storage layer 22, if the memory cell is further miniaturized and the interval between adjacent memory cells is narrowed, the threshold voltage of the adjacent memory cell may be affected. However, according to the first embodiment, the charge storage layer 22 is separated between adjacent memory cells. For this reason, whether the conductive film is used for the charge storage layer 22 or the insulating film is used, the influence on the threshold voltage of the adjacent memory cell can be suppressed. As described above, according to the first embodiment, the charge storage layer 22 in the memory cell is separated in the channel direction and also between adjacent memory cells, so that the material that can be used for the charge storage layer 22 is used. You can expand your options.

さらに、図８（ａ）から図８（ｃ）のように、ワードライン１６をマスクに電荷蓄積層２２をエッチングして除去し、ワードライン１６幅方向における両端部下に電荷蓄積層２２を形成する。これにより、電荷蓄積層２２とワードライン１６とは自己整合的に形成することができる。また、図７（ａ）から図７（ｃ）のように、ワードライン１６は、第１導電層３４と第１導電層３４幅方向における両側面に形成された第２導電層３６とからなる。第１導電層３４下にはゲート絶縁膜１８が形成され、第２導電層３６下には電荷蓄積層２２が形成される。これにより、第２導電層３６の膜厚を制御することで、電荷蓄積層２２の大きさを制御することが可能となる。   Further, as shown in FIG. 8A to FIG. 8C, the charge storage layer 22 is removed by etching using the word line 16 as a mask, and the charge storage layer 22 is formed under both ends in the width direction of the word line 16. . As a result, the charge storage layer 22 and the word line 16 can be formed in a self-aligning manner. Further, as shown in FIGS. 7A to 7C, the word line 16 includes a first conductive layer 34 and second conductive layers 36 formed on both side surfaces in the width direction of the first conductive layer 34. . The gate insulating film 18 is formed under the first conductive layer 34, and the charge storage layer 22 is formed under the second conductive layer 36. Thus, the size of the charge storage layer 22 can be controlled by controlling the film thickness of the second conductive layer 36.

さらに、図１のように、電荷蓄積層２２は、ワードライン１６両端部下に形成されている。このため、例えば、ゲート電極の側面に電荷蓄積層が形成されている場合に比べ、ワードライン１６からの電界を意図したようにかけることができ、より効率よく電荷蓄積層２２に電荷を蓄積させることができる。   Further, as shown in FIG. 1, the charge storage layer 22 is formed below both ends of the word line 16. Therefore, for example, compared with the case where the charge storage layer is formed on the side surface of the gate electrode, the electric field from the word line 16 can be applied as intended, and charges are stored in the charge storage layer 22 more efficiently. be able to.

さらに、図６（ａ）から図６（ｃ）のように、第２溝部３２に第１導電層３４を埋め込んで形成した後、第１導電層３４とマスク層３０とをマスクに、絶縁膜１４をエッチングする。これにより、絶縁膜１４がトップ絶縁膜２４より突出する突出量を小さくすることができる。このため、図７（ａ）から図７（ｃ）のように、第１導電層３４を覆うように第２導電層３６を全面堆積した際、絶縁膜１４の側面に形成される第２導電層３６の高さを低くすることができる。よって、その後の、第２導電層３６を全面エッチングする工程で、絶縁膜１４の側面に形成された第２導電層３６は除去され易くなり、絶縁膜１４の側面に第２導電層３６が残存することを抑制できる。例えば、絶縁膜１４の側面に第２導電層３６が残存した場合は、隣接するワードライン１６同士が電気的に接続してしまう。よって、実施例１の製造方法によれば、隣接するワードライン１６同士が電気的に接続することを抑制することができる。   Further, as shown in FIGS. 6A to 6C, after the first conductive layer 34 is formed in the second groove 32, the insulating film is formed using the first conductive layer 34 and the mask layer 30 as a mask. 14 is etched. Thereby, the protrusion amount by which the insulating film 14 protrudes from the top insulating film 24 can be reduced. For this reason, as shown in FIGS. 7A to 7C, when the second conductive layer 36 is deposited over the entire surface so as to cover the first conductive layer 34, the second conductivity formed on the side surface of the insulating film 14. The height of the layer 36 can be reduced. Therefore, in the subsequent step of etching the entire surface of the second conductive layer 36, the second conductive layer 36 formed on the side surface of the insulating film 14 is easily removed, and the second conductive layer 36 remains on the side surface of the insulating film 14. Can be suppressed. For example, when the second conductive layer 36 remains on the side surface of the insulating film 14, the adjacent word lines 16 are electrically connected. Therefore, according to the manufacturing method of Example 1, it can suppress that the adjacent word lines 16 are electrically connected.

さらに、図２（ａ）から図２（ｃ）のように、絶縁膜１４は、絶縁膜１４の上面とマスク層３０の上面とが同一面になるように形成する。例えば、絶縁膜１４の上面がマスク層３０の上面より下方にある場合は、図５（ａ）から図５（ｃ）に示す、第２溝部３２に埋め込まれるように第１導電層３４を形成する工程において、第１導電層３４が絶縁膜１４上に第１溝部１２延伸方向に延伸して形成される場合が生じる。この場合は、隣接する第１導電層３４同士が電気的に接続してしまう。つまり、隣接するワードライン１６同士が電気的に接続してしまう。しかしながら、実施例１の製造方法によれば、絶縁膜１４の上面とマスク層３０の上面とが同一面になるよう形成するため、第１導電層３４が絶縁膜１４上に第１溝部１２延伸方向に延伸して形成されることを抑制できる。よって、隣接するワードライン１６同士が電気的に接続することを抑制できる。   Further, as shown in FIGS. 2A to 2C, the insulating film 14 is formed so that the upper surface of the insulating film 14 and the upper surface of the mask layer 30 are flush with each other. For example, when the upper surface of the insulating film 14 is below the upper surface of the mask layer 30, the first conductive layer 34 is formed so as to be embedded in the second groove portion 32 shown in FIGS. 5 (a) to 5 (c). In this step, the first conductive layer 34 may be formed on the insulating film 14 by extending in the extending direction of the first groove 12. In this case, the adjacent first conductive layers 34 are electrically connected to each other. That is, adjacent word lines 16 are electrically connected. However, according to the manufacturing method of the first embodiment, since the upper surface of the insulating film 14 and the upper surface of the mask layer 30 are formed to be flush with each other, the first conductive layer 34 extends on the insulating film 14 in the first groove portion 12. It can suppress forming by extending | stretching to a direction. Therefore, it can suppress that the adjacent word lines 16 are electrically connected.

さらに、図３（ａ）から図３（ｃ）のように、第２溝部３２は、第２溝部３２の底面が半導体基板１０の上面より上方にあるように形成する。これにより、図５（ａ）から図５（ｃ）のように、第２溝部３２に第１導電層３４を埋め込んで形成する場合に、第１導電層３４が半導体基板１０に接触することを抑制できる。つまり、ワードライン１６が半導体基板１０に接触し、ワードライン１６と半導体基板１０とが電気的に接続することを抑制できる。また、図３（ａ）から図３（ｃ）のように、第２溝部３２は電荷蓄積層２２の表面が露出するように形成する。これにより、図４（ａ）から図４（ｃ）に示す、ゲート絶縁膜１８を形成する工程において、電荷蓄積層２２を容易に酸化させることができる。   Further, as shown in FIG. 3A to FIG. 3C, the second groove portion 32 is formed so that the bottom surface of the second groove portion 32 is above the upper surface of the semiconductor substrate 10. Accordingly, as shown in FIGS. 5A to 5C, when the first conductive layer 34 is embedded in the second groove 32, the first conductive layer 34 is in contact with the semiconductor substrate 10. Can be suppressed. That is, it is possible to suppress the word line 16 from contacting the semiconductor substrate 10 and electrically connecting the word line 16 and the semiconductor substrate 10. Further, as shown in FIGS. 3A to 3C, the second groove portion 32 is formed so that the surface of the charge storage layer 22 is exposed. Thereby, the charge storage layer 22 can be easily oxidized in the step of forming the gate insulating film 18 shown in FIGS. 4A to 4C.

さらに、上記製造方法で製造された実施例１に係るＮＡＮＤ型フラッシュメモリにおいては、ワードライン１６幅方向における中央部であって、ゲート絶縁膜１８上のワードライン１６の高さと絶縁膜１４上のワードライン１６の高さとは異なるように形成される。また、絶縁膜１４上であって、ワードライン１６幅方向中央部のワードライン１６の高さと、ワードライン１６幅方向両端部のワードライン１６の高さとは異なるように形成される。   Furthermore, in the NAND flash memory according to the first embodiment manufactured by the above manufacturing method, the height of the word line 16 on the gate insulating film 18 and the height of the word line 16 in the center in the width direction of the word line 16. It is formed different from the height of the word line 16. Further, the height of the word line 16 at the center in the width direction of the word line 16 on the insulating film 14 is different from the height of the word line 16 at both ends in the width direction of the word line 16.

実施例２に係るＮＡＮＤ型フラッシュメモリは、電荷蓄積層２２とマスク層３０とが同じ材料からなる場合の例である。図９（ａ）から図１０（ｂ）を用い、実施例２に係るフラッシュメモリの製造方法を説明する。なお、図９（ａ）から図１０（ｂ）は、図２のＢ−Ｂ間に相当する箇所の断面図である。   The NAND flash memory according to the second embodiment is an example in which the charge storage layer 22 and the mask layer 30 are made of the same material. A method for manufacturing the flash memory according to the second embodiment will be described with reference to FIGS. 9A to 10B. FIG. 9A to FIG. 10B are cross-sectional views of a portion corresponding to BB in FIG.

まず、図２（ａ）から図３（ｃ）で説明した工程を実施する。ただし、電荷蓄積層２２は窒化シリコン膜を用いる。図９（ａ）を参照に、第２溝部３２下に形成された電荷蓄積層２２を、ラジカル酸化法もしくはプラズマ酸化法を用いて酸化させて、ゲート絶縁膜１８を形成する。電荷蓄積層２２とマスク層３０とは共に窒化シリコン膜であり、同じ材料であるため、マスク層３０の上面および側面も酸化されて酸化膜３８が形成される。   First, the steps described in FIGS. 2A to 3C are performed. However, the charge storage layer 22 uses a silicon nitride film. Referring to FIG. 9A, the charge storage layer 22 formed under the second trench 32 is oxidized using a radical oxidation method or a plasma oxidation method to form the gate insulating film 18. Since both the charge storage layer 22 and the mask layer 30 are silicon nitride films and are made of the same material, the upper surface and side surfaces of the mask layer 30 are also oxidized to form an oxide film 38.

図９（ｂ）を参照に、第２溝部３２に埋め込まれるように第１導電層３４を形成する。図９（ｃ）を参照に、ＲＩＥ法もしくはフッ酸によるウエットエッチング法を用いて、第１導電層３４の側面が露出するよう、酸化膜３８を除去する。   With reference to FIG. 9B, the first conductive layer 34 is formed so as to be embedded in the second groove portion 32. Referring to FIG. 9C, the oxide film 38 is removed using the RIE method or the wet etching method using hydrofluoric acid so that the side surface of the first conductive layer 34 is exposed.

図１０（ａ）を参照に、マスク層３０を除去した後、第１導電層３４幅方向における両側面に第２導電層３６を形成し、第１導電層３４と第２導電層３６とからなるワードライン１６を形成する。図１０（ｂ）を参照に、ワードライン１６をマスクに、トップ絶縁膜２４と電荷蓄積層２２とをエッチングにより除去する。その後、第１溝部１２間であって、ワードライン１６幅方向両側の半導体基板１０にソース領域およびドレイン領域である拡散領域２６を形成する。   Referring to FIG. 10A, after removing mask layer 30, second conductive layer 36 is formed on both side surfaces in the width direction of first conductive layer 34, and first conductive layer 34 and second conductive layer 36 are separated from each other. The word line 16 is formed. Referring to FIG. 10B, the top insulating film 24 and the charge storage layer 22 are removed by etching using the word line 16 as a mask. Thereafter, a diffusion region 26 as a source region and a drain region is formed in the semiconductor substrate 10 between the first groove portions 12 and on both sides of the word line 16 in the width direction.

実施例２の製造方法によれば、電荷蓄積層２２とマスク層３０とが同じ材料からなるため、図９（ａ）のように、電荷蓄積層２２を酸化させてゲート絶縁膜１８を形成する工程を実施すると、マスク層３０の上面と側面とに酸化膜３８が形成される。図９（ｃ）のように、第２溝部３２に第１導電層３４を形成した後、第１導電層３４の側面が露出するよう酸化膜３８を除去する。これにより、図１０（ａ）に示すように、第１導電層３４と第１導電層３４の両側面に形成された第２導電層３６とを電気的に接続させることができる。なお、第１導電層３４と第２導電層３６との電気的な接続の観点から、図９（ｃ）に示す酸化膜３８を除去する工程は、第１導電層３４の側面が半分以上露出するように酸化膜３８を除去することが好ましい。   According to the manufacturing method of the second embodiment, since the charge storage layer 22 and the mask layer 30 are made of the same material, the charge storage layer 22 is oxidized to form the gate insulating film 18 as shown in FIG. When the process is performed, an oxide film 38 is formed on the upper surface and the side surface of the mask layer 30. As shown in FIG. 9C, after forming the first conductive layer 34 in the second groove 32, the oxide film 38 is removed so that the side surface of the first conductive layer 34 is exposed. Accordingly, as shown in FIG. 10A, the first conductive layer 34 and the second conductive layer 36 formed on both side surfaces of the first conductive layer 34 can be electrically connected. Note that, from the viewpoint of electrical connection between the first conductive layer 34 and the second conductive layer 36, in the step of removing the oxide film 38 shown in FIG. 9C, more than half of the side surface of the first conductive layer 34 is exposed. Thus, it is preferable to remove the oxide film 38.

また、上記製造方法で製造された実施例２に係るＮＡＮＤ型フラッシュメモリにおいては、第１導電層３４と第２導電層３６との間に酸化膜３８が形成される。言い換えると、ワードライン１６幅方向におけるゲート絶縁膜１８両端部上に、ワードライン１６に突出する酸化膜３８が形成される。   In the NAND flash memory according to the second embodiment manufactured by the above manufacturing method, the oxide film 38 is formed between the first conductive layer 34 and the second conductive layer 36. In other words, the oxide film 38 protruding to the word line 16 is formed on both ends of the gate insulating film 18 in the width direction of the word line 16.

以上、本発明の好ましい実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

図１は実施例１に係るＮＡＮＤ型フラッシュメモリの斜視図である。FIG. 1 is a perspective view of a NAND flash memory according to the first embodiment. 図２（ａ）は実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を示す斜視図（その１）であり、図２（ｂ）および図２（ｃ）は図２（ａ）のＢ−Ｂ間およびＣ−Ｃ間の断面図である。FIG. 2A is a perspective view (No. 1) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 2B and 2C are cross-sectional views taken along line BB in FIG. It is sectional drawing between C and C-C. 図３（ａ）は実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を示す斜視図（その２）であり、図３（ｂ）および図３（ｃ）は図３（ａ）のＢ−Ｂ間およびＣ−Ｃ間の断面図である。FIG. 3A is a perspective view (No. 2) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 3B and 3C are cross-sectional views taken along line BB in FIG. It is sectional drawing between C and C-C. 図４（ａ）は実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を示す斜視図（その３）であり、図４（ｂ）および図４（ｃ）は図４（ａ）のＢ−Ｂ間およびＣ−Ｃ間の断面図である。4A is a perspective view (No. 3) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 4B and 4C are cross-sectional views taken along line BB in FIG. It is sectional drawing between C and C-C. 図５（ａ）は実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を示す斜視図（その４）であり、図５（ｂ）および図５（ｃ）は図５（ａ）のＢ−Ｂ間およびＣ−Ｃ間の断面図である。FIG. 5A is a perspective view (No. 4) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 5B and 5C are cross-sectional views taken along line BB in FIG. It is sectional drawing between C and C-C. 図６（ａ）は実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を示す斜視図（その５）であり、図６（ｂ）および図６（ｃ）は図６（ａ）のＢ−Ｂ間およびＣ−Ｃ間の断面図である。FIG. 6A is a perspective view (No. 5) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 6B and 6C are cross-sectional views taken along line BB in FIG. It is sectional drawing between C and C-C. 図７（ａ）は実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を示す斜視図（その６）であり、図７（ｂ）および図７（ｃ）は図７（ａ）のＢ−Ｂ間およびＣ−Ｃ間の断面図である。FIG. 7A is a perspective view (No. 6) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 7B and 7C are cross-sectional views taken along line BB in FIG. It is sectional drawing between C and C-C. 図８（ａ）は実施例１に係るＮＡＮＤ型フラッシュメモリの製造方法を示す斜視図（その７）であり、図８（ｂ）および図８（ｃ）は図８（ａ）のＢ−Ｂ間およびＣ−Ｃ間の断面図である。FIG. 8A is a perspective view (No. 7) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 8B and 8C are cross-sectional views taken along line BB in FIG. It is sectional drawing between C and C-C. 図９（ａ）から図９（ｃ）は実施例２に係るＮＡＮＤ型フラッシュメモリの製造方法を示す、図２のＢ−Ｂ間に相当する箇所の断面図（その１）である。FIG. 9A to FIG. 9C are cross-sectional views (No. 1) of a portion corresponding to the line BB in FIG. 図１０（ａ）および図１０（ｂ）は実施例２に係るＮＡＮＤ型フラッシュメモリの製造方法を示す、図２のＢ−Ｂ間に相当する箇所の断面図（その２）である。FIG. 10A and FIG. 10B are cross-sectional views (No. 2) of a portion corresponding to the line B-B in FIG.

符号の説明Explanation of symbols

１０ 半導体基板
１２ 第１溝部
１４ 絶縁膜
１６ ワードライン
１８ ゲート絶縁膜
２０ トンネル絶縁膜
２２ 電荷蓄積層
２４ トップ絶縁膜
２５ 積層膜
２６ 拡散領域
３０ マスク層
３２ 第２溝部
３４ 第１導電層
３６ 第２導電層
３８ 酸化膜 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 1st groove part 14 Insulating film 16 Word line 18 Gate insulating film 20 Tunnel insulating film 22 Charge storage layer 24 Top insulating film 25 Laminated film 26 Diffusion area 30 Mask layer 32 2nd groove part 34 1st conductive layer 36 2nd Conductive layer 38 Oxide film

Claims (7)

半導体基板上に電荷蓄積層を形成する工程と、
前記電荷蓄積層上に形成されたマスク層をマスクにして、前記電荷蓄積層と前記半導体基板とに、延伸する第１溝部を形成する工程と、
前記第１溝部に埋め込むように絶縁膜を形成する工程と、
前記マスク層と前記絶縁膜とに、前記第１溝部に交差して延伸する第２溝部を形成する工程と、
前記第２溝部下に形成された前記電荷蓄積層を酸化させてゲート絶縁膜を形成する工程と、
前記第２溝部に埋め込むように第１導電層を形成する工程と、
前記マスク層を除去する工程と、
前記第１導電層幅方向における両側面に第２導電層を形成し、前記第１導電層と前記第２導電層とからなるワードラインを形成する工程と、
前記ワードラインをマスクに前記電荷蓄積層を除去する工程と、を有することを特徴とする半導体装置の製造方法。 Forming a charge storage layer on a semiconductor substrate;
Forming a first groove extending in the charge storage layer and the semiconductor substrate using the mask layer formed on the charge storage layer as a mask;
Forming an insulating film so as to be embedded in the first groove,
Forming a second groove portion extending across the first groove portion in the mask layer and the insulating film; and
Oxidizing the charge storage layer formed under the second groove to form a gate insulating film;
Forming a first conductive layer so as to be embedded in the second groove,
Removing the mask layer;
Forming a second conductive layer on both side surfaces in the width direction of the first conductive layer, and forming a word line composed of the first conductive layer and the second conductive layer;
And a step of removing the charge storage layer using the word line as a mask. 前記第１導電層を形成する工程の後、前記第１導電層と前記マスク層とをマスクに、前記絶縁膜をエッチングする工程を有することを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching the insulating film using the first conductive layer and the mask layer as a mask after the step of forming the first conductive layer. . 前記絶縁膜を形成する工程は、前記絶縁膜の上面と前記マスク層の上面とが同一面になるよう、前記絶縁膜を形成する工程であることを特徴とする請求項１または２記載の半導体装置の製造方法。   3. The semiconductor according to claim 1, wherein the step of forming the insulating film is a step of forming the insulating film such that an upper surface of the insulating film and an upper surface of the mask layer are flush with each other. Device manufacturing method. 前記第２溝部を形成する工程は、前記第２溝部の底面が前記半導体基板の上面より上方にあるよう、前記第２溝部を形成する工程であることを特徴とする請求項１から３のいずれか一項記載の半導体装置の製造方法。   The step of forming the second groove portion is a step of forming the second groove portion so that the bottom surface of the second groove portion is above the upper surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 1. 前記第２溝部を形成する工程は、前記電荷蓄積層が露出するよう、前記第２溝部を形成する工程であることを特徴とする請求項１から４のいずれか一項記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the second groove is a step of forming the second groove so that the charge storage layer is exposed. Method. 前記ゲート絶縁膜を形成する工程は、前記マスク層の上面と側面とに酸化膜を形成する工程を含み、
前記第１導電層を形成する工程の後、前記第１導電層の側面が露出するよう、前記酸化膜を除去する工程を有することを特徴とする請求項１から５のいずれか一項記載の半導体装置の製造方法。 The step of forming the gate insulating film includes a step of forming an oxide film on an upper surface and a side surface of the mask layer,
6. The method according to claim 1, further comprising a step of removing the oxide film so that a side surface of the first conductive layer is exposed after the step of forming the first conductive layer. A method for manufacturing a semiconductor device. 前記ワードラインと前記絶縁膜とをマスクに、前記半導体基板内に拡散領域を形成する工程を有することを特徴とする請求項１から６のいずれか一項記載の半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a diffusion region in the semiconductor substrate using the word line and the insulating film as a mask.
JP2007308094A 2007-11-28 2007-11-28 Semiconductor device and manufacturing method thereof Active JP5491694B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007308094A JP5491694B2 (en) 2007-11-28 2007-11-28 Semiconductor device and manufacturing method thereof
PCT/US2008/013227 WO2009070336A1 (en) 2007-11-28 2008-11-26 Semiconductor device and method for manufacturing thereof
TW97146131A TWI471936B (en) 2007-11-28 2008-11-28 Semiconductor device and method for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007308094A JP5491694B2 (en) 2007-11-28 2007-11-28 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2009135155A JP2009135155A (en) 2009-06-18
JP5491694B2 true JP5491694B2 (en) 2014-05-14

Family

ID=40289231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007308094A Active JP5491694B2 (en) 2007-11-28 2007-11-28 Semiconductor device and manufacturing method thereof

Country Status (3)

Country Link
JP (1) JP5491694B2 (en)
TW (1) TWI471936B (en)
WO (1) WO2009070336A1 (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3233998B2 (en) * 1992-08-28 2001-12-04 株式会社東芝 Manufacturing method of nonvolatile semiconductor memory device
JP4834897B2 (en) * 2000-05-02 2011-12-14 ソニー株式会社 Nonvolatile semiconductor memory device and operation method thereof
JP2003163292A (en) * 2001-08-13 2003-06-06 Halo Lsi Inc Twin nand device structure, its array operation and its fabricating method
JP2003258128A (en) * 2002-02-27 2003-09-12 Nec Electronics Corp Non-volatile semiconductor memory device, manufacturing method and operating method of the same
JP3983094B2 (en) * 2002-04-25 2007-09-26 Ｎｅｃエレクトロニクス株式会社 Method for manufacturing nonvolatile semiconductor memory device
KR100480645B1 (en) * 2003-04-01 2005-03-31 삼성전자주식회사 Method for manufacturing SONOS memory device with twin-ONO by reverse self-aligning process
JP4041076B2 (en) * 2004-02-27 2008-01-30 株式会社東芝 Data storage system
KR100655291B1 (en) * 2005-03-14 2006-12-08 삼성전자주식회사 Non-volatile semiconductor memory device and method of fabrication the same

Also Published As

Publication number Publication date
TW200937524A (en) 2009-09-01
TWI471936B (en) 2015-02-01
WO2009070336A1 (en) 2009-06-04
JP2009135155A (en) 2009-06-18

Similar Documents

Publication Publication Date Title
KR100660543B1 (en) Nand falsh memory device and method of fabricating the same
JP4250616B2 (en) Semiconductor integrated circuit device and manufacturing method thereof
US20170256556A1 (en) Nonvolatile memory device and method for fabricating the same
JP2011066052A (en) Semiconductor device manufacturing method, and the semiconductor device
US8669606B2 (en) Semiconductor device and method for manufacturing thereof
JP5319092B2 (en) Semiconductor device and manufacturing method thereof
JP2009049208A (en) Semiconductor device and method for manufacturing the same
JP5319107B2 (en) Semiconductor device and manufacturing method thereof
JP5491694B2 (en) Semiconductor device and manufacturing method thereof
JP5264139B2 (en) Manufacturing method of semiconductor device
JP5308024B2 (en) Semiconductor device and manufacturing method thereof
JP5789654B2 (en) Semiconductor device and manufacturing method thereof
JP5367256B2 (en) Semiconductor device and manufacturing method thereof
JP5395344B2 (en) Semiconductor device
JP4284311B2 (en) Manufacturing method of semiconductor memory device
JP5566013B2 (en) Semiconductor device and manufacturing method thereof
JP5405066B2 (en) Manufacturing method of semiconductor device
JP5313486B2 (en) Manufacturing method of semiconductor device
JP5363004B2 (en) Manufacturing method of semiconductor device
JP5681761B2 (en) Manufacturing method of semiconductor device
JP5792759B2 (en) Memory system having a switch element
JP5290592B2 (en) Semiconductor device and manufacturing method thereof
JP2016006894A (en) Semiconductor device and manufacturing method of the same
JP2008112898A (en) Nonvolatile semiconductor memory, and manufacturing method thereof
KR20080100968A (en) Non-volatile memory device and manufacturing method thereof

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20100329

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20100402

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100616

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101126

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101202

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20120830

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130214

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130418

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131015

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140114

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140117

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140120

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140205

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140228

R150 Certificate of patent or registration of utility model

Ref document number: 5491694

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250