TW200937524A - Semiconductor device and method for manufacturing thereof - Google Patents

Semiconductor device and method for manufacturing thereof Download PDF

Info

Publication number
TW200937524A
TW200937524A TW097146131A TW97146131A TW200937524A TW 200937524 A TW200937524 A TW 200937524A TW 097146131 A TW097146131 A TW 097146131A TW 97146131 A TW97146131 A TW 97146131A TW 200937524 A TW200937524 A TW 200937524A
Authority
TW
Taiwan
Prior art keywords
insulating film
layer
word line
charge storage
mask
Prior art date
Application number
TW097146131A
Other languages
Chinese (zh)
Other versions
TWI471936B (en
Inventor
Famihiko Inoue
Takayuki Maruyama
Masayuki Sato
Original Assignee
Spansion Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc filed Critical Spansion Llc
Publication of TW200937524A publication Critical patent/TW200937524A/en
Application granted granted Critical
Publication of TWI471936B publication Critical patent/TWI471936B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The method for manufacturing the semiconductor device, which includes the steps of forming a charge storage layer 22 on a semiconductor substrate 10, forming an extending first groove 12 in the charge storage layer and the semiconductor substrate using a mask layer 30 formed on the charge storage layer as a mask, forming an insulating film 14 in the first groove, forming a second groove 32 extending across the first groove in the mask layer and the insulating film, forming a gate insulating film 18 formed below the second groove, forming a first conductive layer 34 in the second groove, eliminating the mask layer, forming a second conductive layer 36 on both side surfaces of the first conductive layer to form a word line 16 which includes the first and the second conductive layers, and eliminating the charge storage layer using the word line as a mask.

Description

200937524 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體裝置，其具有分隔的電荷儲 存層。 【先前技術】 非揮發性的記憶體是已經被廣泛使用的半導體裝 置’其中的資料不但可以重複寫入，即使切掉電源也還能 保有儲藏的資料。在一種典型非揮發性記憶體的快閃記憶 ❹ 體（Dash memory )中，組構記憶體單元（ memory cell) 的電晶體係包括所謂的電荷儲存層（charge st〇rage layer )， 不是由浮置閘（floating gate)便是由絕緣薄膜所構成。電 荷會積聚在用來儲存資料的電荷儲存層内。 近來有各式各樣的方法被提出，用來增加於單一記憶 體單兀中所能儲存的資料容量。舉例來說，在虛接地 (virtual ground)式的快閃記憶體中，區域會在源極區域 〇 以及汲極區域之間切換，用來在單一記憶體單元的電荷儲 存層中形成兩個電荷儲存區域。這使得在單一記憶體單元 中有可能儲存2個位元的資料。 曰本未經審查的專利申請案公開號No. 2002-313967 揭露了種决閃5己憶體’其具有以STI ( shallow trench isolation，淺溝槽隔離）區域來分隔的電荷儲存層。例如， 使用以氮化物薄膜製成的遮罩層製作用來分隔電荷儲存層 之sti區域的技術，係揭露於2〇〇7年非揮發性半導體記憶 體研 of^Non-volatile Semiconductor Memory Workshop)， 3 94576 200937524 第110至111頁。 於使用絕緣薄膜作為電荷儲存層的虛接地式快問記 憶體中，如果其電荷儲存層沒有在記憶體單元中之通道（通 道）方向被分隔’那麼分別儲存在兩電荷儲存區域中的電 荷便會彼此互相干擾，也就是所謂的CBD (CGmplementary200937524 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device having a divided charge storage layer. [Prior Art] A non-volatile memory is a semiconductor device that has been widely used. The data therein can be repeatedly written, and the stored data can be stored even if the power is cut off. In a typical non-volatile memory Dash memory, the electromorphic system of a memory cell includes a so-called charge st〇rage layer, which is not floated. The floating gate is composed of an insulating film. The charge accumulates in the charge storage layer used to store the data. A variety of methods have recently been proposed to increase the amount of data that can be stored in a single memory unit. For example, in a virtual grounded flash memory, the region switches between the source region and the drain region to form two charges in the charge storage layer of a single memory cell. Storage area. This makes it possible to store 2 bits of data in a single memory unit. An unexamined patent application publication No. 2002-313967 discloses a charge storage layer having a shallow trench isolation (STI) region separated by STI (light trench isolation) regions. For example, a technique for forming a sti region for separating a charge storage layer using a mask layer made of a nitride film is disclosed in the Non-volatile Semiconductor Memory Workshop of Non-volatile Semiconductor Memory. , 3 94576 200937524 Pages 110 to 111. In a virtual grounded fast memory using an insulating film as a charge storage layer, if the charge storage layer is not separated in the channel (channel) direction in the memory cell, then the charges stored in the two charge storage regions are respectively stored. Will interfere with each other, the so-called CBD (CGmplementary

Bit Disturb’互補位元干擾）。目此要分隔儲存在兩電荷 儲存區域巾㈣荷是困_，_是#_用虛接地式的 快閃記憶體使”電薄膜作為電荷儲存層時，所儲存的電 荷會在電荷齡層㈣動。因此，電荷儲存層必須要在記 憶體單元中之通道方向被分隔。 當電何儲存層連接在兩記 荷儲存層的電荷會在其中移動 的臨界電壓。 【發明内容】. 憶體單元之間時，儲存在電 ’而影響到相鄰記憶體單元 〇 本發明之-個實施例是：_種半導財置，其具有 荷儲存層，該電荷儲存層於記憶體單元^通道=中 分隔，並且在兩相鄰記憶體單元間被進 造此半導體裝置的方法。 刀隔，以及 根據本發明其中一個面向， 仅 方法，勺kT* '、钕出一種半導體裝置 “方法包括下列步驟：在半導體基 層；利用形成於雷共神六su 上七成電何儲 荷儲存層及半導體基板中形成延伸之第—為遮旱而在 形成欲填人第-時内㈣緣_ ; ^ 1〇叫 中形成延伸跨過第—凹槽的第 ^層，、絕緣薄 價’韁由對形成在第 94576 4 200937524 凹槽下方的電荷儲存層進行氧化，以形成閘極絕緣薄膜； 形成欲填入第二凹槽之第一導體層；除去遮罩層；在第一 ' 導體層於寬度方向的兩個侧面上形成第二導體層，以形成 . 包含第一和第二導體層的字元線；以及利用字元線做為遮 罩來除去電荷儲存層。 根據本發明另一面向，提供一種半導體裝置，包括： 半導體基板，具有延伸的第一凹槽；絕緣薄膜，用來填入 第一凹槽，並且突出於半導體基板上表面的上方；字元線， ❹ 形成在半導體裝置上，並延伸跨過第一凹槽；閘極絕緣薄 膜，係形成在半導體基板上並位於字元線之寬度方向中心 . 下方，並且在字元線的延伸方向由絕緣薄膜所分隔；電荷 儲存層，係形成在半導體基板上，並位於字元線之寬度方 向兩端下方，並且於其間插進有閘極絕緣薄膜，以便在字 元線的延伸方向由絕緣薄膜分隔。 【實施方式】 q 第1圖是根據實施例之NAND型快閃記憶體的透視 圖。參見第1圖，形成在半導體基板10中延伸之第一凹槽 12。絕緣薄膜14係填入第一凹槽12内，並且從半導體基 板10的上表面突出。被填入絕緣薄膜14的凹槽12，是用 來當作STI (淺溝槽隔離）區域。在半導體基板10上形成 跨過第一凹槽12延伸的字元線16。在一實施例中，字元 線16是用來作為閘極電極。閘極絕緣薄膜18則是形成在 半導體基板10上並位於字元線16的寬度方向之中心下 方。閘極絕緣薄膜18係被絕緣薄膜14沿著字元線16長度 5 94576 200937524 或是延伸方向所分隔。料層25由隧道絕緣薄膜2〇、電 '荷儲，層22以及頂部絕緣薄膜24所組成。層疊層25係形 ·-成在子元線16沿著寬度方向的兩側下方，並插進閘極的絕 ，緣薄f 18。層疊層25係被絕緣薄膜14沿著字元線16長 度或疋延伸方向所分隔。用來作為源極區域與没極區域之 擴散區域26係於第一凹槽12之間形成在字元線16之寬度 方向兩侧的半導體基板10之内。 第2A圖至第8C圖係圖解一種用來製造根據一實施 例的NAND型快閃記憶體的方法。為了便於說明，此處將 敘述的不範方法是用來製造單一的記憶體單元。 參見第2A至2C圖，在一實施例中，隧道絕緣薄膜 20是由厚度約5nm的氧化矽薄膜所形成，電荷儲存層 疋由厚度約7nm的非晶石夕（amorphous siiicon)薄膜所形 成，而頂部絕緣薄膜24則是由厚度約15nm氧化矽薄膜所 形成’各層依序製作在p型矽基板的半導體基板1〇上方。 ❺如此便在半導體基板10的上形成層疊層25。隧道絕緣薄 膜2〇可採用熱氧化（thermal oxidation)製程來製作，而 電荷儲存層22和頂部絕緣薄膜24則可橡用CVD (Chemical Vapor Deposition，化學氣相沉積）法來製作。 具有延伸開口的遮罩層30係藉由CVD製程形成在頂 部絕緣薄膜24上。在一實施例中，遮罩層3〇是由厚度約 lOOnm的氮化矽薄膜所構成。以遮罩層30作為遮罩，透過 RIE ( reactive i〇n etching，反應性離子钱刻）製程钱刻層 疊層25與半導體基板10。結果，於層疊層25與丰導體基 6 94576 200937524 板10中形成延伸之第一凹槽12。絕緣薄膜14則是由氧化 • 矽薄膜所構成，其實質上係藉由高密度CVD電漿製程所 *- 沈積，以便填入第一凹槽12。之後，絕緣薄膜14可利用 CMP ( Chemical Mechanical Polishing，化學機械研磨法） 製程來移除，以暴露出遮罩層30的上表面。如此可讓絕緣 薄膜14的上表面齊平於遮罩層30的上表面。 參見第3A至3C圖，厚度約l〇〇nm的光阻材料（未 繪出）係塗敷在遮罩層30與絕緣薄膜14上。在一實施例 ❹中’藉由光阻收縮（resist shrink )或是雙曝光（double exposure)製程，於光阻材料内形成延伸跨過第一凹槽12、 寬度約30nm的開口。遮罩層3〇、頂部絕緣薄膜24以及絕 緣薄膜14能以光阻材料作為遮罩，利用RIE製程進行蝕 刻。如此可形成第二凹槽32，其於遮罩層3〇、頂部絕緣薄 膜24以及絕緣薄膜14中延伸跨過第一凹槽12。 在一實施例中，遮罩層3〇是由氮化矽薄膜製作雨成， φ而頂部絕緣薄膜24以及絕緣薄膜14.各者是由氧化矽薄膜 製作而成。因此於製作第二凹槽32的步驟中，遮罩層30 會被侧以暴露㈣部躲薄膜24喊面m緣薄膜 24以^絕緣薄膜可以同時被钱刻。即使已經移除了頂 β絕緣薄膜24而暴露出電荷儲存層22的表面，對於絕緣 薄膜14—仍可貝施過餘刻碰⑻以飯刻地更深。 因為電何儲存層22是由非晶石夕的薄膜所製作，因此即使是 私取過姓刻的方式也报難被姓刻。可實施過钱刻讓第二凹 槽32的下表面位於半導體基板ι〇的上表面之上。換言之， 94576 200937524 就是實施過侧好讓第二凹槽32的下表面位祕道絕緣 薄膜20的下表面之上。 : 參見第4A至4C圖，形成在第二凹槽32下方、表面 ，暴露出來的電荷儲存層22，係經由熱氧化製程來氧化。如 此可形成厚度約20nm、由氧化矽薄骐所構成的閘極絕緣薄 膜18 〇 參見第5A至5C圖，由非晶矽薄膜（或是多晶矽薄 ❹ 膜）所構成的第一導體層34實貧上以CVD製程沈積，以 便填入第二凹槽32。之後’可透過CMP製程來移除第一 導體層34 ,以便暴露出遮罩層30與絕緣薄膜14的每個上 表面。如此，將閘極絕緣薄膜18形成於第一導體層34之 下。 參見第6A至6C圖，利用第一導體層34與遮罩層30 作為遮罩，透過RIE製程來蝕刻絕緣薄膜14。如此可降低 絕緣薄膜14的高度。換言之，就是可以降低絕緣薄膜14 ©從了員部絕緣薄膜24上表面突出的量。之後，町逸過利用磷 •酸之濕蝕刻製程來移除遮罩層30。 參見第7A至7C圖，由非晶矽薄膜（戒是多SB梦薄 膜）製成、厚度約25nm的第二導體層36係遂過CVD製 程來沈積，以實質上覆蓋住第一導體層34。之後第一導體 層36的表面係利用rie製程來蝕刻。如此/來’第一導 體層36係留存在第一導體層34的寬度方向之雨侧’以形 成包含第一導體層34以及第二導體層36的字元線W閘 極絶緣薄膜18係形成於第一導體層34的下方’也就疋位 94576 200937524 於字元線16之寬度方向中心的下方。 參見第8A至8C圖，頂部絕緣薄膜24與電荷儲存層 \ 22係以字元線16作為遮罩並透過RIE製程來移除。因此 ’ 電荷儲存層22係留存於字元線16之寬度方向兩端的下 方。換言之，電荷儲存層22是形成於字元線16之寬度兩 端的下方，以插進閘極絕緣薄膜18。之後，可利用字元線 16與絕緣薄膜14作為遮罩，將砷離子植入半導體基板10。 如此可讓作為源極區域與汲極區域的擴散區域26於第一 ❹ 凹槽12之間形成於字元線16之寬度方向兩侧的半導體基 板10之内。 根據一實施例的製造方法，係利用形成在頂部絕緣薄 膜24之上並具有延伸開口的遮罩層30作為遮罩來钱刻層 疊層薄膜25以及半導體基板10，以形成延伸的第一凹槽 12，如第2A至2C圖所示。接著形成欲填入第一凹槽12 内的絕緣薄膜14。如第3A至3C圖所示，在遮罩層30與 φ 絕緣薄膜14内，形成延伸跨過第一凹槽12的第二凹槽Bit Disturb's complementary bit interference). The purpose of this is to separate the storage in the two charge storage areas (four) load is sleepy _, _ is # _ virtual ground type flash memory to make "electric film as a charge storage layer, the stored charge will be in the charge age layer (four) Therefore, the charge storage layer must be separated in the direction of the channel in the memory cell. When the storage layer is connected to the threshold voltage at which the charge of the two storage layers will move. [Summary] Between the two, the embodiment of the present invention is: _ kind of semiconductor package, which has a storage layer, the charge storage layer in the memory unit ^ channel = a method of separating the semiconductor device between two adjacent memory cells. The knife is separated, and according to one of the aspects of the present invention, only the method, the spoon kT* ', a semiconductor device is extracted, the method includes the following steps : in the semiconductor base layer; the formation of the extension in the storage layer and the semiconductor substrate of the Qicheng electric storage layer and the semiconductor substrate formed on the Leishenliusu--for the prevention of drought and the formation of the person-in-time (four) edge _ ; ^ 1 Howling Forming a layer extending across the first groove, the insulating thin price '缰 is oxidized by the charge storage layer formed under the groove of the 94576 4 200937524 to form a gate insulating film; a first conductor layer of the recess; removing the mask layer; forming a second conductor layer on both sides of the first 'conductor layer in the width direction to form a word line including the first and second conductor layers; The word storage line is removed by using a word line as a mask. According to another aspect of the present invention, a semiconductor device includes: a semiconductor substrate having an extended first recess; an insulating film for filling the first recess and protruding above the upper surface of the semiconductor substrate; , ❹ is formed on the semiconductor device and extends across the first recess; the gate insulating film is formed on the semiconductor substrate and located at the center of the width direction of the word line, and is insulated by the extending direction of the word line The film is separated by a charge storage layer formed on the semiconductor substrate and located below both ends of the width direction of the word line, and a gate insulating film is interposed therebetween so as to be separated by an insulating film in the extending direction of the word line . [Embodiment] q Fig. 1 is a perspective view of a NAND type flash memory according to an embodiment. Referring to Fig. 1, a first recess 12 extending in the semiconductor substrate 10 is formed. The insulating film 14 is filled in the first recess 12 and protrudes from the upper surface of the semiconductor substrate 10. The groove 12 filled in the insulating film 14 is used as an STI (Shallow Trench Isolation) region. A word line 16 extending across the first recess 12 is formed on the semiconductor substrate 10. In one embodiment, word line 16 is used as a gate electrode. The gate insulating film 18 is formed on the semiconductor substrate 10 and below the center of the width direction of the word line 16. The gate insulating film 18 is separated by the insulating film 14 along the length of the word line 16 5 94576 200937524 or the direction of extension. The material layer 25 is composed of a tunnel insulating film 2, an electric charge, a layer 22, and a top insulating film 24. The layered layer 25 is formed so as to be formed below the both sides of the sub-member line 16 in the width direction, and is inserted into the gate of the gate to be thin. The laminated layer 25 is separated by the insulating film 14 along the length of the word line 16 or the direction in which the ytterbium extends. A diffusion region 26 serving as a source region and a gate region is formed between the first recesses 12 in the semiconductor substrate 10 on both sides in the width direction of the word line 16. 2A through 8C are diagrams illustrating a method for fabricating a NAND type flash memory according to an embodiment. For ease of explanation, the anomalous method described herein is used to fabricate a single memory cell. Referring to FIGS. 2A to 2C, in one embodiment, the tunnel insulating film 20 is formed of a yttria film having a thickness of about 5 nm, and the charge storage layer 疋 is formed of an amorphous siiicon film having a thickness of about 7 nm. On the other hand, the top insulating film 24 is formed of a ruthenium oxide film having a thickness of about 15 nm. The respective layers are sequentially formed over the semiconductor substrate 1 of the p-type germanium substrate. Thus, the laminated layer 25 is formed on the semiconductor substrate 10. The tunnel insulating film 2 is formed by a thermal oxidation process, and the charge storage layer 22 and the top insulating film 24 are made of CVD (Chemical Vapor Deposition). A mask layer 30 having an extended opening is formed on the top insulating film 24 by a CVD process. In one embodiment, the mask layer 3 is formed of a tantalum nitride film having a thickness of about 100 nm. The mask layer 30 is used as a mask, and the layer 25 and the semiconductor substrate 10 are etched by a RIE (reactive ion etching) process. As a result, an extended first groove 12 is formed in the laminate layer 25 and the conductor base 6 94576 200937524. The insulating film 14 is composed of an oxide film, which is substantially deposited by a high-density CVD plasma process to fill the first recess 12. Thereafter, the insulating film 14 can be removed by a CMP (Chemical Mechanical Polishing) process to expose the upper surface of the mask layer 30. This allows the upper surface of the insulating film 14 to be flush with the upper surface of the mask layer 30. Referring to Figs. 3A to 3C, a photoresist material (not shown) having a thickness of about 10 nm is coated on the mask layer 30 and the insulating film 14. In one embodiment, an opening extending across the first recess 12 and having a width of about 30 nm is formed in the photoresist material by a resist shrink or double exposure process. The mask layer 3, the top insulating film 24, and the insulating film 14 can be etched by a RIE process using a photoresist as a mask. Thus, a second recess 32 is formed which extends across the first recess 12 in the mask layer 3, the top insulating film 24, and the insulating film 14. In one embodiment, the mask layer 3 is made of a tantalum nitride film, and the top insulating film 24 and the insulating film 14. Each is made of a hafnium oxide film. Therefore, in the step of fabricating the second recess 32, the mask layer 30 is laterally exposed to expose the (four) portion of the film 24, and the insulating film can be simultaneously engraved. Even if the top β insulating film 24 has been removed to expose the surface of the charge storage layer 22, the insulating film 14 can still be subjected to a deeper touch (8) to be deeper in the rice. Because the electricity storage layer 22 is made of a thin film of amorphous stone, even if it is privately taken, it is difficult to be engraved by the surname. The lower surface of the second recess 32 may be placed over the upper surface of the semiconductor substrate. In other words, 94576 200937524 is implemented on the lower surface of the lower surface insulating film 20 of the second recess 32. : Referring to FIGS. 4A to 4C, the surface of the second recess 32 is formed, and the exposed charge storage layer 22 is oxidized by a thermal oxidation process. Thus, a gate insulating film 18 composed of a hafnium oxide thin layer having a thickness of about 20 nm can be formed. Referring to FIGS. 5A to 5C, the first conductor layer 34 composed of an amorphous germanium film (or a polysilicon thin film) is formed. The lean is deposited by a CVD process to fill the second recess 32. The first conductor layer 34 is then removed through a CMP process to expose each of the upper surfaces of the mask layer 30 and the insulating film 14. Thus, the gate insulating film 18 is formed under the first conductor layer 34. Referring to FIGS. 6A to 6C, the insulating film 14 is etched through the RIE process using the first conductor layer 34 and the mask layer 30 as a mask. This can lower the height of the insulating film 14. In other words, it is possible to reduce the amount by which the insulating film 14 is protruded from the upper surface of the member insulating film 24. Thereafter, the furnace escapes the mask layer 30 by a wet etching process using phosphorus. Referring to FIGS. 7A to 7C, a second conductor layer 36 made of an amorphous germanium film (or a multi-SB dream film) having a thickness of about 25 nm is deposited by a CVD process to substantially cover the first conductor layer 34. . The surface of the first conductor layer 36 is then etched using a rie process. Thus, the first conductor layer 36 is left on the rain side in the width direction of the first conductor layer 34 to form a word line W including the first conductor layer 34 and the second conductor layer 36. The lower portion of the first conductor layer 34 is also clamped below the center of the width direction of the word line 16 in the direction of the line 94476 200937524. Referring to Figures 8A through 8C, the top insulating film 24 and the charge storage layer \22 are removed by the RIE process using the word line 16 as a mask. Therefore, the charge storage layer 22 remains below the both ends in the width direction of the word line 16. In other words, the charge storage layer 22 is formed under both ends of the width of the word line 16 to be inserted into the gate insulating film 18. Thereafter, arsenic ions can be implanted into the semiconductor substrate 10 by using the word line 16 and the insulating film 14 as a mask. Thus, the diffusion region 26 as the source region and the drain region can be formed in the semiconductor substrate 10 on both sides in the width direction of the word line 16 between the first trenches 12. According to the manufacturing method of an embodiment, the interlayer film 25 and the semiconductor substrate 10 are etched by using the mask layer 30 formed on the top insulating film 24 and having an extended opening as a mask to form an extended first groove. 12, as shown in Figures 2A through 2C. Next, an insulating film 14 to be filled in the first recess 12 is formed. As shown in FIGS. 3A to 3C, in the mask layer 30 and the φ insulating film 14, a second groove extending across the first groove 12 is formed.

32。如第4A至4C圖所示，形成在第二凹槽32下方的電 荷儲存層22係經氧化，以形成閘極絕緣薄膜18。如第5A 至5C圖所示，在第二凹槽32内填入第一導體層34，之後 如第6A至6C圖，移除遮罩層30。如第7A至7C圖，在 第一導體層34的寬度方向之南個侧面處形成第二導體層 36，以形成字元線16，而字元線16包含第一導體層34以 及第二導體層36。之後，利用字元線16作為遮罩，以蝕 刻的方式移除頂部絕緣薄膜24與電荷儲存層22，如第8A 94576 200937524 至8C圖所示。 在上述的製造方法中，如第1圖所示，係形成延伸在 ' 半導體基板10内部的第一凹槽12,並於第一凹槽12内填 ， 入絕緣薄膜14，其係從於半導體基板10的表面突出。電 荷儲存層22係被絕緣薄膜14在字元線16之長度或是延伸 方向所分隔，且形成於字元線16之寬度方向兩端之下方。 換言之，電荷儲存層22是在字元線16的延伸方向在兩相 鄰的記憶體單元之間被分隔，並進一步沿著字元線16的寬 © 度方向在兩相鄰的記憶體單元之間被分隔。再者，被絕緣 薄膜14在字元線16延伸的方向所分隔的閘極絕緣薄膜18 係形成在字元線16之寬度方向的中心下方。電荷儲存層 22被形成以插入閘極絕緣薄膜18。也就是說，在記憶體單 元的内部，係沿著通道的方向來分隔電荷儲存層22。 在一實施例中，電荷儲存層22在記憶體單元内部是 沿著通道方向被分開地形成。所以就算電荷儲存層22由像 @ 是非晶矽薄膜的導電薄膜所製成，在單一記憶體單元内部 也會形成兩個電荷儲存區域，因此可讓單一的記憶體單元 儲存兩個位元的資料。特別是當採用導電薄膜來製作電荷 儲存層22的時候，與採用絕緣薄膜的情形相較之下，可儲 存的電荷量會變得更大。當採用絕緣薄膜（如氮化矽薄膜） 來形成電荷儲存層22時，在記億體單元内即使沒有沿著通 道的方向來分隔，仍然可以製作出兩個電荷儲存區域。然 而，當電荷儲存層22沿著通道的方向被分隔時，可以避免 積聚在兩電荷儲存區域内的電荷互相干擾，也就是所謂的 10 94576 200937524 CBD (互補位元干擾）。如此可更有效地分隔儲存在兩電 荷儲存區域内的電荷。舉例來說，如果是採用絕緣薄膜來 \ 製作電荷儲存層22，在記憶體單元内電荷儲存層22會沿 , 著通道的方向被分隔。特別是當微型化（miniaturize )記 憶體單元，使得通道長度減少的時候，抑制CBD的效果可 以更好。 在一實施例中，電荷儲存層22係在兩相鄰的記憶體 單元之間被分隔。當電荷儲存層是連接在兩相鄰記憶體單 © 元之間的情況下，使用導電薄膜來製作電荷儲存層時會讓 積聚在電荷儲存層22内的電荷在兩相鄰的記憶體單元間 移動，而影響到相鄰記憶體單元的臨界電壓。舉例來說， 如果採用絕緣薄膜來製作電荷儲存層22，當記憶體單元被 微型化以縮短兩相鄰記憶體單元間的間距時，使有可能影 響相鄰記憶體單元的臨界電壓。在一實施例中，電荷儲存 層22是在兩相鄰的記憶體單元之間被分隔。所以不論是使 q 用導電薄膜或是絕緣薄膜來製作電荷儲存層22之情形，都 可以抑制相鄰的記憶體單元對於湘鄰記憶體單元之臨界電 壓的影響。採用這種方式，於一實施例中，於記憶體單元 内不但沿著通道的方向來分隔電荷儲存層22，也進一步在 兩相鄰的記憶體單元之間來分隔電荷儲存層22。如此可增 加可以用來製作電荷儲存層22的材料。 參見第8A至8C圖，使用字元線16作為遮罩，藉由 蝕刻移除電荷儲存層22，以便將電荷儲存層22形成在字 元線16之寬度方向兩端之下方。如此可以自我對齊 11 94576 200937524 (self-alignment.)字元線16的方式來製作電荷儲存層22。 參見第7A至7C圖，字元線16是由第一導體層34以及第 ' 二導體層36所形成，其中，第二導體層36是形成在第一 _ 導體層34的寬度方向的兩個側面。閘極絕緣薄膜18係形 成在第一導體層34的下方，而電荷儲存層22則是形成在 第二導體層36的下方。如此可藉由控制第二導體層之厚度 而避免電荷儲存層22的尺寸之增加。 參見第1圖，電荷儲存層22係形成在字元線16的兩 ❹端之下。相較於電荷儲存層形成在閘極電極之側表面上的 情形，此結構可以如預期地從字元線16施加電場。如此可 更有效率地在電荷儲存層22中儲存電荷。 參見第6A至6C圖，在第二凹槽32内填入第一導體 層34，然後利用第一導體層34以及遮罩層30作為遮罩， 蝕刻絕緣薄膜14。如此可減少絕緣薄膜14從頂部絕緣薄 膜24突出的量。因為此，如第7A至7C圖所示，當沈積 q 第二導體層36以實質覆蓋第一導體層34的時候，形成在 絕緣薄膜14侧表面上之第二導體層36的高度便可以降 低。在接下來實質上蝕刻第二導體層36的步驟，很有可能 會移除掉形成在絕緣薄膜14側面上的第二導體層36,因 此可避免第二導體層36仍然殘留在絕緣薄膜14的側面 • - j 上。舉例來說，如果第二導體層36仍然殘留在絕緣薄膜 14的侧面上.，相鄰的字元線16將會被電氣麵合。因此根 據一實施例的製造方法，其能夠避免相鄰字元線16發生電 氣耦合。 12 94576 200937524 參見第2A至2C圖，絕緣薄膜14係經形成為其上表 面會齊平於遮罩層30的上表面。舉例來說，在絕緣薄膜 \ 14的上表面低於遮罩層30的上表面的情形中，在形成第 . 一導體層34來填入第二凹槽32的步驟中（如第5A至5C 圖所示），可能會將第一導體層34疮成為於絕緣薄膜14上 方延伸於第一凹槽12的延伸方向。在上述的例子，相鄰的 第一導體層34可能會發生電氣耦合。也就是說，相鄰的字 元線16可能會發生電氣耦合。然而根據一實施例的製造方 ❹ 法，係將絕緣薄膜14形成為使其上表面齊平於遮罩層30 的上表面。如此可避免將第一導體層34形成為於絕緣薄膜 14的上方延伸於第一凹槽12的延伸方向。如此便可避免 相鄰的字元線16發生電氣耦合。 參見第3A至3C圖，第二凹槽32的下表面是位於半 導體基板10上表面的上方。如此可避免要被填入第二凹槽 32的第一導體層34接觸到半導體基板10,如第5A至5C q 圖所示。也就是說，可避免字元線16以及半導體基板10 互相接觸，而發生電氣躺合。如第3A至3C圖所示，以暴 露出電荷儲存層22的表面之方式形成第二凹槽32。於是 在形成閘極絕緣薄膜18的步驟裡，便能輕易氧化電荷儲存 層22，如第4A至4C圖所示。 根據一實施例的前述方法所製造的NAND型快閃記 憶體中，在字元線之寬度方向中心處的閘極絕緣薄膜18 的上方之字元線16的高度，可能會和位於絕緣薄膜14上 方之字元線16的高度不同。字元線16在寬度方向之中心 13 94576 200937524 處的高度係不同於字元線16在絕緣薄膜14上方、在寬度 方向之每一端的高度。 在另一實施例之NAND型快閃記憶體中，係採用實質 . 上相同的材料來形成電荷儲存層22及遮罩層30。以下參 照第9A至10B圖說明製造另一實施例之快閃記憶體的方 法。第9A至10B圖為例示性剖視圖，其分別對應於沿第 2圖B-B線所取之剖面。 進行如參照第2A至3C圖敘述的製造步驟，而採用 〇 氮化矽薄膜來製作電荷儲存層22。參見第9A圖，形成在 第二凹槽32下方的電荷锗存層22係藉由自由基氧化 (radical oxidation)製程或是電漿氧化製程來氧化，以形 成閘極絕緣薄膜18。由於是採用氮化矽薄膜來形成電荷儲 存層22與遮罩層30,故將遮罩層30的上表面與侧面兩者 予以氧化，以形成氧化物薄膜層38。 參見第9B圖，形成第一導體層34來填入第二凹槽 ©32。參照第9C圖，藉由RIE製程或是濕蝕刻製程（例如， • . · 使用氟酸（fluorinated acid))來移除氧化物薄膜38，以 暴露出第一導體層34的側面。 參見第10A圖，移除遮罩層30並在第一導體層34 之寬度方向兩侧面上形成第二導體層36,以形成字元線 16，其中字元線16係包含第一導體層34以及第二導體層 36。參見第10B圖，利用字元線16作為遮罩，以蝕刻的 方式移除頂部絕緣薄膜24以及電荷儲存層22。之後，在 第一凹槽12之間，在字元線16之寬度方向兩側的半導體 14 94576 200937524 基板10内製作擴散區域26，以作為源極區域以及汲極區 域兩者。 \ 在根據另一實施例的製造方法中，採用實質上類似的 ..材料來製作電荷儲存層22與遮罩層30。如第9A圖，於實 施藉由氧化電荷儲存層22以製作出閘極絕緣薄膜18的步 驟中，氧化物薄膜38會形成在遮罩層30的上表面與側面。 如第9C圖，於第二凹槽32中形成第一導體層34之後， 除去氧化物薄膜38以暴露出第一導體層34的侧面。如第 ❹ 10A圖，第一導體層34可與形成在第一導體層34兩侧面 上的第二導體層36發生電氣耦合。考慮到第一導體層34 與第二導體層36之間電氣耦合的關係，較佳的作法為移除 氧化物的薄膜38，以暴露出第一導體層34侧面的一半或 者是一半以上。 在透過前述方法所製造之另一實施例的NAND型快 閃記憶體中，在第一導體層34與第二導體層36之間形成 U 有氧化物薄膜38。換言之，氧化物薄膜38是形成在字元 線16内，而從閘極絕緣薄膜18在字元線16的寬度方向兩 側突出。 根據本發明的一個面向，提供一種用來製造半導體裝 置的方法，其包括下列步驟：在半導體基板上形成電荷儲 存層；利用形成在電荷儲存層上的遮罩層作為遮罩，而在 電荷儲存層與半導體基板内形成延伸的第一凹槽；形成欲 填入第一凹槽内的絕緣薄膜；在遮罩層與絕緣薄膜内形成 延伸跨過第一凹槽的第二凹槽；藉由氧化形成在第二凹槽 15 94576 200937524 下方的電荷儲存層’形成閘_緣薄膜；形成 凹槽的第一導體層;移除遮罩層；在第-導體層於 ==形成第二導體層，成包含 二 Ο ，層的子讀；以及字元線作為鮮來移除電荷J 方法可製作在記憶體單元内部於通道方向:存 ，广鄰記憶體單元之間被進一步分隔的電行:二 ^本方法還能以自我對齊字元線的方式來製作電荷儲ς 用韋-導體層與遮步驟之後，利 此可抑制相鄰的字元絕緣薄膜的步驟。如 驟:二，係成為 疋線發生電_合。 如此可抑制相鄰的字 ，二本表方二= μ線與铸縣板互相_，==上^^此可避免 在太太生丧蜩乂成電氣耦合。 成可暴露出電::以了的步驟中，第二四槽係製作 驟裡，可輕易地氧化電姆=形成_邑緣薄膜的步 "έ- ^ ^ . 步録，其利用Ί在半導體基板内部製作擴散區域的 在本方法中7°、M及絕緣薄膜來作為遮罩。 層的上表面與侧極絕緣薄膜的步驟係包含在遮罩 上形成氧化物薄膜的步驟t 94576 16 200937524 過形成第一導體層的步驟之後，實施移除氧化物薄膜的步 驟，以暴露出第一導體層之侧面。當採用實質上類似的材 *. 料來製作電荷儲存層與遮罩層時，如此可將第一導體層與 . 第二導體層予以電氣耦合。 根據本發明的另一面向，提出一種半導體裝置，包 括：半導體基板，其具有延伸的第一凹槽；絕緣薄膜，被 填入第一凹槽内並突出在半導體基板上表面的上方；字元 線，形成在半導體裝置上，並且延伸跨過第一凹槽；閘極 ❹ 絕緣薄膜，係形成在半導體基板上並位於字元線之寬度方 向中心下方，並且在字元線的延伸的方向由絕緣薄膜分 隔；以及電荷儲存層，係形成在半導體基板上並位於字元 線之寬度方向兩端下方，並且於其間插進有閘極絕緣薄 膜，以便在字元線的延伸方向由絕緣薄膜分隔。此結構提 供在記憶體單元内部於通道方向被分隔、並且在兩相鄰記 憶體單元之間被進一步分隔的電荷儲存層。 Φ 本結構中，字元線在閘極絕緣薄膜上方的高度，可能 會和字元線在絕緣薄膜上方的高度不同，其中閘極絕緣薄 膜是位於字元線寬度方向的中心處。 本結構包括位於字元線内的氧化物薄膜，其係從閘極 絕緣薄膜之在字元線寬度方向的兩端突出。 以上描述雖然是本發明的較佳實施例，但是本發明並 不侷限於這些特定的實施例，在由專利申請範圍所定義的 本發明之精神與範圍内，可採取別種作法與進行各樣的變 更。 17 94576 200937524 【圖式簡單說明】 第1圖是根據一實施例之NAND型快閃記憶體的例示 - 性透視圖。 ， 第2A圖的例示性透視谓展示一種方法，用來製作根 據一實施例的NAND型快閃記憶體。 第2B與2C圖是根據一實施例，沿著第2A圖中B-B 與C-C直線所取的例示性剖面圖。 第3A圖的例示性透視圖展示一種方法，用來製作根 〇 據一實施例的NAND型快閃記憶體。 第3B與3C圖是根據一實施例，沿著第3A圖中B-B 與C-C直線所取的例示性剖面圖。 第4A圖的例示性透視圖展示一種方法，用來製作根 據一實施例的NAND型快閃記憶體。 第4B與4C圖是根據一實施例，沿第4A圖中Β·Β與 C-C直線所取的例示性剖面圖。 0 第5Α圖的例示性透視圖展示一種方法，用來製作根 據一實施例的NAND型快閃記憶體。 第5B與5C圖是根據一實施例，沿著第5A圖中B-B 與C-C直線所取的例示性剖面圖。 第6A圖的例示性透視圖展示一種方法，用來製作根 據一實施例的NAND型快閃記憶體。 第6B與6C圖是根據一實施例，沿著第6A圖中B-B 與C-C直線所取的例示性剖面圖。 第7A圖的例示性透視圖展示一種方法，用來製作根 18 94576 200937524 據一實施例的NAND型快閃記憶體。 第7B與7C圖是根據一實施例，沿著第7A圖中B-B 與C-C直線所取的例示性剖面圖。 ’ 第8A圖的例示性透視圖展示一種方法，用來製作根 據一實施例的NAND型快閃記憶體。 第8B與8C圖是根據一實施例，沿著第8A圖中B-B 與C-C直線所取的例示性剖面圖。 第9A至9C圖的例示性剖面圖展示一種方法，用來 ❹ 製作根據另一實施例的NAND型快閃記憶體，每張圖相當 於沿著第2圖中B-B直線所取的剖面。 第10A與10B圖的例示性剖面圖展示一種方法，用 來製作根據另一實施例的NAND型快閃記憶體，每張圖相 當於沿著第2圖中B-B直線所取的剖面。 【主要元件符號說明】 10 半導體基板 12 第一凹槽 14 絕緣薄膜 16 字元線 18 閘極絕緣薄膜 20 隧道絕緣薄膜 22 電荷儲存層 24 頂部絕緣薄膜 25 層疊層 26 擴散區域 30 遮罩詹 32 第二凹槽 34 第一導體層 36 第二導體層 38 氧化物薄膜層 19 9457632. As shown in Figs. 4A to 4C, the charge storage layer 22 formed under the second recess 32 is oxidized to form the gate insulating film 18. As shown in Figs. 5A to 5C, the first conductor layer 34 is filled in the second recess 32, and then the mask layer 30 is removed as shown in Figs. 6A to 6C. As shown in FIGS. 7A to 7C, a second conductor layer 36 is formed at a south side of the width direction of the first conductor layer 34 to form a word line 16, and the word line 16 includes a first conductor layer 34 and a second conductor. Layer 36. Thereafter, the top insulating film 24 and the charge storage layer 22 are removed in an etched manner by using the word line 16 as a mask as shown in Figs. 8A 94576 200937524 to 8C. In the above manufacturing method, as shown in FIG. 1, a first recess 12 extending inside the 'semiconductor substrate 10 is formed, and is filled in the first recess 12, and an insulating film 14 is formed from the semiconductor. The surface of the substrate 10 protrudes. The charge storage layer 22 is partitioned by the insulating film 14 in the length or extension direction of the word line 16, and is formed below the both ends in the width direction of the word line 16. In other words, the charge storage layer 22 is separated between two adjacent memory cells in the extending direction of the word line 16, and further in the width direction of the word line 16 in two adjacent memory cells. Separated. Further, a gate insulating film 18 partitioned by the insulating film 14 in the direction in which the word line 16 extends is formed below the center in the width direction of the word line 16. The charge storage layer 22 is formed to be inserted into the gate insulating film 18. That is, inside the memory cell, the charge storage layer 22 is separated along the direction of the channel. In one embodiment, the charge storage layer 22 is formed separately along the channel direction inside the memory cell. Therefore, even if the charge storage layer 22 is made of a conductive film like @ is an amorphous germanium film, two charge storage regions are formed inside a single memory cell, so that a single memory cell can store two bits of data. . In particular, when a conductive film is used to form the charge storage layer 22, the amount of charge that can be stored becomes larger as compared with the case of using an insulating film. When an insulating film (e.g., a tantalum nitride film) is used to form the charge storage layer 22, two charge storage regions can be fabricated even if they are not separated in the direction of the channel. However, when the charge storage layers 22 are separated along the direction of the channels, the charges accumulated in the two charge storage regions can be prevented from interfering with each other, so-called 10 94576 200937524 CBD (complementary bit interference). This makes it possible to more effectively separate the charges stored in the two charge storage regions. For example, if the charge storage layer 22 is formed by using an insulating film, the charge storage layer 22 is separated in the direction of the channel in the memory cell. Especially when miniaturizing the memory unit, the effect of suppressing the CBD can be better when the channel length is reduced. In one embodiment, the charge storage layer 22 is separated between two adjacent memory cells. When the charge storage layer is connected between two adjacent memory cells, the use of the conductive film to form the charge storage layer causes the charge accumulated in the charge storage layer 22 to be between two adjacent memory cells. Move, which affects the threshold voltage of adjacent memory cells. For example, if an insulating film is used to form the charge storage layer 22, when the memory cells are miniaturized to shorten the spacing between two adjacent memory cells, it is possible to affect the threshold voltage of adjacent memory cells. In one embodiment, the charge storage layer 22 is separated between two adjacent memory cells. Therefore, the effect of the adjacent memory cells on the critical voltage of the adjacent memory cells can be suppressed by using the conductive film or the insulating film to form the charge storage layer 22. In this manner, in one embodiment, the charge storage layer 22 is separated not only in the direction of the channel in the memory cell, but also between the two adjacent memory cells. This makes it possible to add materials which can be used to form the charge storage layer 22. Referring to Figs. 8A to 8C, the word storage line 22 is removed by etching using the word line 16 as a mask so that the charge storage layer 22 is formed below both ends in the width direction of the word line 16. Thus, the charge storage layer 22 can be fabricated by self-aligning 11 94576 200937524 (self-alignment.) word lines 16. Referring to FIGS. 7A to 7C, the word line 16 is formed by the first conductor layer 34 and the 'second conductor layer 36, wherein the second conductor layer 36 is formed in the width direction of the first_conductor layer 34. side. The gate insulating film 18 is formed under the first conductor layer 34, and the charge storage layer 22 is formed under the second conductor layer 36. Thus, the increase in the size of the charge storage layer 22 can be avoided by controlling the thickness of the second conductor layer. Referring to Fig. 1, a charge storage layer 22 is formed under the two ends of the word line 16. This structure can apply an electric field from the word line 16 as expected, as compared to the case where the charge storage layer is formed on the side surface of the gate electrode. This makes it possible to store charges in the charge storage layer 22 more efficiently. Referring to Figs. 6A to 6C, the first conductor layer 34 is filled in the second recess 32, and then the insulating film 14 is etched by using the first conductor layer 34 and the mask layer 30 as a mask. This can reduce the amount by which the insulating film 14 protrudes from the top insulating film 24. Because of this, as shown in Figs. 7A to 7C, when the q second conductor layer 36 is deposited to substantially cover the first conductor layer 34, the height of the second conductor layer 36 formed on the side surface of the insulating film 14 can be lowered. . In the subsequent step of substantially etching the second conductor layer 36, it is highly possible to remove the second conductor layer 36 formed on the side of the insulating film 14, thereby preventing the second conductor layer 36 from remaining on the insulating film 14. Side • - j on. For example, if the second conductor layer 36 remains on the side of the insulating film 14, the adjacent word lines 16 will be electrically surfaced. Therefore, according to the manufacturing method of an embodiment, it is possible to avoid electrical coupling of adjacent word lines 16 . 12 94576 200937524 Referring to Figures 2A to 2C, the insulating film 14 is formed such that its upper surface is flush with the upper surface of the mask layer 30. For example, in the case where the upper surface of the insulating film \14 is lower than the upper surface of the mask layer 30, in the step of forming the first conductor layer 34 to fill the second groove 32 (e.g., 5A to 5C) As shown in the figure, the first conductor layer 34 may be formed to extend over the insulating film 14 in the extending direction of the first groove 12. In the above example, adjacent first conductor layers 34 may be electrically coupled. That is, adjacent word lines 16 may be electrically coupled. However, according to the manufacturing method of an embodiment, the insulating film 14 is formed such that its upper surface is flush with the upper surface of the mask layer 30. This prevents the first conductor layer 34 from being formed to extend in the extending direction of the first recess 12 above the insulating film 14. This avoids electrical coupling between adjacent word lines 16. Referring to Figs. 3A to 3C, the lower surface of the second recess 32 is located above the upper surface of the semiconductor substrate 10. Thus, the first conductor layer 34 to be filled in the second recess 32 can be prevented from contacting the semiconductor substrate 10 as shown in Figs. 5A to 5C q. That is, the word line 16 and the semiconductor substrate 10 can be prevented from coming into contact with each other, and electrical lying can occur. As shown in Figs. 3A to 3C, the second recess 32 is formed in such a manner as to expose the surface of the charge storage layer 22. Thus, in the step of forming the gate insulating film 18, the charge storage layer 22 can be easily oxidized as shown in Figs. 4A to 4C. In the NAND type flash memory manufactured by the foregoing method of the embodiment, the height of the word line 16 above the gate insulating film 18 at the center in the width direction of the word line may be located at the insulating film 14. The height of the upper character line 16 is different. The height of the word line 16 at the center of the width direction 13 94576 200937524 is different from the height of the word line 16 above the insulating film 14 at each end in the width direction. In another embodiment of the NAND type flash memory, the same material is used to form the charge storage layer 22 and the mask layer 30. A method of manufacturing a flash memory of another embodiment will be described below with reference to Figs. 9A to 10B. Figs. 9A to 10B are exemplary cross-sectional views respectively corresponding to the cross sections taken along line B-B of Fig. 2. The charge storage layer 22 is formed by using a tantalum nitride film as described in the description of Figs. 2A to 3C. Referring to Fig. 9A, the charge storage layer 22 formed under the second recess 32 is oxidized by a radical oxidation process or a plasma oxidation process to form a gate insulating film 18. Since the charge storage layer 22 and the mask layer 30 are formed using a tantalum nitride film, both the upper surface and the side surface of the mask layer 30 are oxidized to form the oxide thin film layer 38. Referring to Figure 9B, a first conductor layer 34 is formed to fill the second recesses ©32. Referring to Fig. 9C, the oxide film 38 is removed by an RIE process or a wet etching process (e.g., using fluorinated acid) to expose the side of the first conductor layer 34. Referring to FIG. 10A, the mask layer 30 is removed and a second conductor layer 36 is formed on both sides in the width direction of the first conductor layer 34 to form the word line 16, wherein the word line 16 includes the first conductor layer 34. And a second conductor layer 36. Referring to Fig. 10B, the top insulating film 24 and the charge storage layer 22 are removed by etching using the word line 16 as a mask. Thereafter, between the first recesses 12, a diffusion region 26 is formed in the substrate 14 on both sides of the width direction of the word line 16 in the semiconductor 14 94576 200937524 as both the source region and the drain region. In a fabrication method according to another embodiment, the charge storage layer 22 and the mask layer 30 are formed using substantially similar materials. As shown in Fig. 9A, in the step of forming the gate insulating film 18 by oxidizing the charge storage layer 22, an oxide film 38 is formed on the upper surface and the side surface of the mask layer 30. As shown in FIG. 9C, after the first conductor layer 34 is formed in the second recess 32, the oxide film 38 is removed to expose the side surface of the first conductor layer 34. As shown in Fig. 10A, the first conductor layer 34 can be electrically coupled to the second conductor layer 36 formed on both sides of the first conductor layer 34. In view of the electrical coupling relationship between the first conductor layer 34 and the second conductor layer 36, it is preferred to remove the oxide film 38 to expose half or more of the sides of the first conductor layer 34. In the NAND type flash memory of another embodiment manufactured by the above method, a U-containing oxide film 38 is formed between the first conductor layer 34 and the second conductor layer 36. In other words, the oxide film 38 is formed in the word line 16 and protrudes from the gate insulating film 18 on both sides in the width direction of the word line 16. According to an aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming a charge storage layer on a semiconductor substrate; using a mask layer formed on the charge storage layer as a mask, and storing the charge Forming an extended first groove in the layer and the semiconductor substrate; forming an insulating film to be filled in the first groove; forming a second groove extending across the first groove in the mask layer and the insulating film; Oxidizing a charge storage layer formed under the second recess 15 94576 200937524 to form a gate-edge film; forming a first conductor layer of the recess; removing the mask layer; forming a second conductor layer at the first conductor layer at == , the sub-read that contains the dice, the layer; and the word line as the fresh to remove the charge J method can be made inside the memory unit in the channel direction: the storage, the wide adjacent memory cells are further separated: The method can also be used to self-align the word lines to form a charge reservoir. After the step of using the Wei-conductor layer and the masking step, the step of suppressing the adjacent character insulating film can be suppressed. For example, the second line is the electricity generation. This can suppress adjacent words, two tables and two = μ line and the cast county board _, == on the ^ ^ this can avoid the electrical coupling of the wife. The step of exposing electricity to: in the step of the second four-channel system, the electrode can be easily oxidized = the step of forming a film of 邑 ^ ^ ^ ^ ^ ^. In the present method, a diffusion region is formed inside the semiconductor substrate by 7°, M, and an insulating film as a mask. The step of forming the upper surface and the side pole insulating film of the layer includes the step of forming an oxide film on the mask. t 94576 16 200937524 After the step of forming the first conductor layer, the step of removing the oxide film is performed to expose the first The side of a conductor layer. When a substantially similar material is used to form the charge storage layer and the mask layer, the first conductor layer and the second conductor layer can be electrically coupled. According to another aspect of the present invention, a semiconductor device includes: a semiconductor substrate having an extended first recess; an insulating film filled in the first recess and protruding above the upper surface of the semiconductor substrate; a line formed on the semiconductor device and extending across the first recess; a gate ❹ insulating film formed on the semiconductor substrate and located below the center of the width direction of the word line, and extending in the direction of the word line The insulating film is separated; and the charge storage layer is formed on the semiconductor substrate and located below both ends of the width direction of the word line, and a gate insulating film is interposed therebetween so as to be separated by an insulating film in the extending direction of the word line . This structure provides a charge storage layer that is separated inside the memory cell in the channel direction and further separated between two adjacent memory cells. Φ In this structure, the height of the word line above the gate insulating film may be different from the height of the word line above the insulating film, wherein the gate insulating film is located at the center of the width direction of the word line. The structure includes an oxide film located in the word line which protrudes from both ends of the gate insulating film in the width direction of the word line. The above description is a preferred embodiment of the present invention, but the present invention is not limited to the specific embodiments, and various other methods and various modifications can be made within the spirit and scope of the invention as defined by the scope of the patent application. change. 17 94576 200937524 [Simplified Schematic] FIG. 1 is an exemplary perspective view of a NAND type flash memory according to an embodiment. The exemplary perspective of Fig. 2A shows a method for fabricating a NAND type flash memory according to an embodiment. 2B and 2C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 2A, according to an embodiment. An exemplary perspective view of Fig. 3A shows a method for fabricating a NAND type flash memory according to an embodiment. 3B and 3C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 3A, according to an embodiment. The illustrative perspective view of Figure 4A shows a method for fabricating a NAND type flash memory in accordance with an embodiment. 4B and 4C are exemplary cross-sectional views taken along line Β·Β and C-C of Fig. 4A, according to an embodiment. An exemplary perspective view of Fig. 5 shows a method for fabricating a NAND type flash memory according to an embodiment. 5B and 5C are exemplary cross-sectional views taken along lines B-B and C-C in Fig. 5A, according to an embodiment. The illustrative perspective view of Figure 6A shows a method for fabricating a NAND type flash memory in accordance with an embodiment. 6B and 6C are exemplary cross-sectional views taken along lines B-B and C-C of Fig. 6A, according to an embodiment. An exemplary perspective view of Figure 7A shows a method for making a NAND type flash memory according to an embodiment of the root 18 94576 200937524. Figures 7B and 7C are exemplary cross-sectional views taken along lines B-B and C-C of Figure 7A, in accordance with an embodiment. The illustrative perspective view of Fig. 8A shows a method for fabricating a NAND type flash memory according to an embodiment. 8B and 8C are exemplary cross-sectional views taken along lines B-B and C-C of Fig. 8A, according to an embodiment. The exemplary cross-sectional views of Figs. 9A through 9C show a method for fabricating a NAND type flash memory according to another embodiment, each of which corresponds to a section taken along the line B-B in Fig. 2. The exemplary cross-sectional views of Figs. 10A and 10B show a method for fabricating a NAND type flash memory according to another embodiment, each of which corresponds to a section taken along the line B-B in Fig. 2. [Main component symbol description] 10 Semiconductor substrate 12 First recess 14 Insulating film 16 Word line 18 Gate insulating film 20 Tunnel insulating film 22 Charge storage layer 24 Top insulating film 25 Laminated layer 26 Diffusion region 30 Mask Zhan 32 Two grooves 34 first conductor layer 36 second conductor layer 38 oxide film layer 19 94576

Claims (1)

200937524 七、申請專利範圍： 1. 一種半導體裝置的製造方法，包括： ' 於半導體基板上形成電荷儲存層； . 利用形成在電荷儲存層上的遮罩層作為遮罩，而 於電荷儲存層和半導體基板中形成延伸的第一凹槽； 形成欲填入第一凹槽内的絕緣薄膜； ' 於遮罩層與絕緣薄膜中形成延伸跨過第一凹槽的 第二凹槽； 〇 藉由對形成在第二凹槽下方的電荷儲存層進行氧 化，而形成閘極絕緣薄膜； 形成欲填入第二凹槽内的第一導體層； 移除遮罩層； 在第一導體層於寬度方向的兩個側面上形成第二 導體層，以形成包含第一和第二導體層的字元線；以 及 Φ 利用字元線作為遮罩以移除電荷儲存層。 2·如專利申請範圍第1項的半導體裝置的製造方法，尚 包含在施行過形成第一導體層的步驟之後，利用第一 · 導體層與遮罩層作為遮罩，來蝕刻絕緣薄膜。 3. 如專利申請範圍第1項的半導體裝置的製造方法，其 中，該絕緣薄膜被形成為使其上表面齊平於遮罩層的 上表面。 4. 如專利申請範圍第1項的半導體裝置的製造方法，其 中，第二凹槽被形成為使其下表面位於半導體基板上 20 94576 200937524 表面的上方。 5.如專利申請範圍第1項的半導體裝置的製造方法，其 V. 中，第二凹槽被形成為使電荷的儲存層暴露出。 , 6.如專利申請範圍第1項的半導體裝置的製造方法，其 中，製作閘極絕緣薄膜之步驟係包含在遮罩層的上表 面與侧面雙方上形成氧化物薄膜，並且尚包括： 在施行過形成第一導體層的步驟之後，除去氧化 物薄膜，以暴露出第一導體層之侧面。 © 7.如專利申請範圍第1項的半導體裝置的製造方法，尚 包括利用字元線與絕緣薄膜作為遮罩，在半導體基板 内部形成擴散區域。 8. 一種半導體裝置，包括： 半導體基板，其具有延伸的第一凹槽； 絕緣薄膜，用來填入第一凹槽，並且突出於半導 體基板上表面的上方； 字元線，形成在半導體裝置上，並延伸跨過第一 凹槽； 閘極絕緣薄膜，係形成在半導體基板上並位於字 元線之寬度方向中心下方，並且在字元線的延伸方向 由絕緣薄膜分隔；以及 電荷儲存層，係形成在半導體基板上並位於字元 線之寬度方向兩端下方，於其間插進有閘極絕緣薄 膜，以便在字元線的延伸方向由絕緣薄膜分隔。 如專利申請範圍第8項的半導體裝置，其中，在寬度 21 94576 9. 200937524 方向中心處的閘極絕緣薄膜上的字元線之高度係不同 於在絕緣薄膜上的字元線之高度。 *- 10.如專利申請範圍第8項的半導體裝置，其包括位於字 . 元線内的氧化物薄膜，該氧化物薄膜係從閘極絕緣薄 膜之在字元線寬度方向的兩端突出。 ❹ Ο 22 94576200937524 VII. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising: 'forming a charge storage layer on a semiconductor substrate; using a mask layer formed on the charge storage layer as a mask, and on the charge storage layer and Forming an extended first groove in the semiconductor substrate; forming an insulating film to be filled in the first groove; forming a second groove extending across the first groove in the mask layer and the insulating film; Oxidizing the charge storage layer formed under the second recess to form a gate insulating film; forming a first conductor layer to be filled in the second recess; removing the mask layer; and width at the first conductor layer A second conductor layer is formed on both sides of the direction to form a word line including the first and second conductor layers; and Φ uses the word line as a mask to remove the charge storage layer. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising etching the insulating film by using the first conductor layer and the mask layer as a mask after the step of forming the first conductor layer is performed. 3. The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the insulating film is formed such that an upper surface thereof is flush with an upper surface of the mask layer. 4. The method of fabricating a semiconductor device according to claim 1, wherein the second recess is formed such that its lower surface is above the surface of the semiconductor substrate 20 94576 200937524. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in the V., the second recess is formed to expose the storage layer of the electric charge. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the gate insulating film comprises forming an oxide film on both the upper surface and the side surface of the mask layer, and further comprising: After the step of forming the first conductor layer, the oxide film is removed to expose the side of the first conductor layer. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a diffusion region in the semiconductor substrate by using a word line and an insulating film as a mask. 8. A semiconductor device comprising: a semiconductor substrate having an extended first recess; an insulating film for filling a first recess and protruding above an upper surface of the semiconductor substrate; a word line formed on the semiconductor device And extending across the first recess; the gate insulating film is formed on the semiconductor substrate and located below the center of the width direction of the word line, and is separated by an insulating film in the extending direction of the word line; and the charge storage layer The film is formed on the semiconductor substrate and located below both ends in the width direction of the word line, and a gate insulating film is interposed therebetween so as to be separated by an insulating film in the extending direction of the word line. The semiconductor device of claim 8, wherein the height of the word line on the gate insulating film at the center of the width 21 94576 9. 200937524 is different from the height of the word line on the insulating film. The semiconductor device of claim 8, which comprises an oxide film located in the word line, which is protruded from both ends of the gate insulating film in the width direction of the word line. ❹ Ο 22 94576
TW97146131A 2007-11-28 2008-11-28 Semiconductor device and method for manufacturing thereof TWI471936B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007308094A JP5491694B2 (en) 2007-11-28 2007-11-28 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW200937524A true TW200937524A (en) 2009-09-01
TWI471936B TWI471936B (en) 2015-02-01

Family

ID=40289231

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97146131A TWI471936B (en) 2007-11-28 2008-11-28 Semiconductor device and method for manufacturing thereof

Country Status (3)

Country Link
JP (1) JP5491694B2 (en)
TW (1) TWI471936B (en)
WO (1) WO2009070336A1 (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3233998B2 (en) * 1992-08-28 2001-12-04 株式会社東芝 Manufacturing method of nonvolatile semiconductor memory device
JP4834897B2 (en) * 2000-05-02 2011-12-14 ソニー株式会社 Nonvolatile semiconductor memory device and operation method thereof
US6670240B2 (en) * 2001-08-13 2003-12-30 Halo Lsi, Inc. Twin NAND device structure, array operations and fabrication method
JP2003258128A (en) * 2002-02-27 2003-09-12 Nec Electronics Corp Non-volatile semiconductor memory device, manufacturing method and operating method of the same
JP3983094B2 (en) * 2002-04-25 2007-09-26 Ｎｅｃエレクトロニクス株式会社 Method for manufacturing nonvolatile semiconductor memory device
KR100480645B1 (en) * 2003-04-01 2005-03-31 삼성전자주식회사 Method for manufacturing SONOS memory device with twin-ONO by reverse self-aligning process
JP4041076B2 (en) * 2004-02-27 2008-01-30 株式会社東芝 Data storage system
KR100655291B1 (en) * 2005-03-14 2006-12-08 삼성전자주식회사 Non-volatile semiconductor memory device and method of fabrication the same

Also Published As

Publication number Publication date
TWI471936B (en) 2015-02-01
WO2009070336A1 (en) 2009-06-04
JP5491694B2 (en) 2014-05-14
JP2009135155A (en) 2009-06-18

Similar Documents

Publication Publication Date Title
US6667503B2 (en) Semiconductor trench capacitor
JPH10270575A (en) Non-volatile semiconductor memory storage and manufacture thereof
TW200820380A (en) Manufacturing method for an integrated semiconductor structure
TWI285943B (en) Trench capacitor DRAM cell using buried oxide as array top oxide
JP2007335533A (en) Semiconductor memory and manufacturing method therefor
US20100190315A1 (en) Method of manufacturing semiconductor memory device
JP2009267208A (en) Semiconductor device, and manufacturing method thereof
TWI360203B (en) Non-volatile memory and method of manufacturing th
JP5733997B2 (en) Memory device
TWI294669B (en) Method for preventing trenching in fabricating split gate flash devices
TW200929445A (en) Semiconductor device for reducing interference between adjoining gates and method for manufacturing the same
TW201003903A (en) Semiconductor memory device and method of manufacturing the same
JP2004319586A (en) Nonvolatile semiconductor storage device and its manufacturing method
JP2005340853A (en) Nonvolatile semiconductor memory and its manufacturing method
US8669606B2 (en) Semiconductor device and method for manufacturing thereof
TWI464884B (en) Semiconductor device and method for manufacturing thereof
US6893918B1 (en) Method of fabricating a flash memory
TW200826282A (en) Semiconductor memory device and method of manufacturing the same
TW200937524A (en) Semiconductor device and method for manufacturing thereof
JP2010129740A (en) Non-volatile semiconductor memory device and method of manufacturing the same
TWI296837B (en) Method for manufacturing floating gate and non-volatile memory
JP5308024B2 (en) Semiconductor device and manufacturing method thereof
US20100270603A1 (en) Semiconductor device and method of manufacturing the same
CN101261959B (en) Method of manufacturing flash memory device
KR20100012504A (en) Method of fabricating semiconductor apparatus