KR100655291B1 - Non-volatile semiconductor memory device and method of fabrication the same - Google Patents

Non-volatile semiconductor memory device and method of fabrication the same Download PDF

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Publication number
KR100655291B1
KR100655291B1 KR20050021070A KR20050021070A KR100655291B1 KR 100655291 B1 KR100655291 B1 KR 100655291B1 KR 20050021070 A KR20050021070 A KR 20050021070A KR 20050021070 A KR20050021070 A KR 20050021070A KR 100655291 B1 KR100655291 B1 KR 100655291B1
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film
device isolation
insulating film
semiconductor substrate
memory device
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KR20050021070A
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Korean (ko)
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KR20060099690A (en
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이창현
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삼성전자주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • H01L29/42332Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

The present invention relates to a nonvolatile semiconductor memory. According to the nonvolatile semiconductor memory device of the present invention, an isolation layer defining an active region of a semiconductor substrate is recessed by a predetermined thickness so that an upper surface of the semiconductor substrate protrudes between the recessed isolation layers. A gate insulating film and a gate conductive film are formed along the upper surface of the device isolation film and the semiconductor substrate. Under the above structure, the gate insulating film formed on the semiconductor substrate is formed to have a uniform thickness in all regions including the center and the edge of the active region. As a result, the program / erase operation of data is performed at the same speed in each active region on the semiconductor substrate, and the overall performance of the semiconductor memory device can be improved.

Description

Non-volatile semiconductor memory device and method for manufacturing the same

1 is a cross-sectional view in a bit line direction of a conventional Sonos memory device;

2 is a cross-sectional view in a gate direction of a conventional Sonos memory device;

3a and 3b are views for explaining the problems of the prior art,

4A through 4D are gate sectional views of a nonvolatile semiconductor memory device according to various embodiments of the present disclosure;

5A through 5E are cross-sectional views illustrating a process of manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

♧ description of symbols for the main parts of the drawing

10-semiconductor substrate 20-gate insulating film

30-Tunneling insulating film 40-Charge storage film

50-blocking insulating film 60-gate conductive film

70-metal film 80-gate electrode

90-device separator

The present invention relates to a semiconductor memory, and more particularly to a nonvolatile semiconductor memory device and a method of manufacturing the same.

Semiconductor memory devices are used to store various types of data, and are generally classified into volatile and non-volatile memory devices. Volatile memory devices lose their stored data when their power supply is interrupted, while nonvolatile memory devices retain their stored data even when their power supply is interrupted. Therefore, non-volatile memory devices are widely used in various applications such as mobile phones or other memory cards for storing music or images, under the situation where power is not continuously available.

A nonvolatile memory device is classified into a floating gate type memory device and a floating trap type memory device according to a structure of forming a memory cell. A floating gate type memory device programs data by forming a floating gate isolated with an insulating layer between a semiconductor substrate and a control gate, and storing charge in the floating gate. In contrast, the floating trap type memory device programs data by storing a charge in a trap formed in a non-conductive charge storage layer between a semiconductor substrate and a gate electrode.

Since the floating gate type memory device uses a conductive floating gate, when a defect occurs in a portion of the tunneling insulating layer spaced apart from the floating gate and the semiconductor substrate, all of the charge stored in the floating gate may be lost. Therefore, a relatively thick tunneling insulating film is required to maintain the reliability of the floating gate type memory device. On the other hand, since the floating trap type memory device is stored in a deep level trap of charge, it has the advantage of using a thinner tunneling insulating film and operating at a relatively low voltage than the floating gate type memory device. have.

Typical structures of a floating trap type memory device include a silicon substrate having a channel region formed therein, an oxide film forming a tunneling layer, a nitride film used as a charge storage film, an oxide film used as a blocking film, and a control gate. It includes a conductive film used as an electrode. This is commonly referred to as a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) cell structure. In this case, the charge storage layer may have a form in which separate charge storage units in the form of dots such as silicon germanium (SiGe) quantum dots, silicon quantum dots, and metal quantum dots are distributed in addition to the nitride film, and a high dielectric material in the form of an insulating layer is an example of a modification. .

FIG. 1 is a cross-sectional view illustrating a configuration of a conventional Sonos memory device, and illustrates a state cut along a bit line.

Referring to FIG. 1, in the sonos memory device, a gate stack 2 is formed on a p-type semiconductor substrate 1, and the gate stack 2 includes a tunneling insulating layer 3 and a charge storage layer 3 which are sequentially stacked. 4) The blocking insulating film 5 and the gate conductive film 6 are patterned. Source / drain regions 7 and 8 are formed on both sides of the gate stack 2 by n-type impurities.

The charge storage film 4 usually has a trap level as a silicon nitride film, but the Sonos memory device uses the trap level, and a schematic operation process is as follows.

The materials corresponding to the semiconductor substrate 1, the tunneling insulating film 3, the charge storage film 4, the blocking insulating film 5 and the gate conductive film 6 each have a unique energy band gap, The difference creates a potential barrier at each interface. When a positive voltage is applied to the gate electrode 2 and the drain region 8 and the source region 7 is grounded, an electric field is formed along the channel from the source region 7 to the drain region 8. The electrons in the source region 7 are accelerated to the drain region 8 by the electric field, and some of them are tunneled with energy enough to pass through the potential barrier of the tunneling insulating layer 3 to charge storage layer 4. Trapped at the trap level. As such, when electrons are trapped and accumulated in the charge storage film 4, the threshold voltage of the transistor is increased to become a program state (or an erase state). On the contrary, when a negative voltage is applied to the gate stack 2, electrons trapped in the trap in the charge storage film 4 are tunneled through the tunneling insulating film 3 to exit to the semiconductor substrate 1. At the same time, holes from the semiconductor substrate 1 pass through the tunneling insulating film 3 and are trapped in the charge storage film 4, and the threshold voltage of the device is lowered to be in an erased state (or a program state).

2 is a sectional view in a gate direction of a conventional Sonos memory device. Referring to FIG. 2, an isolation layer 9 defining an active region is formed on the semiconductor substrate 1, and a tunneling insulation layer is formed along the upper surface of the isolation layer 9 and the semiconductor substrate 1 belonging to the active region. (3), the charge storage film 4 and the blocking insulating film 5 are stacked, and the gate conductive film 6 is formed on the blocking insulating film 5.

However, semiconductor memory devices, including the sonos memory device shown in FIGS. 1 and 2, have been reduced in size due to a high integration trend. Accordingly, the structure in the microscopic area, which has not been previously highlighted, may affect the operation of the memory device. Went crazy. In particular, the present invention relates to a structure at the boundary between the active region of the semiconductor substrate and the device isolation layer. Hereinafter, the problems inherent in the prior art will be described with reference to the accompanying drawings.

3A and 3B are diagrams for explaining a problem of the prior art. FIG. 3A is a detailed cross-sectional view of a gate direction of a conventional Sonos memory device, and FIG. 3B is an enlarged view of a dotted line of FIG. 3A.

Referring to FIG. 3A, the upper surface of the device isolation film 9 and the upper surface of the semiconductor substrate 1 in the active region defined by the device isolation film 9 are not actually formed at the same level, and there are minute steps. You can check it. In general, the device isolation layer 9 is formed by forming a pad insulating film pattern on the semiconductor substrate 1, forming a trench with an etch mask, and then filling the trench with an insulator. However, after the insulator is buried, planarization is performed to the upper surface of the semiconductor substrate 1, at which time the reference for the planarization is set to the position where the pad insulating film pattern is formed. Therefore, in the process, the top surface of the device isolation film 9 is inevitably formed higher than the top surface of the semiconductor substrate 10 belonging to the active region. However, the step difference between the device isolation film 9 and the top surface of the semiconductor substrate 1 is increased. If the tunneling insulating film 3, the charge storage film 4, the blocking insulating film 5, the gate conductive film 6, and the like are laminated in the present state, the films 3, 4, 5, and 6 are flattened. That is, as shown in Fig. 3A, the tunneling insulating film 3 or the like is formed concave with respect to the semiconductor substrate 1 in the region between the device isolation film 9 and the device isolation film 9. As described above, the step at the boundary between the active region of the device isolation film 9 and the semiconductor substrate 1 has not been considered in the related art, but recently, as the size of the semiconductor device is reduced, it is highlighted as a factor affecting the operating characteristics. have.

Referring to FIG. 3B, it can be seen that the thickness of the tunneling insulating film 3 and the like is different in the center and the edge in the active region between the device isolation layers 9. Therefore, when a voltage is applied to program / erase data, the electric field applied to the center and the edge of the active region is changed. That is, as shown in FIG. 3B, a uniform electric field is applied to the center of the active region, but the electric field becomes nonuniform toward the edge and the intensity thereof becomes small. However, as described above with reference to FIG. 1, the program / erase of data proceeds as the electric charge accelerated by the electric field is tunneled. Therefore, if the intensity of the electric field varies depending on the position, the program / erase at the center and the edge of the active region is consequently. Speed is different. This problem becomes more serious as the size of the memory cell is reduced and the area occupied by the edge portion of the active area is increased.

The present invention has been proposed to solve this problem in view of the above circumstances, and the technical problem to be achieved by the present invention is that a uniform electric field is applied at the center and the edge of the active area without a difference in speed depending on the location of the program / erase of data. A nonvolatile semiconductor memory device capable of operating and a method of manufacturing the same are provided.

In order to achieve the above technical problem, in the nonvolatile semiconductor memory device according to the present invention, a device isolation film defining an active region of a semiconductor substrate is recessed by a predetermined thickness so that an upper surface of the semiconductor substrate protrudes between the recessed device isolation films. Is formed. A gate insulating film and a gate conductive film are formed along the upper surface of the device isolation film and the semiconductor substrate, and the gate insulating film includes a tunneling insulating film, a charge storage film, and a blocking insulating film. In the above structure, the gate insulating film formed on the semiconductor substrate is formed to have a uniform thickness, including the center and the edge of the active region, and the electric field for programming / erasing the semiconductor memory device is also uniform regardless of the position on the semiconductor substrate. Can be applied.

According to an embodiment of the nonvolatile memory device of the present invention, the recess region of the device isolation layer may be filled with only the tunneling insulating layer and the charge storage layer, which is implemented by forming the charge storage layer thickly in the process step. . The recess thickness of the device isolation layer is not particularly limited, but may be limited to within 5 to 20% of the total thickness of the device isolation layer that is initially formed in order to prevent the function of the device isolation layer from being weakened.

Alternatively, according to another embodiment of the present invention, considering that the gate insulating film filling the recess region of the device isolation film is an insulator component similar to the device isolation film, the entire device isolation film may be recessed and removed to replace the device isolation film as the gate insulating film. have. Specifically, the tunneling insulating film may be a silicon thermal oxide film, and the charge storage film may include a silicon nitride film, a silicon oxynitride film, a high dielectric film, a film including silicon dots, a film containing silicon germanium dots, and germanium dots. The film may include any one of a film, a film including a metal dot, and a film including a nitride dot, and the blocking insulating film may be any one of a silicon oxide film, a high dielectric film, and a metal oxide film, or a combination thereof.

According to another embodiment of the present invention, a metal film is further included between the blocking insulating film and the gate conductive film. The metal film is a conductive material having a value of 4.0 eV or more as a work function, and representative examples thereof are titanium nitride film (TiN), titanium silicon film (TiSiN), tantalum nitride film (TaN), tungsten nitride film (WN), and nitride nitride The film may be any one of, or a combination of, an aluminum film (HfN), a tantalum nitride silicon (TaSiN), a tungsten film (W), and a titanium film (Ti) to increase the data erase speed.

In order to manufacture the nonvolatile semiconductor memory device as described above, forming an isolation layer on a semiconductor substrate to define an active region, recessing the isolation layer by a predetermined thickness, and forming a semiconductor substrate belonging to the isolation layer and the active region Sequentially forming a gate insulating film and a gate conductive film along the upper surface of the substrate. In addition, as an embodiment of the nonvolatile semiconductor memory device of the present invention, in the case of replacing the device isolation film with the gate insulating film, a gate insulating film is formed immediately after forming a trench defining an active region even if a separate device isolation film is not recessed. And a gate conductive film may be formed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be applied and modified in various forms. Rather, the following embodiments are provided only to clarify the technical spirit disclosed by the present invention and furthermore, to sufficiently convey the technical spirit of the present invention to those skilled in the art having an average knowledge in the field to which the present invention belongs. The scope of should not be construed as limited by the embodiments described below. In addition, in the drawings presented in conjunction with the following examples, the size of layers and regions are simplified or somewhat exaggerated to emphasize clarity, and like reference numerals in the drawings indicate like elements.

4A through 4D are cross-sectional views of a gate direction of a nonvolatile semiconductor memory device according to various embodiments of the present disclosure.

Referring to FIG. 4A, an isolation layer 90 defining an active region is formed on a semiconductor substrate 10, and a gate insulating layer is formed along the upper surface of the isolation layer 90 and a semiconductor substrate 10 belonging to an active region. 20 and the gate conductive film 60 are laminated. The gate insulating film 20 may include a tunneling insulating film 30, a charge storage film 40, and a blocking insulating film 50 in a sonos memory device, which is one of typical nonvolatile memory devices. At this time, as shown in FIG. 4A, the surface of the device isolation film 90 is recessed so that the upper surface thereof is lower than that of the semiconductor substrate 10. As a result, the surface of the semiconductor substrate 10 belonging to the active region between the device isolation film 90 protrudes upward, the device isolation film 90 is in a concave state. Compared to FIG. 3A of the related art, the device isolation film 90 is formed slightly higher than the upper surface of the semiconductor substrate 10 so that the portion where the gate insulating film 20 is stepped is the device isolation film 90. In contrast, in the present invention, a portion where the thickness of the gate insulating film 20 is unevenly formed and stepped is formed inside the concave recessed isolation layer 90. Therefore, the gate insulating film 20 having a uniform thickness is formed on the semiconductor substrate 10 only at least for the active region, and the problem that the operation speed varies depending on the region in the program / erasure of data, etc. can be solved.

The recess thickness of the device isolation layer 90 may be selected in a range of 5 to 20% of the total thickness of the device isolation layer 90 that was originally formed to define the active region. As the device isolation layer 90 is deeply recessed, an area where the gate insulating layer 20 is stepped may be moved to an inner region of the recessed device isolation layer 90. However, as the depth of the device isolation film 90 decreases, the function of causing each device to suffer physically or electrically may be weakened, so the recess thickness is selected within a limited range. Therefore, when the device isolation film 90 of the sonos memory device is formed at about 4000 mW, it is preferable to recess about 300 to 400 mW of the device isolation film 90. However, the above recess thickness may be somewhat relative. If there is a concern that the thickness of the device isolation layer 90 may cause a problem, the trench for forming the first device isolation layer 90 may be formed deeper and may be sufficient as necessary. A method of recessing the device isolation film 90 having a thickness may be applied.

4B is a view according to another embodiment of the present invention. Referring to FIG. 4B, an isolation layer 90 defining an active region is formed on the semiconductor substrate 10, and a tunneling insulating layer is formed along the upper surface of the isolation layer 90 and the semiconductor substrate 10 belonging to the active region. The gate insulating film 20 and the gate conductive film 60 made of the 30, the charge storage film 40, and the blocking insulating film 50 are formed. The surface of the device isolation film 90 is recessed, and the upper surface of the device isolation film 90 is lower than that of the semiconductor substrate 10. 4A, the recess region of the device isolation layer 90 is filled only with the tunneling insulation layer 30 and the charge storage layer 40, and the blocking insulation layer 50 is not inserted into the recess region. Is that. This does not cause a large difference in operation of the memory device, but differs in that the charge storage layer 40 is formed thick in the manufacturing process.

4C is a view according to another embodiment of the present invention. Referring to FIG. 4C, in the present embodiment, a trench for an isolation layer defining an active region is formed on the semiconductor substrate 10, but there is no separate isolation layer. That is, the entire device isolation film is recessed and removed to replace the device isolation film with the gate insulating film 20. Although the thickness of the portion where the device isolation layer is recessed has been limited to a predetermined range, the materials constituting the gate insulating film 20 are all insulating materials, as described below. Thus, even if the device isolation film is removed, the gate insulating film 20 may be removed. As a substitute for device isolation.

The lowermost layer of the gate insulating film 20 is made of a thermal oxide film (SiO 2 ) obtained by oxidizing a silicon semiconductor substrate with the tunneling insulating film 30. On the other hand, since the device isolation film is usually formed of an oxide film by HDP (High Density Plasma) or the like, the substantial components are the same. Next, the charge storage film 40 uses a silicon nitride film (Si 3 N 4 ) as an insulating film having a higher trap density and higher electron affinity than the tunneling insulating film 30 or the blocking insulating film 50. Ride films (SiON), films containing silicon dots, films containing nitride dots, ferroelectric layers and the like can be used. Lastly, as the blocking insulating film 50, a silicon oxide film is generally used, but a high dielectric film or a metal oxide film having a high dielectric constant and a large energy band gap may be used. Specifically, materials such as aluminum oxide film (Al 2 O 3 ), tantalum pentoxide (Ta 2 O 5 ), titanium dioxide film (TiO 2 ), hafnium aluminum oxide films (HfAlO, HfAlON), and hafnium silicon oxide films (HfSiO, HfSiON) A film may be used or a film made of a combination of the above high dielectric material films may be used.

As described above, since the three layer films constituting the gate insulating film 20 are all made of an insulating material, the device isolation film may be replaced with the gate insulating film 20. In particular, in the present invention, since the active region is formed to protrude relatively upward, effective isolation between devices can be achieved even without a separate device isolation layer, and a structure in which the entire device isolation layer is recessed can be used as shown in FIG. 3C.

4d is a view according to another embodiment of the present invention. Referring to FIG. 4D, an isolation layer 90 defining an active region is formed on the semiconductor substrate 10, and a gate insulating layer is formed along the upper surface of the isolation layer 90 and the semiconductor substrate 10 belonging to the active region. 20, metal film 70, and gate conductive film 60 are formed. In addition to the upper surface of the device isolation film 90 is lower than the upper surface of the semiconductor substrate 10, in particular a metal film 70 was added. 4D is applied to the embodiment of FIG. 4A to which the metal film 70 is added, so that the metal film 70 fills a part of the region where the device isolation film 90 is recessed. However, the metal film 70 may also be applied to FIG. 4B or 4C. For example, if the metal film 70 is applied to FIG. 4B, the region where the device isolation film 90 is recessed may be filled only with the tunneling insulating film 30 and the charge storage film 40. The metal film 70 is formed only on the blocking insulating film 50. The metal film 70 should have a larger work function than the n-type polysilicon normally used as the gate conductive film 60. Specifically, a titanium nitride film (TiN), titanium nitride film (TiSiN), tantalum nitride film (TaN), tungsten nitride film (WN), hafnium nitride film (HfN), or tantalum silicon nitride film (TaSiN) having a work function of 4 eV or more. ) And a film obtained by combining these film components.

The metal layer 70 added as described above forms a gate electrode together with the gate conductive layer 60 and serves to shorten the erase and write operation time in the erase mode. As described above, in the erase mode, the electrons trapped in the trap in the charge storage film 40 are emitted to the semiconductor substrate 10 through the tunneling insulating film 30. In this case, the blocking insulating film ( By tunneling 50, electrons may be injected into the charge storage layer 40. These electrons act as a factor to delay the erase time, but in the embodiment of the present invention, by adding the metal film 70, a high potential barrier is formed between the gate conductive film 60 and the blocking insulating film 50. As a result, the probability of electrons tunneling the blocking insulating film 50 is reduced, and the operation time in the erase mode is also shortened. As shown in FIG. 4D, an electrode may be formed by sequentially stacking the metal film 70 and the polysilicon conductive film 60. Alternatively, the metal film 70 having a higher work function than the n-type polysilicon may be used. An electrode can be formed.

A method of manufacturing the semiconductor memory device shown in FIGS. 4A to 4D will be described. A method of manufacturing a nonvolatile semiconductor memory device of the present invention is characterized by including the step of recessing the device isolation film. Hereinafter, a manufacturing method for the embodiment of FIG. 4A will be described with reference to FIGS. 5A to 5E, but a similar manufacturing method may be applied to the invention shown in FIGS. 4B to 4D.

Referring to FIG. 5A, an isolation layer 90 defining an active region is formed on the semiconductor substrate 10. The isolation layer 90 may be formed according to a conventional shallow trench isolation (STI) method. For example, after forming a pad insulating film made of an oxide film and a nitride film on the semiconductor substrate 10, they are patterned to expose a region where the trench of the semiconductor substrate 10 is to be formed. Subsequently, the semiconductor substrate 10 is etched using the patterned pad insulating layer as a mask to form a trench. Next, a silicon oxide film (not shown) is formed on the entire surface of the resultant trench to protect the inner wall of the trench, and the trench is filled with an USG (Undoped Silicate Glass) film or HDP (High Density Plasma) oxide film having excellent gap fill performance. . Thereafter, when the oxide film filling the trench is planarized and the pad insulating film pattern is removed, an isolation layer 90 is formed to separate the active and inactive regions as shown in FIG. 5A.

Referring to FIG. 5B, the device isolation layer 90 is recessed to remove a predetermined thickness from the surface. The thickness to be removed may be determined within a range of 5 to 20% of the thickness of the device isolation film 90 that was originally formed. For example, when the device isolation film 90 of about 4000 mW is formed, the thickness may be approximately 300 to 400 mW. The etching of the device isolation layer 90 may use both dry and wet etching of the oxide layer. For example, when wet etching is applied, an etchback is applied using a buffered solution of hydrogen fluoride (HF) or a solution of hydrogen fluoride diluted with water. At this time, the semiconductor substrate 10 is immersed in an etchant, or the etchant is sprayed onto the semiconductor substrate 10.

The nonvolatile semiconductor memory device of the present invention is characterized in that the semiconductor substrate 10 protrudes upward from the device isolation layer 90. In FIG. 5B, the semiconductor substrate 10 is formed by lowering the height of the device isolation film 90 by recessing the device isolation film 90 while the semiconductor substrate 10 and the device isolation film 90 are formed at the same level. It is intended to protrude. However, in a similar principle, in the state where the semiconductor substrate 10 and the device isolation film 90 are formed at the same level, the semiconductor substrate 10 is grown by a selective epitaxy method to increase the height of the semiconductor substrate 10. 10) may be protruded. In addition, when the device isolation film 90 is replaced with the gate insulating film 20 as shown in FIG. 4C, it is not necessary to form the device isolation film 90. Therefore, although the entire device may be recessed after the device isolation film 90 is formed, the trenches defining the active region may be formed, and the formation and recess steps of the device isolation film 90 may be omitted, and the gate insulating film 20 may be immediately removed. A step of depositing the gate conductive layer 60 (see FIGS. 5C and 5D) may be applied.

Referring to FIG. 5C, the gate insulating film 20 including the tunneling insulating film 30, the charge storage film 40, and the blocking insulating film 50 is formed on the resultant device isolation film 90. The tunneling insulating layer 30 may be formed by thermal oxidation of a resultant product of FIG. 5B or by low pressure CVD (LPCVD). Next, the charge storage layer 40 is formed. If the nitride layer is formed of a conventional nitride layer, the tunneling insulating layer 30 may be formed by nitriding or low pressure chemical vapor deposition. Subsequently, a thermal insulating method or the like is applied on the charge storage layer 40 to form the blocking insulating layer 50.

Referring to FIG. 5D, the gate conductive layer 60 is formed on the resultant product on which the gate insulating layer 20 is formed. Here, as in the embodiment of FIG. 4D, a separate metal film may be formed before the gate conductive film 60. The gate conductive layer 60 may be doped polysilicon or may be composed of the doped polysilicon and metal silicide. The polysilicon may be deposited by chemical vapor deposition, and may have conductivity by doping impurities in the deposition process or by doping impurities after deposition.

Referring to FIG. 5E, a general process such as patterning the gate insulating film and the gate conductive film and implanting impurity ions is performed. For reference, in FIGS. 5A to 5E, FIGS. 5A to 5D are cross-sectional views in a gate direction, and FIG. 5E is a cross-sectional view taken along a bit line. As shown in FIG. 5E, the gate conductive layer and the gate insulating layer are successively patterned to form gate electrodes 80s, 80w, and 80g, which include a string select line 80s and a ground select line 80g, A plurality of word lines 80w are included. Subsequently, impurity ions are implanted into the impurity region 85 of the semiconductor substrate 10 using the gate electrodes 80s, 80w, and 80g as ion implantation masks to form transistors. Thereafter, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 10, and a normal process of forming a contact connected to the impurity region 85 or a bit line connected to the contact is performed.

As described above, according to the present invention, a gate insulating film having a uniform thickness is formed on a semiconductor substrate, and the same size is formed at any position including the center and the edge of the active region of the semiconductor substrate during the program / erase operation of data. Can be operated. Therefore, the performance of the semiconductor memory device can be improved overall, such as the program / erase operation of data at the same speed regardless of a specific position on the semiconductor substrate.

Claims (20)

  1. A device isolation film defining an active region of the semiconductor substrate, a gate insulating film formed of a tunneling insulating film, a charge storage film, and a blocking insulating film formed along the upper surface of the device isolation film and the semiconductor substrate, and a gate conductive film formed on the gate insulating film. ;
    The device isolation layer is recessed to a predetermined thickness so that an upper surface of the semiconductor substrate belonging to the active region is formed to protrude between the recessed device isolation layers, and the region of the recessed device isolation layer is filled by the gate insulating layer. And a gate insulating layer has a uniform thickness on the active region.
  2. The nonvolatile semiconductor memory device of claim 1, wherein the recessed isolation region is filled only with the tunneling insulating layer and the charge storage layer of the gate insulating layer.
  3. The nonvolatile semiconductor memory device of claim 1, further comprising a metal layer between the gate insulating layer and the gate conductive layer.
  4. 4. The nonvolatile semiconductor memory device of claim 3, wherein the metal film is formed to fill the recessed device isolation region.
  5. The nonvolatile semiconductor memory device of claim 1, wherein the recess thickness of the device isolation layer is 5 to 20% of the total thickness.
  6. 6. The nonvolatile semiconductor memory device of claim 5, wherein the recess thickness of the device isolation layer is about 300 to about 400 microns.
  7. The nonvolatile semiconductor memory device according to any one of claims 1 to 4, wherein the entire device isolation film is recessed and removed.
  8. The nonvolatile semiconductor memory device according to any one of claims 1 to 4, wherein the tunneling insulating film is made of a silicon thermal oxide film.
  9. 5. The charge storage film of claim 1, wherein the charge storage film comprises a silicon nitride film, a silicon oxynitride film, a high dielectric film, a film containing silicon dots, a film containing silicon germanium dots, and germanium dots. Non-volatile semiconductor memory device, characterized in that any one of a film, a film containing a metal dot, a film containing a nitride dot.
  10. The nonvolatile semiconductor memory device according to any one of claims 1 to 4, wherein the blocking insulating film is any one of a silicon oxide film, a high dielectric film, and a metal oxide film, or a film formed by combining two or more of the film components.
  11. The nonvolatile semiconductor memory device according to any one of claims 1 to 4, wherein the gate conductive film is made of polysilicon.
  12. The nonvolatile semiconductor memory device of claim 3, wherein a work function of the metal film is greater than 4.0 eV.
  13. The metal film of claim 12, wherein the metal film is a titanium nitride film (TiN), a titanium nitride film (TiSiN), a tantalum nitride film (TaN), a tungsten nitride film (WN), a hafnium nitride film (HfN), or a tantalum nitride silicon film ( Non-volatile semiconductor memory, characterized in that any one of TaSiN, titanium film (Ti), tungsten film (W), iridium film (Ir, IrO), platinum film (Pt) or a combination of two or more of the film components Device.
  14. Forming an isolation layer on the semiconductor substrate to define an active region;
    Recessing the device isolation layer by a predetermined thickness;
    Forming a gate insulating film including a tunneling insulating film, a charge storage film, and a blocking insulating film along an upper surface of the device isolation film and a semiconductor substrate belonging to an active region; And
    Forming a gate conductive film on the gate insulating film,
    And the gate insulating film is formed to have a uniform thickness on the active region.
  15. delete
  16. 15. The method of claim 14, further comprising forming a metal film between the gate insulating film and the gate conductive film.
  17. The method of claim 14, wherein the recessing of the device isolation layer is performed by dry or wet etching a predetermined thickness of the device isolation layer.
  18. 17. The method of claim 14, wherein the recessing of the device isolation layer removes the entire device isolation layer by dry or wet etching.
  19. Forming a trench defining an active region on the semiconductor substrate;
    Forming a gate insulating film including a tunneling insulating film, a charge storage film, and a blocking insulating film along an upper surface of the semiconductor substrate belonging to the trench and the active region; And
    Forming a gate conductive film on the gate insulating film,
    And the gate insulating film is formed to have a uniform thickness on the active region.
  20. delete
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US11/296,479 US7714379B2 (en) 2005-03-14 2005-12-08 SONOS floating trap memory device formed in recess with the lower surface of the conductive gate formed higher that the upper surface of the active region
DE200610005547 DE102006005547A1 (en) 2005-03-14 2006-02-07 Semiconductor memory device, e.g. silicon-oxide-nitride-oxide-semiconductor device for use in, e.g., memory card, has metal film generating high potential barrier between conductive gate film and blocking insulation film
CN200610007064XA CN1835240B (en) 2005-03-14 2006-02-14 Nonvolatile semiconductor memory device and method of fabricating the same

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