JP5313486B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a charge storage layer separated in a channel direction and a word line extension direction to make a memory cell compact. <P>SOLUTION: The method of manufacturing the semiconductor device includes the steps of: forming grooves 40 extended on a semiconductor substrate 10; forming a first insulating film 30 on the semiconductor substrate between grooves; forming a second insulating film 32 so as to be buried in the grooves; forming word lines 20 extending while crossing the second insulating film on the first insulating film and second insulating film; removing the first insulating film and the second insulating film having a faster etching rate than the first insulating film from between the word lines so that the first insulating film is left below word line center portions; and forming a charge storage layer 14 below the word lines in regions where the first insulating film is removed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a separated charge storage layer.

  Nonvolatile memories, which are semiconductor devices that can rewrite data and retain stored data even when the power is turned off, are widely used. In a flash memory, which is a typical nonvolatile memory, a transistor constituting a memory cell has a floating gate or an insulating film called a charge storage layer. Data is stored by accumulating charges in the charge accumulation layer. There is a SONOS (Silicon Oxide Nitride Oxide Silicon) type flash memory that accumulates charges in a nitride film in an ONO (Oxide Nitride Oxide) film as a flash memory having an insulating film as a charge storage layer. As one of the SONOS type flash memories, there is a virtual ground type flash memory capable of storing 2 bits in a charge storage layer in one memory cell by switching between a source region and a drain region.

  In recent years, demands for miniaturization and high integration of memory cells have increased. When the memory cell is miniaturized and highly integrated, and the channel length is shortened, the charges accumulated in the charge accumulation layer approach each other. This increases the influence of a phenomenon called CBD (Complementary bit disturb) in which the charges accumulated in the charge accumulation layer interfere with each other, making it difficult to separate the charges from each other.

As a method for suppressing the movement of charges accumulated in the charge accumulation layer in the channel direction, a method of separating the charge accumulation layer in the channel direction has been proposed (for example, Patent Document 1). Thereby, the influence of CBD can be suppressed.
JP-T-2006-521024

  However, as the miniaturization and high integration of memory cells progress, not only the channel length but also the interval between adjacent memory cells in the extending direction of the word line 20 becomes narrower. Here, FIG. 1 shows an example of a NAND flash memory in which the charge storage layer is separated in the channel direction. In FIG. 1, the charge storage layer 14 is shown through the word line 20.

  Referring to FIG. 1, an element isolation insulating film 24 is formed extending in the semiconductor substrate 10. A word line 20 also serving as a gate is formed above the semiconductor substrate 10 and extends across the element isolation insulating film 24. A source / drain region 22 defined by a word line 20 and an element isolation insulating film 24 is formed in the semiconductor substrate 10. The charge storage layer 14 is formed by extending in the extending direction of the word line 20 below both ends of the word line 20.

  As shown in FIG. 1, the charge storage layer 14 is formed by extending in the extending direction of the word line 20. For this reason, if the memory cell is further miniaturized and the interval between adjacent memory cells in the extending direction of the word line 20 is narrowed, the threshold voltage of the adjacent memory cell may be affected by the charge moving through the charge storage layer 14. Arise.

  The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device having a charge storage layer separated in a channel direction and a word line extending direction in order to miniaturize a memory cell. To do.

  The present invention includes a step of forming a groove extending in a semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate between the groove portions, and a step of forming a second insulating film so as to be embedded in the groove. A step of forming a word line extending across the second insulating film on the first insulating film and the second insulating film, and the first insulating film remaining under the center of the word line. Removing the first insulating film and the second insulating film having an etching rate faster than that of the first insulating film from between the word lines, and a region where the first insulating film is removed, and under the word line And a step of forming a charge storage layer on the semiconductor device. According to the present invention, the charge storage layer separated in the channel direction and the word line extending direction can be formed in a self-aligned manner on the second insulating film and the word line. Thereby, miniaturization of the memory cell can be achieved.

  In the above configuration, the step of forming the charge storage layer includes forming the charge storage layer so as to cover the word line, and forming the upper side surface of the word line and the region where the second insulating film is removed. And oxidizing the charged charge storage layer. According to this configuration, the charge storage layer separated in the channel direction and the word line extending direction can be formed in a self-aligned manner on the second insulating film and the word line.

  In the above configuration, the region where the second insulating film is removed may be larger than the region where the first insulating film is removed.

  In the above configuration, the step of forming the second insulating film is a step of forming the second insulating film such that the upper surface of the second insulating film protrudes from the upper surface of the first insulating film. be able to. According to this structure, it can suppress that the 2nd insulating film formed in the groove part is removed. Thereby, deterioration of device characteristics can be suppressed.

  In the above configuration, the step of forming the groove portion is a step of forming the groove portion using a mask layer formed on the semiconductor substrate, and the step of forming the second insulating film is the mask layer. A step of forming the second insulating film to be defined, and a step of reducing the width of the mask layer after the step of forming the groove and before the step of forming the second insulating film; can do. According to this structure, it can suppress more that the 2nd insulating film formed in the groove part is removed.

  In the above-described configuration, the step of removing the first insulating film and the second insulating film having an etching rate faster than that of the first insulating film is performed by using isotropic etching and etching is performed from the first insulating film and the first insulating film. The second insulating film having a high rate can be removed. According to this configuration, the first insulating film can be easily left below the center portion of the word line.

  In the above configuration, before the step of forming the charge storage layer, a step of oxidizing the word line and the semiconductor substrate to form a tunnel oxide film and a top oxide film in the region where the first insulating film is removed. It can be set as the structure which has.

  In the above structure, the first insulating film may be an oxide film formed by a thermal oxidation method, and the second insulating film may be an oxide film formed by a high density plasma CVD method. In the above configuration, the charge storage layer may be one of a nitride film and a polysilicon film. Furthermore, the above-described configuration may include a step of forming a source / drain region defined by the word line and the second insulating film in the semiconductor substrate.

  According to the present invention, the charge storage layer separated in the channel direction and the word line extending direction can be formed in a self-aligned manner on the second insulating film and the word line. Thereby, miniaturization of the memory cell can be achieved.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2A is a top view of the NAND flash memory according to the first embodiment, and FIGS. 2B to 2D are cross sections between BB and DD in FIG. 2A. FIG. In FIG. 2A, the source / drain regions 22 and the second insulating film 32 are shown through the silicon oxide film 34, and the charge storage layer 14 is seen through the word line 20. It is shown. 2A to 2D, a second insulating film 32 functioning as an element isolation insulating film is provided so as to extend into the semiconductor substrate 10. A word line 20 extending across the second insulating film 32 is provided above the semiconductor substrate 10. A silicon oxide film 34 is formed on the semiconductor substrate 10 and the second insulating film 32 around the word line 20 and between the word lines 20.

  2A and 2C, a first insulating film 30 functioning as a gate insulating film is provided on the semiconductor substrate 10 between the second insulating films 32 and below the center of the word line 20. ing. A tunnel oxide film 12, a charge storage layer 14, and a top oxide film 16 are sequentially provided so as to sandwich the first insulating film 30 below both ends of the word line 20, thereby forming an ONO film 18. A source / drain region 22 defined by the word line 20 and the second insulating film 32 is provided in the semiconductor substrate 10. Referring to FIG. 2B, a cavity 36 is formed between the second insulating film 32 and the word line 20 below both ends of the word line 20.

  Next, a method for manufacturing the flash memory according to the first embodiment will be described with reference to FIGS. 7A, FIG. 8A, and FIG. 9A are illustrated through the silicon oxide film 34 and the silicon nitride film 44. 3A and 3B, a first insulating film made of a silicon oxide film and having a thickness of about 27 nm is formed on a semiconductor substrate 10 which is a p-type silicon substrate by using a thermal oxidation method. 30 is formed. A mask layer 38 made of a silicon nitride film and having a width of about 60 nm is formed on the first insulating film 30 by using a CVD (chemical vapor deposition) method. The interval between the mask layers 38 is about 60 nm. Using the mask layer 38 as a mask, the first insulating film 30 and the semiconductor substrate 10 are etched by RIE (reactive ion etching). As a result, the groove 40 having a width of about 60 nm and a depth of about 200 nm is formed in the semiconductor substrate 10 by extending.

  Referring to FIGS. 4A and 4B, using mask layer 38 as a mask, second insulating film 32 made of a silicon oxide film is formed to be embedded in trench 40 using a high-density plasma CVD method. To do. Thereby, a second insulating film 32 extending into the semiconductor substrate 10 is formed. At this time, the second insulating film 32 is formed so that the upper surface of the second insulating film 32 protrudes from the upper surface of the first insulating film 30. Thereafter, the mask layer 38 is removed by wet etching using phosphoric acid.

  Referring to FIGS. 5A to 5D, a polysilicon film having a thickness of about 100 nm is formed on the second insulating film 32 and the first insulating film 30 by CVD. The polysilicon film is planarized using a CMP (Chemical Mechanical Polishing) method. A silicon nitride film (not shown) extending across the second insulating film 32 is formed on the polysilicon film. The polysilicon film is etched by RIE using the silicon nitride film as a mask. As a result, a word line 20 made of a polysilicon film is formed which extends across the second insulating film 32 and has a width of about 110 nm and a distance of about 70 nm.

  6A to 6D, the first insulating film is formed between the word lines 20 by using a wet etching method using hydrofluoric acid so that the first insulating film 30 remains below the center of the word line 20. 30 and the second insulating film 32 are etched. Thereby, in the region where the first insulating film 30 under both ends of the word line 20 is removed, the undercut portion 42a having a depth of about 30 nm from the side surface of the word line 20 is formed, and the second insulating film 32 is removed. The undercut portion 42b having a depth of about 40 nm from the side surface of the word line 20 is formed.

  Here, the reason why the undercut portion 42b, which is the region where the second insulating film 32 is removed, is larger than the undercut portion 42a, which is the region where the first insulating film 30 is removed, will be described. As shown in FIGS. 3A to 4B, the first insulating film 30 is formed by a thermal oxidation method, and the second insulating film 32 is formed by a high-density plasma CVD method. The silicon oxide film formed by the high-density plasma CVD method has a rougher film quality than the silicon oxide film formed by the thermal oxidation method. For this reason, the etching rate in wet etching with hydrofluoric acid is faster in the second insulating film 32 than in the first insulating film 30. Therefore, when wet etching with hydrofluoric acid is performed for the same time, the second insulating film 32 is etched more than the first insulating film 30, and the undercut portion 42b becomes larger than the undercut portion 42a.

  7A to 7D, the word line 20 and the semiconductor substrate 10 are oxidized using a thermal oxidation method. Thereby, the tunnel oxide film 12 and the top oxide film 16 having a thickness of about 10 nm made of a silicon oxide film are formed in the undercut portion 42a. A silicon oxide film 34 is formed around the word lines 20 and on the surface of the semiconductor substrate 10 between the word lines 20.

  Referring to FIGS. 8A to 8D, a silicon nitride film 44 is formed so as to cover the word line 20 by using LP-CVD (low pressure chemical vapor deposition). Since the LP-CVD method has excellent wraparound characteristics, the silicon nitride film 44 is also formed in the undercut portion 42 a and the undercut portion 42 b between the tunnel oxide film 12 and the top oxide film 16. Here, since the undercut portion 42b is larger than the undercut portion 42a, even when the undercut portion 42a is formed so as to be completely filled with the silicon nitride film 44, the undercut portion 42b is not completely filled but is a hollow portion. 36 is formed.

  9A to 9D, the silicon nitride film 44 is oxidized into a silicon oxide film 34 by using a radical oxidation method or a plasma oxidation method. Since the undercut portion 42a is completely filled with the silicon nitride film 44, the silicon nitride film 44 formed in the deep region of the undercut portion 42a hardly oxidizes and remains as the silicon nitride film 44 with a thickness. Becomes the charge storage layer 14 of about 7 nm. Since the undercut portion 42 b is not completely filled with the silicon nitride film 44 and the cavity portion 36 is formed, the silicon nitride film 44 is completely oxidized and becomes the silicon oxide film 34. Further, the silicon nitride film 44 formed on the upper side surface or the like of the word line 20 is also oxidized to become a silicon oxide film 34. Thereafter, arsenic ions are implanted into the semiconductor substrate 10 using the word line 20 as a mask. As a result, source / drain regions 22, which are n-type diffusion regions, defined by the word lines 20 and the second insulating film 32 are formed in the semiconductor substrate 10.

  According to the manufacturing method of Example 1, as shown in FIGS. 4A and 4B, the first insulating film 30 is formed on the semiconductor substrate 10 between the groove portions 40 formed in the semiconductor substrate 10, A second insulating film 32 is formed so as to be embedded in the groove 40. 6A to 6D, the first insulating film 30 is formed on the first insulating film 30 and the second insulating film 32 so that the first insulating film 30 remains below the center of the word line 20. The first insulating film 30 and the second insulating film 32 are removed from between the word lines 20. Thereafter, as shown in FIGS. 9A to 9D, the charge storage layer 14 is formed in the undercut portion 42a, which is a region where the first insulating film 30 is removed.

  As described above, the region where the second insulating film 32 is removed (undercut portion 42b) is larger than the region where the first insulating film 30 is removed (undercut portion 42a). Therefore, when the silicon nitride film 44 is formed so as to cover the word line 20 and the undercut portion 42a is completely filled with the silicon nitride film 44, as shown in FIGS. However, the undercut part 42b is not completely filled, and the cavity part 36 is formed. When the silicon nitride film 44 is oxidized in this state, as shown in FIGS. 9A to 9D, the silicon nitride film 44 formed in the undercut portion 42a remains as it is, but the undercut portion 42b. The silicon nitride film 44 thus formed is completely oxidized.

  As a result, the charge storage layer 14 (silicon nitride film 44) is formed in a self-aligned manner in the second insulating film 32 and the word line 20 in the region where the first insulating film 30 is removed (undercut portion 42a). be able to. That is, the charge storage layer 14 separated in the channel direction and the extending direction of the word line 20 can be formed in the region where the first insulating film 30 has been removed. As a result, the influence of CBD can be suppressed, and the influence of the memory cells adjacent in the extending direction of the word line 20 on the threshold voltage can be suppressed. For this reason, it is possible to miniaturize the memory cell.

  Further, as shown in FIGS. 4A and 4B, it is preferable that the upper surface of the second insulating film 32 is formed so as to protrude from the upper surface of the first insulating film 30. Thereby, in the step of removing the first insulating film 30 and the second insulating film 32 shown in FIGS. 6A to 6D, the second insulating film 32 formed in the trench 40 is removed. This can be suppressed. That is, it can suppress that a cavity part is formed in the groove part 40. FIG. If a hollow portion is formed in the groove 40, the device characteristics are deteriorated. Therefore, by forming the upper surface of the second insulating film 32 so as to protrude from the upper surface of the first insulating film 30, it is possible to suppress deterioration of device characteristics. In particular, it is preferable that the protruding amount of the upper surface of the second insulating film 32 is larger than the amount by which the second insulating film 32 is removed in the step of removing the first insulating film 30 and the second insulating film 32.

  Further, the step of removing the first insulating film 30 and the second insulating film 32 from between the word lines 20 shown in FIGS. 6A to 6D is performed by isotropic etching such as wet etching with hydrofluoric acid. Use is preferred. When isotropic etching is used, the first insulating film 30 and the second insulating film 32 are similarly removed from both ends of the word line 20. For this reason, the first insulating film 30 can easily remain below the center of the word line 20.

  Further, in Example 1, the first insulating film 30 is a silicon oxide film formed by a thermal oxidation method, and the second insulating film 32 is a silicon oxide film formed by a high-density plasma CVD method. However, it is not limited to this. If the etching rate of the second insulating film 32 is faster than the etching rate of the first insulating film 30 in the step of removing the first insulating film 30 and the second insulating film 32, it may be formed by another manufacturing method. Further, it may be made of other materials.

  Furthermore, although the case where the charge storage layer 14 is made of a silicon nitride film has been shown, the present invention is not limited to this, and it may be made of another material as long as it is a material capable of storing charges, such as a polysilicon film. In particular, when the charge storage layer 14 is made of a polysilicon film, after forming the polysilicon film so as to cover the word line 20, the polysilicon film formed on the upper side surface of the word line 20 and the undercut portion 42b is used. By performing the oxidation by the thermal oxidation method, the charge storage layer 14 made of a polysilicon film can be formed in the undercut portion 42a.

  The NAND flash memory manufacturing method according to the second embodiment is an example in the case of having a step of reducing the width of the mask layer before forming the second insulating film so as to be embedded in the groove. A method for manufacturing a NAND flash memory according to the second embodiment will be described with reference to FIGS.

  Referring to FIG. 10A, the first insulating film 30 is formed on the semiconductor substrate 10 by using a thermal oxidation method. A mask layer 38 is formed on the first insulating film 30 so as to extend. The first insulating film 30 and the semiconductor substrate 10 are etched using the mask layer 38 as a mask. Thereby, the groove part 40 extended to the semiconductor substrate 10 is formed.

  Referring to FIG. 10B, the widths of the mask layer 38 and the first insulating film 30 are narrowed. The width of the mask layer 38 can be reduced by using, for example, wet etching with phosphoric acid, and the width of the first insulating film 30 can be reduced by, for example, etching by the RIE method.

  Referring to FIG. 10C, the second insulating film 32 is formed so as to be embedded in the groove portion 40 by using the mask layer 38 as a mask and using a high-density plasma CVD method. Thereby, the second insulating film 32 extending in the semiconductor substrate 10 is formed. At this time, the second insulating film 32 is formed so that the upper surface of the second insulating film 32 protrudes from the upper surface of the first insulating film 30. Thereafter, the mask layer 38 is completely removed by wet etching with phosphoric acid. Subsequent steps are the same as those in the first embodiment, and are shown in FIGS.

  According to the manufacturing method of the second embodiment, as shown in FIGS. 10A to 10C, after forming the groove 40 in the semiconductor substrate 10 using the mask layer 38 as a mask, the width of the mask layer 38 and the like is increased. Squeeze. Thereafter, the second insulating film 32 is formed so as to be embedded in the groove 40 using the mask layer 38 as a mask. Thereby, the second insulating film 32 is defined by the mask layer 38, and the second insulating film 32 is formed so as to protrude from the semiconductor substrate 10 between the groove portions 40. That is, the width T1 of the upper surface of the second insulating film 32 is wider than the width T2 of the groove 40.

  The effect when the width T1 of the upper surface of the second insulating film 32 is wider than the width T2 of the groove 40 will be described with reference to FIGS. FIG. 11A is a perspective view before the first insulating film 30 and the second insulating film 32 are removed by wet etching with hydrofluoric acid. FIG. 11B is a perspective view after the first insulating film 30 and the second insulating film 32 are removed.

  Referring to FIGS. 11A and 11B, when the first insulating film 30 and the second insulating film 32 are removed by wet etching with hydrofluoric acid, the width T1 of the upper surface of the second insulating film 32 is the groove 40. If the width is larger than the width T2, even if the etching of the second insulating film 32 proceeds, it is possible to further suppress the etching to the second insulating film 32 formed in the groove 40. That is, it is possible to further suppress the formation of a cavity in the groove 40. Therefore, by making the width T1 of the upper surface of the second insulating film 32 wider than the width T2 of the groove 40, it is possible to further suppress the deterioration of device characteristics.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

FIG. 1 is a top view of a NAND flash memory having charge storage layers separated in the channel direction. FIG. 2A is a top view of the NAND flash memory according to the first embodiment, and FIGS. 2B to 2D are cross sections between BB and DD in FIG. 2A. FIG. FIG. 3A is a top view (part 1) illustrating the method for manufacturing the NAND flash memory according to the first embodiment, and FIG. 3B is a cross-sectional view taken along the line D-D in FIG. . 4A is a top view (part 2) illustrating the method for manufacturing the NAND flash memory according to the first embodiment, and FIG. 4B is a cross-sectional view taken along the line DD in FIG. 4A. . FIG. 5A is a top view (No. 3) illustrating the method for manufacturing the NAND flash memory according to the first embodiment, and FIGS. 5B to 5D are views taken along line BB in FIG. It is sectional drawing between DD from between. FIG. 6A is a top view (part 4) illustrating the method for manufacturing the NAND flash memory according to the first embodiment, and FIGS. 6B to 6D are cross-sectional views taken along line BB in FIG. It is sectional drawing between DD from between. FIG. 7A is a top view (No. 5) illustrating the method for manufacturing the NAND flash memory according to the first embodiment, and FIGS. 7B to 7D are views taken along line BB in FIG. It is sectional drawing between DD from between. FIG. 8A is a top view (No. 6) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 8B to 8D are views taken along line BB in FIG. It is sectional drawing between DD from between. FIG. 9A is a top view (No. 7) illustrating the method for manufacturing the NAND flash memory according to the first embodiment. FIGS. 9B to 9D are views taken along line BB in FIG. 9A. It is sectional drawing between DD from between. FIG. 10A to FIG. 10C are cross-sectional views illustrating a method for manufacturing a NAND flash memory according to the second embodiment. FIG. 11A and FIG. 11B are perspective views for explaining the effects of the NAND flash memory according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Tunnel oxide film 14 Charge storage layer 16 Top oxide film 18 ONO film 20 Word line 22 Source / drain region 24 Element isolation insulating film 30 1st insulating film 32 2nd insulating film 34 Silicon oxide film 36 Cavity part 38 Mask Layer 40 Groove portion 42a Undercut portion 42b Undercut portion 44 Silicon nitride film

Claims (9)

Forming a first insulating film on the semiconductor substrate ;
Forming one or more trenches in the semiconductor substrate from the first insulating film side ;
Depositing a second insulating film in the groove;
Forming a plurality of word lines on the first insulating film and the second insulating film;
1 of said one or more first portions and one or more first portions of the second insulating film of the first insulating film, and said first insulating layer under the plurality of word lines between the plurality of word lines and etching in more than three so as to remove the second portion, at the same time different etching rates and the second insulating film and the first insulating film,
One or more charge storage layers covering the plurality of word lines, and a region where the second portion of the first insulating film is removed and a region where the first portion of the second insulating film is removed Forming to be located at,
Oxidizing the charge storage layer formed on the top and side surfaces of each of the plurality of word lines and the region where the first portion of the second insulating film is removed;
A method for manufacturing a semiconductor device comprising: Wherein said region of said first portion is removed the second insulating film, the first said region is greater than said first portion and said second portion of the insulating film is removed, according to claim 1 Symbol mounting of the semiconductor device Manufacturing method. The second step of depositing an insulating film, said having a top projecting from the upper surface of the first insulating film comprises depositing the second insulating film, a method of manufacturing a semiconductor device according to claim 1 or 2 wherein. The step of forming the groove includes Rukoto using a mask layer formed on the semiconductor substrate,
Depositing the second insulating film includes defining the second insulating film using the mask layer ;
After the step of forming the groove, said prior to the second step of depositing an insulating film, Ru narrowing the width of the mask layer, a method of manufacturing a semiconductor device according to any one of claims 1 to 3. Said that the etching at different etch rates at the same time, the first insulating film and said second insulating film, with the same etchant isotropically includes etching, any one of claims 1 to 4 A method for manufacturing a semiconductor device according to one item. By oxidizing a pre-Symbol plurality of word lines and the semiconductor substrate, the first insulating region in the tunnel oxide film and the top other than the region in which the second portion and form a said charge storage layer in the region removed of the film further comprising, a method of manufacturing a semiconductor device according to any one of claims 1 to 5 forming the oxide film. The first insulating film is a first oxide film formed by thermal oxidation, the second insulation film is a second oxide film formed by high density plasma CVD method, any one of claims 1 to 6 A method for manufacturing a semiconductor device according to one item. The charge storage layer is formed of a nitride film or a polysilicon film, a method of manufacturing a semiconductor device according to any one of claims 1 7. In the semiconductor substrate, further comprising the step of forming the source and drain regions defined by the plurality of word lines and the second insulating film, a method of manufacturing a semiconductor device according to any one of claims 1 8 .

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