JP4056964B2 - Semiconductor device group, manufacturing method thereof, and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device group including a semiconductor device in which no flash memory is embedded and a semiconductor device in which flash memory cells are embedded, a manufacturing method thereof, and a semiconductor device included in the semiconductor device group.

  FPGAs (Field Programmable Gate Arrays) form a large field in the logic semiconductor market because of their programmable features. The FPGA is basically configured by spreading reconfigurable wiring or the like based on SRAM on a chip. Specific reconfigurable program data is stored in a flash memory (Flash EPROM) or the like which is a separate chip. Each time the power is turned on, the data stored in the flash memory is transmitted to the FPGA chip to perform programming. When such a configuration is adopted, problems such as a slow start-up at the time of power-on and unfavorable security such that program data can be taken out from the outside occur.

  In order to solve such a problem, an FPGA chip in which a flash memory capable of storing program data is mounted on the same chip is being developed. However, the manufacturing process of the FPGA chip in which the flash memory is mixedly mounted has a new problem that the number of processes increases by the number of processes for forming the flash memory as compared with a normal FPGA chip, and the manufacturing cost increases. Arise.

  From such a background, it is assumed that a flash memory embedded chip is used for an FPGA that requires high security, and a chip consisting only of a logic circuit is used for an FPGA that places more importance on the price of the chip than security. Although the two are different in chip configuration, the functions as FPGA are basically the same, and they are designed using the same design macro. Therefore, an effort is made to bring the characteristics of the transistor manufactured through the manufacturing process in which the flash memory is mixed and the transistor characteristics manufactured through the manufacturing process in which the flash memory is not mounted as close as possible.

Patent Document 1 discloses a manufacturing process for forming a well for forming a flash memory element, a well for forming a high voltage transistor, a floating gate for the flash memory element, and the like, and then forming a well for the transistor constituting the main logic circuit. It is disclosed. In this way, the manufacturing process peculiar to the flash memory is performed before the manufacturing process of the transistor that constitutes the logic circuit, so that the channel impurity distribution of the transistor that constitutes the logic circuit is almost equal to the case where the flash memory is not mixedly mounted. Can be equal.
JP 2001-196470 A JP-A-11-317458 JP 2000-269450 A JP 2000-315738 A JP 2001-015618 A JP 2001-068652 A JP 2003-007863 A "A 130nm Generation High Density ETOX Flash Memory Technology", IEDM 2001

  However, as described in Non-Patent Document 1, for example, when flash memories are mixedly mounted, the rounding amount at the upper end of the active region may be increased to a certain level or more in order to ensure the reliability of the tunnel insulating film. desirable. On the other hand, when the flash memory is not mixedly mounted, this is not necessary. If the roundness of the upper end of the active region is different, the characteristics of the narrow transistor having a particularly narrow channel width are different.

  In addition, when a flash memory is embedded, a high voltage transistor for controlling the flash memory element is necessary. Since a high voltage is applied to the high-voltage operation transistor, it is desirable to use a gate insulating film thicker than the gate insulating film of the main logic transistor. Therefore, when a flash memory is embedded, it is necessary to form more gate insulating films.

  A general method for forming a plurality of gate insulating films is described in Patent Document 2, for example. The method described in Patent Document 2 is to first grow a thick gate insulating film, remove the thick gate insulating film in the region where the thin gate insulating film is to be formed, and then grow the thin gate insulating film. Therefore, when the flash memory is embedded, the amount of recess of the element isolation film in the main logic transistor forming region having the thin gate insulating film is increased by removing the thick gate insulating film for the high voltage transistor. . When the recess amount of the element isolation film increases, the influence of the side surface of the element isolation film that occupies the narrow transistor increases, and the channel width dependence of the threshold voltage of the transistor changes.

  Thus, the characteristics required for element isolation differ greatly depending on whether the flash memory is mixed or not, and it is very difficult to make the transistor characteristics, particularly the narrow effect, the same.

  As one method for solving such a problem, it is conceivable to establish a manufacturing method in consideration of all the characteristics to be satisfied in cases where the flash memory is embedded and not used. However, this newly causes the following problems.

  First, it is necessary to simultaneously develop a process technology that incorporates flash memory and a process technology that does not incorporate flash memory. For example, the rounding amount at the upper end of the active region is optimized from the viewpoint of both the characteristics of the flash memory device and the characteristics of the main logic transistor. The process technology with embedded flash memory also needs to be optimized. This delays the development of process technology that does not incorporate flash memory.

  Secondly, in order to make the STI recess amount when the flash memory is not mixedly mounted the same as that when the flash memory is mixedly mounted, it is necessary to perform an extra insulating film removal process before forming the gate insulating film of the main logic transistor when not mixedly mounted. is there. Then, the surface of the semiconductor substrate in the gate insulating film formation region of the main logic transistor is excessively exposed to the insulating film removing chemical. When the surface of the semiconductor substrate is excessively exposed to the insulating film removing chemical, the surface of the semiconductor substrate is roughened or contamination from the chemical is increased. If a thick insulating film is grown in advance in the gate insulating film formation region of the main logic transistor, it can be prevented from being excessively exposed to a chemical solution, but an unnecessary process is added to the manufacture of a semiconductor device in which no flash memory is embedded. As a result, the manufacturing cost of a semiconductor device in which no flash memory is embedded is increased. Although it is conceivable to improve the purity of the chemical solution, the cost increases in order to increase the purity of the chemical solution, and eventually the manufacturing cost of the semiconductor device in which the flash memory is not mixed increases.

  As another solution, for example, as described in Patent Documents 3 to 6, the element isolation structure of the flash memory unit and the main logic unit is made different so as to match each characteristic, and for example, As described in Patent Document 7, it is conceivable to prevent the element isolation film from sinking. However, this method increases the number of manufacturing steps of the flash memory mixed semiconductor device and increases the manufacturing cost.

  An object of the present invention is to enable preferential development of a process technology that does not include a non-volatile memory, and a common design macro between a semiconductor device that does not include a non-volatile memory and a semiconductor device that includes a non-volatile memory. A semiconductor device group and a method for manufacturing the same, in which a high voltage transistor having a thick gate insulating film can be easily added with a high reliability of a tunnel insulating film in a semiconductor device in which a nonvolatile memory is embedded It is to provide.

  Another object of the present invention is to provide a semiconductor device included in the semiconductor device group.

Upper Symbol object is achieved by a semiconductor device including a first design macro and non-volatile memory having a first active region and the first isolation region formed on a semiconductor substrate, on the other semiconductor substrate Another semiconductor device having a formed second active region and a second element isolation region, including a second design macro having the same function as the first design macro, and not including a nonvolatile memory And a radius of curvature of the surface side edge when the first active region is seen in cross section is larger than the radius of curvature of the surface side edge when the second active region is seen in cross section The difference in height between the surface of the first active region and the surface of the first element isolation region is largely the height of the surface of the second active region and the surface of the second element isolation region. the difference is made reach by a semiconductor device being larger than the.

Another object of the present invention is to provide a semiconductor device including a first design macro having a first active region and a first element isolation region formed on a semiconductor substrate and not including a nonvolatile memory. Other semiconductors including a second design macro and a non-volatile memory having a second active region and a second element isolation region formed on a semiconductor substrate and having the same function as the first design macro A semiconductor device group is configured together with the device, and the radius of curvature of the surface side edge when the first active region is seen in cross section is larger than the radius of curvature of the surface side edge when the second active region is seen in cross section The difference in height between the surface of the first active region and the surface of the first element isolation region is a height difference between the surface of the second active region and the surface of the second element isolation region. Also achieved by a semiconductor device characterized by being smaller than the difference in thickness It is.

The above-described object, the first semiconductor device including a first design macro and non-volatile memory having a first active region and the first isolation region formed in the first semiconductor substrate, the A non-volatile memory including a second design macro having a second active region and a second element isolation region formed on two semiconductor substrates and having the same function as the first design macro a method of manufacturing a semiconductor device group comprising a second semiconductor device not including, the first semiconductor device, a first for forming the first isolation region in the first semiconductor substrate Forming the groove, oxidizing the first semiconductor substrate to round the upper end of the first groove, burying a first insulator in the first groove, Removing a part of the first insulator embedded in the first groove, Subduction region produced by the method of manufacturing a semiconductor device having a step of forming a second semiconductor device, wherein the second isolation region second to form a second semiconductor substrate Forming a groove; oxidizing the second semiconductor substrate to round an upper end of the second groove; embedding a second insulator in the second groove; A portion of the second insulator embedded in the second groove is removed, and a second subduction region is formed on the surface of the semiconductor device. In the step of rounding the upper end portion and the step of rounding the upper end portion of the second groove, the curvature radius of the upper end portion of the first groove is larger than the curvature radius of the upper end portion of the second groove. Increasing the size of the first subduction region and forming the first subduction region; and In the step of forming the second subduction region, the subtraction amount in the first subtraction region is set to be larger than the subtraction amount in the second subtraction region. This method can also be achieved.

  According to the present invention, a difference in STI recess amount between a semiconductor device in which a non-volatile memory is not mixed and a semiconductor device in which a non-volatile memory is embedded is taken into consideration, and a semiconductor device and a non-volatile memory that are not mixedly mounted based on this difference By controlling the radius of curvature at the upper end of the active region of the semiconductor device in which the memory is mixed, the variation in element characteristics due to the increase in the STI recess amount is offset by the increase in the radius of curvature at the upper end of the active layer. One common design macro can be applied to a semiconductor device in which no memory is embedded and a semiconductor device in which a nonvolatile memory is embedded.

  As a result, it is possible to preferentially develop a process technology that does not incorporate a nonvolatile memory. Further, the reliability of the tunnel insulating film of the nonvolatile memory can be improved by increasing the radius of curvature of the upper end portion of the active region. Further, by allowing an increase in the recess amount, it is possible to easily form a tunnel oxide film and a gate insulating film of a high voltage transistor.

  A semiconductor device group and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS.

  1 is a plan view showing the structure of the semiconductor device group according to the present embodiment, FIGS. 2 and 3 are schematic cross-sectional views showing the structure of the semiconductor device group according to the present embodiment, and FIG. 4 is the upper end of the active region related to the threshold voltage of the logic transistor. FIG. 5 to FIG. 21 are process cross-sectional views illustrating the method of manufacturing the semiconductor device group according to the present embodiment.

  First, the semiconductor device group according to the present embodiment will be explained with reference to FIGS. 1A is a conceptual diagram of a chip of a semiconductor device in which flash memory cells are not mixedly mounted. FIG. 1B is a conceptual diagram of a chip of a semiconductor device in which flash memory cells are embedded. FIG. FIG. 2B is a schematic cross-sectional view showing 11 types of transistors used in a semiconductor device in which flash memory cells are embedded, and FIG. 2B is a schematic cross-sectional view showing six types of transistors used in a semiconductor device that is not embedded.

  The semiconductor device group according to the present embodiment includes a semiconductor device in which flash memory cells are not mixedly mounted and a semiconductor device in which flash memory is embedded. The main feature is that the main logic circuit portion of the semiconductor device in which the flash memory is not mixed and the main logic circuit portion of the semiconductor device in which the flash memory is embedded are configured by a common design macro.

  The design macro includes information such as a predetermined circuit and pattern layout, and is a functional block for performing specific processing, and is also called an IP macro. By designing a circuit by combining design macros, the design cost can be reduced. Even if the circuit and layout of the design macro are the same, a predetermined operation may not be performed if the characteristics and resistance values of the included transistors are different. Therefore, when the same design macro is used in different semiconductor devices, it is necessary to make the characteristics of the transistors included in the design macro as close as possible.

  As shown in FIG. 1A, a semiconductor device 200 not including a flash memory includes a main logic circuit unit 202 and an input / output circuit unit 204. The input / output circuit unit 204 includes a PMOS unit 204P and an NMOS unit 204N.

  As shown in FIG. 2A, the semiconductor device in which the flash memory is not embedded includes an n-channel medium voltage transistor (N-MV) formed in the p-type well 82 and a p-type formed in the n-type well 84. A channel medium voltage transistor (P-MV), an n channel low voltage / high threshold transistor (N-LV High Vt) and an n channel low voltage / low threshold transistor (N-LV Low Vt) formed in the p-type well 86. ), And a p-channel low voltage / high threshold transistor (P-LV High Vt) and a p-channel low voltage / low threshold transistor (P-LV Low Vt) formed in the n-type well 88.

  The n-channel medium voltage transistor (N-MV) and the p-channel medium voltage transistor (P-MV) are transistors constituting the input / output circuit unit 204, and are transistors of 2.5V operation or 3.3V operation. The 2.5V operation transistor and the 3.3V operation transistor have different gate insulating film thickness, threshold voltage control conditions, and LDD conditions, but it is not necessary to mount both at the same time. Only one of them is mounted. Is.

  n-channel low voltage / high threshold transistor (N-LV High Vt), n-channel low voltage / low threshold transistor (N-LV Low Vt), p-channel low voltage / high threshold transistor (P-LV High Vt), The p-channel low voltage / low threshold transistor (P-LV Low Vt) is a transistor constituting the main logic circuit unit 202. For these transistors, an ultra-thin gate insulating film is used to improve the performance of the main logic circuit section 202.

  As shown in FIG. 1B, a semiconductor device 300 in which flash memory is embedded includes a flash memory cell unit 306 in addition to a main logic circuit unit 302 and an input / output circuit unit 304 similar to those of a semiconductor device in which flash memory is not embedded. And a flash memory cell control circuit unit 308. The flash memory cell control circuit unit 308 includes a PMOS unit 308P and an NMOS unit 308N.

  In addition to six types of transistors included in a semiconductor device in which a flash memory is not embedded, a semiconductor device in which a flash memory is embedded is a flash memory cell (Flash cell) formed in a p-type well 78 in an n-type well 90, n A channel high voltage / low threshold transistor (N-HV Low Vt) and an n channel high voltage / high threshold transistor (N-HV High Vt), and a p-channel high voltage / low threshold transistor (N-HV High Vt) formed in the n-type well 80 ( P-HV Low Vt) and a p-channel high voltage / high threshold transistor (P-HV High Vt).

  A flash memory cell (Flash cell) is a flash EPROM having a stack gate structure, and stores predetermined information as electric charges in a floating gate. The thickness of the tunnel oxide film is independently determined according to the charge retention characteristics, the oxide film lifetime, and the like.

  n-channel high voltage / low threshold transistor (N-HV Low Vt), n-channel high voltage / high threshold transistor (N-HV High Vt), p-channel high voltage / low threshold transistor (P-HV Low Vt), The p-channel high-voltage / high-threshold transistor (P-HV High Vt) is a transistor constituting the flash memory cell control circuit unit 308. When the flash memory cell is read, the voltage is 5V, and when writing / erasing is less than 10V. A high voltage transistor to which a voltage is applied. Since the flash memory cell control circuit unit 308 requires such a large voltage, the gate insulating film is also thick.

  As described above, the semiconductor device in which the flash memory is not mixed and the semiconductor device in which the flash memory is mixed are greatly different in the type of the transistor, and the semiconductor device in which the flash memory is simply mounted in the manufacturing process of the semiconductor device in which the flash memory is not mounted. Only by adding a specific process, the main logic circuit portion of the semiconductor device in which the flash memory is embedded and the main logic circuit portion of the semiconductor device in which the flash memory is not embedded cannot be configured by a common design macro.

  Therefore, in the semiconductor device group according to the present embodiment, the characteristics of the transistors constituting the main logic circuit unit 202 of the semiconductor device in which the flash memory is not mixedly mounted and the characteristics of the transistors forming the main logic circuit unit 302 of the semiconductor device in which the flash memory is mixedly mounted. In order to make it possible to apply a common design macro while minimizing the difference from the characteristics, the formation conditions of the element isolation film are appropriately controlled.

  Specifically, with respect to the element isolation film 22 formed in the silicon substrate 10 by the STI method, in a semiconductor device in which no flash memory is embedded, the curvature radius of the upper end of the active region is about 10 to 20 nm and the STI recess amount is 10 to 40 nm. (See FIG. 3A), in the semiconductor device in which the flash memory is embedded, the radius of curvature of the upper end of the active region is about 30 to 60 nm, the STI recess amount is 40 to 80 nm, and the flash memory cell is The value is set to be larger than that of a semiconductor device that is not mixedly mounted (see FIG. 3B). Here, the radius of curvature of the upper end of the active region is the radius of curvature of the surface side edge when the active region is viewed in cross section, and the STI recess amount (or sink amount) is the surface of the active region and the element isolation region. It is a physical quantity that represents the difference in height from the surface (see FIG. 3B).

  FIG. 4 shows a case where a normal STI formation condition of a logic semiconductor device in which no flash memory is mixedly mounted is set as a standard condition (indicated by a circle in the figure), and the amount of recess (sinking) of the STI buried oxide film is increased. The graph shows the dependence of the threshold voltage of the logic transistor on the channel width when the radius of curvature at the upper end of the active region is increased (marked with ■ in the figure).

  As shown in the figure, when the STI recess amount is increased, the so-called reverse narrow channel effect, in which the threshold voltage is greatly reduced as the channel width decreases, becomes significant. On the other hand, when the radius of curvature at the upper end of the active region is increased, a so-called narrow channel effect in which the threshold voltage increases as the channel width decreases becomes significant. Therefore, if the radius of curvature of the upper end of the active region is increased and the STI recess amount is increased, the two cancel each other, and the channel width dependence close to the standard condition can be obtained.

  That is, by making the curvature radius and the STI recess amount at the upper end of the active region in a semiconductor device mixed with a flash memory larger than that in a semiconductor device not embedded with a flash memory, the transistor characteristics of both semiconductor devices are made very close. be able to.

  Moreover, increasing the radius of curvature of the upper end of the active region also has the effect of improving the reliability of the tunnel insulating film of the flash memory cell, as described in Non-Patent Document 1, for example. Further, if an increase in the recess amount is allowed, it becomes easy to additionally form a tunnel oxide film and a gate insulating film of a high voltage transistor.

  Therefore, by appropriately controlling the radius of curvature and the STI recess amount at the upper end of the active region, the transistor characteristics are identical, the reliability of the tunnel insulating film, the addition of a thick gate insulating film, and the priority of the process technology that does not incorporate the flash memory. Development, can be achieved.

  Next, the method for fabricating the semiconductor device group according to the present embodiment will be explained with reference to FIGS.

  5 is a process cross-sectional view illustrating a method for manufacturing an element isolation film in a semiconductor device in which a flash memory is not mounted, FIG. 6 is a process cross-sectional view illustrating a method for manufacturing an element isolation film in a semiconductor device in which a flash memory is mounted. FIG. 21 to FIG. 21 are process cross-sectional views generally showing the manufacturing method of both semiconductor devices.

In the following description, when expressed as an n-channel transistor, an n-channel high voltage / high threshold transistor (N-HV High Vt), an n-channel high voltage / low threshold transistor (N-HV Low Vt), an n-channel medium voltage When a transistor (N-MV), an n-channel low voltage / high threshold transistor (N-LV High Vt), and an n-channel low voltage / low threshold transistor (N-LV Low Vt) are included, and expressed as a p-channel transistor P-channel high voltage / high threshold transistor (P-HV High Vt), p-channel high voltage / low threshold transistor (P-HV Low Vt), p-channel medium voltage transistor (P-MV), p-channel low voltage / High threshold transistor (P-LV High Vt) and p-channel low voltage / low It is intended to include the value transistor (P-LV Low Vt).

  Further, when expressed as a high voltage transistor, an n channel high voltage / low threshold transistor (N-HV Low Vt), an n channel high voltage / high threshold transistor (N-HV High Vt), a p channel high voltage / low threshold Transistor (P-HV Low Vt) and p-channel high voltage / high threshold transistor (P-HV High Vt) are included, and when expressed as a medium voltage transistor, n channel medium voltage transistor (N-MV) and p channel When including a medium voltage transistor (P-MV) and expressed as a low voltage transistor, an n channel low voltage / high threshold transistor (N-LV High Vt), an n channel low voltage / low threshold transistor (N-LV Low) Vt), p-channel low voltage / high threshold transistor (P-LV High Vt) It is intended to include fine p-channel low voltage and low threshold voltage transistor (P-LV Low Vt).

When expressed as an n-channel high voltage transistor, it includes an n-channel high voltage / low threshold transistor (N-HV Low Vt) and an n-channel high voltage / high threshold transistor (N-HV High Vt), and a p-channel When expressed as a high voltage transistor, a p-channel high voltage / low threshold transistor (P-HV Low Vt) and a p-channel high voltage / high threshold transistor (P-HV High Vt) are included, When expressed, it is assumed to include an n-channel low voltage / high threshold transistor (N-LV High Vt) and an n-channel low voltage / low threshold transistor (N-LV Low Vt), and when expressed as a p-channel low voltage transistor. , P-channel low voltage / high threshold transistor (P-LV High Vt) and a p-channel low voltage / low threshold transistor (P-LV Low Vt).

  First, the silicon substrate 10 is thermally oxidized to grow a silicon oxide film 12 having a thickness of 10 nm, for example.

  Next, a silicon nitride film 14 of, eg, a 100 nm-thickness is grown on the silicon oxide film 12 by, eg, CVD.

  Next, the silicon nitride film 14, the silicon oxide film 12, and the silicon substrate 10 are sequentially etched by lithography and dry etching to form a groove 16 having a depth of, for example, 300 nm in the silicon substrate 10 (FIG. 5A). 6 (a)).

  Next, the silicon substrate 10 is thermally oxidized to form a silicon oxide film 18 on the inner surface of the groove. This thermal oxidation is performed under different conditions as follows between a semiconductor device in which no flash memory is embedded and a semiconductor device in which a flash memory is embedded.

  In a semiconductor device in which a flash memory is not mounted, thermal oxidation is performed at a temperature of, for example, 850 ° C., and a silicon oxide film 18 having a thickness of, eg, about 10 nm is grown. When thermal oxidation is performed under these conditions, the final radius of curvature of the upper end of the active region is about 10 to 30 nm (FIG. 5B).

  In a semiconductor device incorporating a flash memory, thermal oxidation is performed at a temperature of 1100 ° C., for example, to grow a silicon oxide film 18 having a thickness of, for example, about 40 nm. The thicker the silicon oxide film 18 is, and the higher the oxidation temperature is, the more rounding the upper end of the active region is. When thermal oxidation is performed under these conditions, the final radius of curvature of the upper end of the active region is about 40 to 60 nm (FIG. 6B).

  Next, a silicon oxide film 20 of, eg, a 550 nm-thickness is grown by, eg, high density plasma CVD.

  Next, the silicon oxide film 20 is planarized by CMP until the silicon nitride film 14 is exposed, and an element isolation film 22 made of the silicon oxide films 18 and 20 is formed by being buried in the trench 16 (FIG. 5C). FIG. 6 (c)).

  After forming the element isolation film 22 in this way, on the active region defined by the element isolation film 22, in the case of a semiconductor device in which flash memory is not mixedly mounted, there are six types of transistors, and the semiconductor device in which flash memory is mixedly mounted. In this case, 11 types of transistors are formed.

  In the following description, the manufacturing method of the semiconductor device group according to the present embodiment will be described along the manufacturing process of the semiconductor device in which the flash memory is embedded. In the manufacturing process of the semiconductor device in which the flash memory is not mixedly mounted, only unnecessary steps are omitted from the manufacturing process of the semiconductor device in which the flash memory is embedded. Therefore, by explaining that fact, it will be described with reference to the sectional view again. I won't do that.

  First, an active region defined by the element isolation film 22 is formed on the silicon substrate 10 by the above-described manufacturing method (FIG. 7A).

  In the figure, the active region defined by the element isolation film 22 is, in order from the left side, a flash memory cell (Flash cell) formation region, an n-channel high voltage / low threshold transistor (N-HV Low Vt) formation region, n Channel high voltage / high threshold transistor (N-HV High Vt) formation region, p channel high voltage / low threshold transistor (P-HV Low Vt) formation region, p channel high voltage / high threshold transistor (P-HV High Vt) Formation region, n-channel medium voltage transistor (N-MV) formation region, p-channel medium voltage transistor (P-MV) formation region, n-channel low voltage / high threshold transistor (N-LV High Vt) formation region, n-channel low Voltage / low threshold transistor (N-LV Low Vt) formation region, p-channel low voltage It denotes the high threshold transistor (P-LV High Vt) forming region and the p-channel low voltage and low threshold voltage transistor (P-LV Low Vt) forming area.

  Next, after removing the silicon nitride film 14 by phosphoric acid and the silicon oxide film 12 by hydrofluoric acid aqueous solution, the silicon substrate 10 is thermally oxidized to grow a silicon oxide film 24 as a sacrificial oxide film having a thickness of 10 nm, for example. .

  Next, a photoresist film 26 is formed by exposing the flash memory cell (Flash cell) formation region and the n-channel high voltage transistor (N-HV High Vt, P-HV Low Vt) formation region by photolithography and covering the other regions. Form.

Next, ion implantation is performed using the photoresist film 26 as a mask, and n-type buried impurities are formed in the flash memory cell (Flash cell) formation region and the n-channel high voltage transistor (N-HV High Vt, N -HV Low Vt) formation region. Layer 28 and p-type well impurity layers 30 and 32 are formed (FIG. 7B). The n-type buried impurity layer 28 is formed, for example, by implanting phosphorus (P ⁺ ) ions under the conditions of an acceleration energy of 2 MeV and a dose of 2 × 10 ¹³ cm ⁻² . The p-type well impurity layer 30 is formed, for example, by implanting boron (B ⁺ ) ions under the conditions of an acceleration energy of 400 keV and a dose of 1.5 × 10 ¹³ cm ⁻² . The p-type well impurity layer 32 is formed, for example, by implanting boron ions under the conditions of an acceleration energy of 100 keV and a dose of 2 × 10 ¹² cm ⁻² .

  Next, the photoresist film 26 is removed by, for example, ashing.

  Next, a photoresist film 34 that exposes the flash memory cell formation region and covers other regions is formed by photolithography.

Next, ion implantation is performed using the photoresist film 34 as a mask to form a threshold voltage control impurity layer 36 in a flash memory cell formation region (FIG. 8A). The threshold voltage control impurity layer 36 is formed, for example, by implanting boron ions under conditions of an acceleration energy of 40 keV and a dose of 6 × 10 ¹³ cm ⁻² .

  Next, the photoresist film 34 is removed by, for example, ashing.

  Next, the silicon oxide film 24 as a sacrificial oxide film is removed with a hydrofluoric acid aqueous solution.

  Next, for example, thermal oxidation is performed at a temperature of 900 to 1050 ° C. for 30 minutes to form a tunnel oxide film 38 having a thickness of 10 nm on the active region (FIG. 8B).

  Next, a polysilicon film of, eg, a 90 nm-thickness is grown on the tunnel oxide film 38 by, eg, CVD.

  Next, the polysilicon film is patterned by photolithography and dry etching, and the floating gate 40 made of the polysilicon film is formed in the flash memory cell (Flash cell) formation region.

  Next, a silicon oxide film having a thickness of, for example, 5 nm and a silicon nitride film having a thickness of, for example, 10 nm are grown on the tunnel oxide film 38 on which the floating gate 40 is formed by, for example, CVD, and then the surface of the silicon nitride film is grown at 950 ° C. Is thermally oxidized for 90 minutes to grow a silicon oxide film having a thickness of about 30 nm. Thus, an ONO film 42 having a silicon oxide film / silicon nitride film / silicon oxide film structure is formed (FIG. 9A). By the heat treatment in the process of forming the ONO film 42, the well impurities are diffused by about 0.1 to 0.2 μm or more, and the impurity distribution becomes broad.

  As described above, in the method of manufacturing the semiconductor device group according to the present embodiment, the intermediate voltage transistor and the low voltage transistor are formed by the heat treatment process peculiar to the flash memory cell such as the tunnel oxide film 38, the floating gate 40, the ONO film 42, and the like. This is performed before the formation of the p-type wells 82 and 86 and the n-type wells 84 and 88. Therefore, it is possible to prevent the heat treatment process peculiar to the semiconductor device embedded with the flash memory from affecting the impurity profiles of the intermediate voltage transistor formation region and the low voltage transistor formation region.

  Note that the steps shown in FIGS. 7B to 9A described above are steps specific to a semiconductor device in which flash memory is embedded, and these steps are omitted in a semiconductor device in which flash memory is not embedded.

  Next, an n-channel high voltage / high threshold transistor (N-HV High Vt) formation region, an n-channel medium voltage transistor (N-MV) formation region, and an n-channel low voltage transistor (N-LV High Vt, N) are formed by photolithography. -LV Low Vt) A photoresist film 44 that exposes the formation region and covers other regions is formed.

Next, ion implantation is performed using the photoresist film 44 as a mask to form an n-channel high-voltage / high-threshold transistor (N-HV High Vt) formation region, an n-channel medium voltage transistor (N-MV) formation region, and an n-channel low-voltage transistor. In the (N-LV High Vt, N-LV Low Vt) formation region, p-type well impurity layers 46 and 48 are formed (FIG. 9B). The p-type well impurity layer 46 is formed, for example, by implanting boron ions under conditions of an acceleration energy of 100 keV and a dose of 6 × 10 ¹² cm ⁻² . The p-type well impurity layer 48 is formed, for example, by implanting boron ions under the conditions of an acceleration energy of 400 keV and a dose of 1.4 × 10 ¹³ cm ⁻² . The p-type well impurity layers 46 and 48 maintain a steep distribution without being subjected to the heat treatment in the above-described ONO film formation process, and suppress punch-through between the n-channel source / drain and the n-type well 90. Has the effect of

  Next, the photoresist film 44 is removed by, for example, ashing.

  Next, a p-channel high voltage transistor (P-HV Low Vt, P-HV High Vt) formation region, a p-channel medium voltage transistor (P-MV) formation region, a p-channel low voltage transistor (P-LV High) are formed by photolithography. Vt, P-LV Low Vt) formation region is exposed, and a photoresist film 50 covering the other region is formed.

Next, ion implantation is performed using the photoresist film 50 as a mask to form a p-channel high voltage transistor (P-HV Low Vt, P-HV High Vt) formation region, a p-channel medium voltage transistor (P-MV) formation region, and a p-channel. N-type well impurity layers 52 and 54 are formed in a low voltage transistor (P-LV High Vt, P-LV Low Vt) formation region (FIG. 10A). The n-type well impurity layer 52 is for controlling the threshold voltage of the p-channel high-voltage / low-threshold transistor, and the conditions can be adjusted as appropriate. For example, phosphorous ions are accelerated at an energy of 240 keV and a dose of 3 × 10. It is formed by ion implantation under the condition of ¹² cm ⁻² to obtain a threshold voltage of about −0.2V. When the flash memory is not mixedly mounted, the pure layer 52 for n-type well is formed, for example, by implanting phosphorus ions under the conditions of an acceleration energy of 240 keV and a dose of 8 × 10 ¹² cm ⁻² . The n-type well impurity layer 54 is formed, for example, by implanting phosphorus ions under the conditions of an acceleration energy of 600 keV and a dose of 1.5 × 10 ¹³ cm ⁻² .

  Next, the photoresist film 50 is removed by, for example, ashing.

  Next, a p-channel high voltage / high threshold transistor (P-HV High Vt) formation region, a p-channel medium voltage transistor (P-MV) formation region, a p-channel low voltage transistor (P-LV High Vt, P) are formed by photolithography. -LV Low Vt) A photoresist film 56 that exposes the formation region and covers other regions is formed.

Next, ion implantation is performed using the photoresist film 56 as a mask, a threshold voltage control impurity diffusion layer 58 is formed in a p-channel high voltage / high threshold transistor (P-HV High Vt) formation region, and a p-channel medium voltage transistor (P− The channel stop layer 60 is formed in the MV) formation region and the p-channel low voltage transistor (P-LV High Vt, P-LV Low Vt) formation region (FIG. 10B). The threshold voltage control impurity layer 58 and the channel stop layer 60 are formed, for example, by implanting phosphorus ions under the conditions of an acceleration energy of 240 keV and a dose of 6.5 × 10 ¹² cm ⁻² . Get the threshold voltage. The n-type well has a steep distribution with little lateral diffusion, and punch-through between the n-channel source / drain and the n-type well is also suppressed.

  Next, the photoresist film 56 is removed by, for example, ashing.

  Note that the process shown in FIG. 10B described above is a process peculiar to a semiconductor device in which a flash memory is embedded, and this process is omitted in a semiconductor device in which a flash memory is not embedded.

  Next, a photoresist film 62 that exposes the n-channel medium voltage transistor (N-MV) formation region and covers the other region is formed by photolithography.

Next, ion implantation is performed using the photoresist film 62 as a mask to form a threshold voltage control impurity layer 64 in the n-channel medium voltage transistor (N-MV) formation region (FIG. 11A). The threshold voltage control impurity layer 64 is formed, for example, by implanting boron ions under the conditions of an acceleration energy of 30 keV and a dose of 5 × 10 ¹² cm ⁻² , and a threshold voltage of about +0.3 to +0.4 V is formed. obtain.

  Next, the photoresist film 62 is removed by, for example, ashing.

  Next, a photoresist film 66 that exposes the p-channel medium voltage transistor (P-MV) formation region and covers other regions is formed by photolithography.

Next, ion implantation is performed using the photoresist film 66 as a mask, and a threshold voltage control impurity layer 68 is formed in the p-channel medium voltage transistor (P-MV) formation region (FIG. 11B). The threshold voltage control impurity layer 68 is formed, for example, by implanting arsenic (As ⁺ ) ions under the conditions of an acceleration energy of 150 keV and a dose of 3 × 10 ¹² cm ⁻² , and is about −0.3 to −0. Obtain a threshold voltage of .4V.

  Next, the photoresist film 66 is removed by, for example, ashing.

  Next, a photoresist film 70 is formed by exposing the n-channel low voltage / high threshold transistor (N-LV High Vt) formation region and covering the other region by photolithography.

Next, ion implantation is performed using the photoresist film 70 as a mask, and a threshold voltage control impurity layer 72 is formed in an n-channel low voltage / high threshold transistor (N-LV High Vt) formation region (FIG. 12A). The threshold voltage control impurity layer 72 is formed, for example, by implanting boron ions under the conditions of an acceleration energy of 10 keV and a dose of 5 × 10 ¹² cm ⁻² to obtain a threshold voltage of about + 0.2V.

  Next, the photoresist film 70 is removed by, for example, ashing.

  Next, a p-channel low voltage / high threshold transistor (P-LV High Vt) forming region is exposed by photolithography, and a photoresist film 74 covering the other region is formed.

Next, ion implantation is performed using the photoresist film 74 as a mask, and a threshold voltage control impurity layer 76 is formed in a p-channel low voltage / high threshold transistor (P-LV High Vt) formation region (FIG. 12B). The threshold voltage control impurity layer 76 is formed, for example, by implanting arsenic ions under conditions of an acceleration energy of 100 keV and a dose of 5 × 10 ¹² cm ⁻² to obtain a threshold voltage of about −0.2V.

  Next, the photoresist film 74 is removed by, for example, ashing.

  Thus, the p-type well impurity layers 30, 32, 46, 48 are formed in the flash memory cell (Flash cell) formation region and the n-channel high voltage transistor (N-HV Low Vt, N-HV High Vt) formation region. The p-type well 78 including the threshold voltage control impurity layer 36, the p-channel high voltage transistor (P-HV Low Vt, P-HV High Vt) formation region, the n-type well impurity layers 52 and 54, the threshold An n-type well 80 including a voltage control impurity layer 58 and a p-type well impurity layer 46 and 48 and a threshold voltage control impurity layer 64 formed in an n-channel medium voltage transistor (N-MV) formation region. The n-type well impurity layers 52 and 54 are formed in the p-type well 82 and the p-channel medium voltage transistor (P-MV) formation region. An n-type well 84 including a nell stop layer 60 and a threshold voltage control impurity layer 68, and an n-channel low voltage transistor (N-LV High Vt, N-LV Low Vt) formation region, and a p-type well impurity layer 46, 48, a p-type well 86 including a threshold voltage control impurity layer 72, and a p-channel low voltage transistor (P-LV High Vt, P-LV Low Vt) formation region, and an n-type well impurity layer 52. , 54, a channel stop layer 60, and an n-type well 88 including a threshold voltage control impurity layer 76. The n-type well 80 also functions as the n-type well 90 surrounding the p-type well 78 together with the n-type buried impurity layer 28. That is, the p-type well 78 is a double well formed in the n-type well 90 (see FIG. 13A).

  Next, a photoresist film 92 is formed by photolithography so as to cover the flash memory cell (Flash cell) formation region and expose other regions.

  Next, the ONO film 42 is etched by dry etching, for example, using the photoresist film 92 as a mask, and the ONO film 42 other than the flash memory cell (Flash cell) formation region is removed.

  Next, the tunnel oxide film 38 is etched by wet etching using, for example, a hydrofluoric acid aqueous solution using the photoresist film 92 as a mask, and the tunnel oxide film 38 other than the flash memory cell formation region is removed (FIG. 13 ( b)).

  Next, the photoresist film 92 is removed by, for example, ashing.

  Next, thermal oxidation is performed at a temperature of 850 ° C., for example, to form a 13 nm-thickness silicon oxide film 94 on the active region.

  Next, a flash memory cell formation region and a high-voltage transistor (N-HV Low Vt, N-HV High Vt, P-HV Low Vt, P-HV High Vt) formation region are covered by photolithography, and the like. A photoresist film 96 exposing the region is formed.

  Next, the silicon oxide film 94 is etched by wet etching using, for example, an aqueous solution of hydrofluoric acid, using the photoresist film 96 as a mask, so that an intermediate voltage transistor (N-MV, P-MV) formation region and a low voltage transistor (N-LV) are formed. The silicon oxide film 94 in the formation region of Low Vt, N-LV High Vt, P-LV Low Vt, and P-LV High Vt is removed (FIG. 14A).

  Next, the photoresist film 96 is removed by, for example, ashing.

  In the process shown in FIG. 14A described above, in a semiconductor device in which no flash memory is embedded, the silicon oxide film 24 as a sacrificial oxide film having a thickness of 10 nm formed after the element isolation film 12 is formed using a mask. It will be removed without.

  Subsequently, for example, thermal oxidation is performed at a temperature of 850 ° C., and a medium voltage transistor (N-MV, P-MV) formation region and a low voltage transistor (N-LV Low Vt, N-LV High Vt, P-LV Low Vt, A silicon oxide film 98 having a thickness of 4.5 nm is formed on the active region of the (P-LV High Vt) formation region. In this thermal oxidation process, the thickness of the silicon oxide film 94 also increases.

  Next, a flash memory cell formation region, a high voltage transistor (N-HV Low Vt, N-HV High Vt, P-HV Low Vt, P-HV High Vt) formation region and a medium voltage transistor are formed by photolithography. (N-MV, P-MV) Photoresist film that covers the formation region and exposes the formation region of the low-voltage transistors (N-LV Low Vt, N-LV High Vt, P-LV Low Vt, P-LV High Vt) 100 is formed.

  Next, the silicon oxide film 98 is etched using the photoresist film 100 as a mask, for example, by wet etching using a hydrofluoric acid aqueous solution, and low voltage transistors (N-LV Low Vt, N-LV High Vt, P-LV Low Vt, The silicon oxide film 98 in the P-LV High Vt formation region is removed (FIG. 14B).

  Next, the photoresist film 100 is removed by, for example, ashing.

  Next, for example, thermal oxidation is performed at a temperature of 850 ° C., and a film is formed on the active region of the low voltage transistor (N-LV Low Vt, N-LV High Vt, P-LV Low Vt, P-LV High Vt) formation region. A gate insulating film 102 made of a silicon oxide film having a thickness of 2.2 nm is formed. In this thermal oxidation process, the thicknesses of the silicon oxide films 94 and 98 are also increased, and high voltage transistors (N-HV Low Vt, N-HV High Vt, P-HV Low Vt, P-HV High Vt) are formed. A gate insulating film 104 having a total film thickness of 16 nm is formed in the region, and a gate insulating film 106 having a total film thickness of 5.5 nm is formed in the intermediate voltage transistor (N-MV, P-MV) formation region (FIG. 15). (A)).

  By performing the steps shown in FIGS. 14A to 15A, in the semiconductor device in which the flash memory is not mixed, when the silicon oxide film 24 is removed in the step shown in FIG. The element isolation film 12 is also etched when removing the silicon oxide film 98 in the step shown in FIG. Considering that the etching amount to be set is 1.5 times the film thickness to be etched and that the silicon oxide film formed by high-density plasma CVD has an etching rate 1.5 times that of the thermal oxide film, The amount of the element isolation film (STI recess amount) etched along with the removal of the films 24 and 98 is about 33 nm.

  On the other hand, in the semiconductor device in which the flash memory is embedded, when the silicon oxide film 24 is removed in the step shown in FIG. 8B, the tunnel oxide film 38 is removed in the step shown in FIG. When the silicon oxide film 94 is removed in the process shown in FIG. 14A, the element isolation film 12 is also etched when the silicon oxide film 98 is removed in the process shown in FIG. Therefore, the amount of the element isolation film (STI recess amount) etched along with the removal of the silicon oxide films 24, 94, 98 and the tunnel oxide film 38 is about 84 nm.

  Thereby, the element isolation film 22 has a curvature radius of 10 at the upper end of the active region in the formation region of the low voltage transistors (N-LV Low Vt, N-LV High Vt, P-LV Low Vt, P-LV High Vt). -30 nm, STI recess amount of about 30 nm, flash memory cell (Flash cell) formation region, the radius of curvature of the upper end of the active region is 40-60 nm, STI recess amount is about 80 nm, flash memory cell (Flash cell) formation region The radius of curvature on the active region and the STI recess amount are larger than the region where the low voltage transistors (N-LV Low Vt, N-LV High Vt, P-LV Low Vt, P-LV High Vt) are formed (FIG. 5). (D), FIG. 6 (d)).

  Next, a polysilicon film 108 having a thickness of 180 nm, for example, is grown by CVD.

  Next, a silicon nitride film 110 of, eg, a 30 nm-thickness is grown on the polysilicon film 108 by plasma CVD. The silicon nitride film 110 also serves as an antireflection and etching mask when patterning the underlying polysilicon film 108, and at the same time, when the side surface oxidation of the gate electrode of the flash cell described later is performed, It also has a role to protect.

  Next, the silicon nitride film 110, the polysilicon film 108, the ONO film 42, and the floating gate 40 in the flash memory cell formation region are patterned by photolithography and dry etching to form a flash memory cell (polysilicon film 108). A flash cell gate electrode 112 and the like are formed (FIG. 15B).

  Next, the side surface of the gate electrode 112 of the flash memory cell is thermally oxidized by about 10 nm, and ion implantation of the source / drain region 114 is performed.

  Next, the side surface of the gate electrode 112 is again thermally oxidized by about 10 nm.

  Next, after depositing a silicon nitride film by, for example, a thermal CVD method, the silicon nitride film and the silicon nitride film 110 are etched back, and a sidewall insulating film 116 made of a silicon nitride film is formed on the sidewall portion of the gate electrode 112.

  Next, a high voltage transistor (N-HV Low Vt, N-HV High Vt, P-HV Low Vt, P-HV High Vt) formation region, medium voltage transistor (N-MV, P-) is formed by photolithography and dry etching. The polysilicon film 108 in the MV) forming region and the low voltage transistor (N-LV Low Vt, N-LV High Vt, P-LV Low Vt, P-LV High Vt) forming region is patterned to be formed of the polysilicon film 108. A gate electrode 118 is formed (FIG. 16A).

  Note that the steps shown in FIGS. 15B and 16A described above are performed in a medium voltage transistor (N-MV, P-MV) formation region and a low voltage transistor (N−) in a semiconductor device in which no flash memory is embedded. Only the patterning of the silicon nitride film 110 and the polysilicon film 108 in the LV Low Vt, N-LV High Vt, P-LV Low Vt, and P-LV High Vt forming regions is performed.

  Next, a p-channel low voltage transistor (P-LV Low Vt, P-LV High Vt) formation region is exposed by photolithography, and a photoresist film 120 covering the other region is formed.

Next, ion implantation is performed using the photoresist film 120 as a mask, and source / drain regions of a p-channel low voltage / high threshold transistor (P-LV High Vt) and a p-channel low voltage / low threshold transistor (P-LV Low Vt). The extension 122 is formed (FIG. 16B). For example, the extension 122 has boron ions as an acceleration energy of 0.5 keV and a dose amount of 3.6 × 10 ¹⁴ cm ⁻² , and arsenic ions as an acceleration energy of 80 keV and a dose amount of 6.5 × 10 ¹² cm ^−2. As an extension with a pocket, it is formed by performing ion implantation from four directions inclined by 28 degrees from the substrate normal.

  Next, the photoresist film 120 is removed by, for example, ashing.

  Next, a photoresist film 124 is formed by exposing the n-channel low voltage transistor (N-LV Low Vt, N-LV High Vt) formation region and covering the other region by photolithography.

Next, ion implantation is performed using the photoresist film 124 as a mask, and source / drain regions of an n-channel low voltage / high threshold transistor (N-LV High Vt) and an n-channel low voltage / low threshold transistor (N-LV Low Vt). The extension 126 is formed (FIG. 17A). The extensions 126 include, for example, arsenic ions with an acceleration energy of 3 keV and a dose amount of 1.1 × 10 ¹⁵ cm ⁻² , and boron fluoride (BF ₂ ⁺ ) ions with an acceleration energy of 35 keV and a dose amount of 9.5 × each. 10 ¹² cm ⁻² is formed by performing ion implantation from four directions inclined by 28 degrees from the substrate normal line to form an extension with a pocket.

  Next, the photoresist film 124 is removed by, for example, ashing.

  Next, a photoresist film 128 that exposes the p-channel medium voltage transistor (P-MV) formation region and covers other regions is formed by photolithography.

Next, ion implantation is performed using the photoresist film 128 as a mask to form extensions 130 of the source / drain regions of the p-channel medium voltage transistor (P-MV) (FIG. 17B). The extension 130 is formed, for example, by implanting boron fluoride ions under the conditions of an acceleration energy of 10 keV and a dose of 7 × 10 ¹³ cm ⁻² .

  Next, the photoresist film 128 is removed by, for example, ashing.

  Next, a photoresist film 132 is formed by photolithography, exposing the n-channel medium voltage transistor (N-MV) formation region and covering the other region.

Next, ion implantation is performed using the photoresist film 132 as a mask to form extensions 134 of the source / drain regions of the n-channel medium voltage transistor (N-MV) (FIG. 18A). Extension 134, for example, arsenic ions, the acceleration energy 10 keV, at a dose of 2 × ¹⁰ 13 ^{cm -2,} for example, phosphorus ions, the acceleration energy 10 keV, at a dose of 3 × ¹⁰ 13 ^{cm -2,} respectively ion implantation It is formed by performing.

  Next, the photoresist film 132 is removed by, for example, ashing.

  Next, a photoresist film 136 is formed by exposing the p-channel high voltage transistor (P-HV Low Vt, P-HV High Vt) formation region and covering the other region by photolithography.

Next, ion implantation is performed using the photoresist film 136 as a mask, and source / drain regions of a p-channel high voltage / low threshold transistor (P-HV Low Vt) and a p-channel high voltage / high threshold transistor (P-HV High Vt). The extension 138 is formed (FIG. 18B). The extension 138 is formed, for example, by implanting boron fluoride ions under the conditions of an acceleration energy of 80 keV and a dose of 4.5 × 10 ¹³ cm ⁻² .

  Next, the photoresist film 136 is removed by, for example, ashing.

  Next, a photoresist film 140 is formed by exposing the n channel high voltage transistor (N-HV Low Vt, N-HV High Vt) formation region and covering the other region by photolithography.

Next, ion implantation is performed using the photoresist film 140 as a mask, and source / drain regions of an n-channel high voltage / low threshold transistor (N-HV Low Vt) and an n-channel high voltage / high threshold transistor (N-HV High Vt). The extension 142 is formed (FIG. 19A). The extension 142 is formed, for example, by implanting phosphorus ions under the conditions of an acceleration energy of 35 keV and a dose of 4 × 10 ¹³ cm ⁻² .

  Next, the photoresist film 140 is removed by, for example, ashing.

  Note that the steps shown in FIGS. 18B and 19A described above are steps specific to a semiconductor device in which flash memory is embedded, and this step is omitted in a semiconductor device in which flash memory is not embedded.

  Next, after depositing a silicon oxide film by, for example, thermal CVD, the silicon oxide film is etched back to form a sidewall insulating film 144 made of a silicon oxide film on the sidewall portions of the gate electrodes 86 and 92.

  Next, a flash memory cell forming region and an n-channel transistor (N-HV Low Vt, N-HV High Vt, N-MV, N-LV High Vt, N-LV Low Vt) forming region are formed by photolithography. A photoresist film 146 is formed so as to expose the other region.

Next, ion implantation is performed using the photoresist film 146 as a mask, and a flash memory cell (Flash cell) and an n-channel transistor (N-HV Low Vt, N-HV High Vt, N-MV, N-LV High Vt, N- A source / drain region 148 of (LV Low Vt) is formed (FIG. 19B). At the same time, by this ion implantation, the gate electrode 112 of the flash memory cell (Flash cell) and the n-channel transistors (N-HV Low Vt, N-HV High Vt, N-MV, N-LV High Vt, N-LV Low Vt) ) Gate electrode 118 is doped n-type. The source / drain region 148 is formed, for example, by implanting phosphorus ions under the conditions of an acceleration energy of 10 keV and a dose of 6 × 10 ¹⁵ cm ⁻² .

  Next, the photoresist film 146 is removed by, for example, ashing.

  Next, a p-channel transistor (P-HV Low Vt, P-HV High Vt, P-MV, P-LV High Vt, P-LV Low Vt) forming region is exposed by photolithography, and a photo that covers other regions is exposed. A resist film 150 is formed.

Next, ion implantation is performed using the photoresist film 150 as a mask, and source / drain of p-channel transistors (P-HV Low Vt, P-HV High Vt, P-MV, P-LV High Vt, P-LV Low Vt). Region 152 is formed (FIG. 20A). At the same time, by this ion implantation, the gate electrode 118 of the p-channel transistor (P-HV Low Vt, P-HV High Vt, P-MV, P-LV High Vt, P-LV Low Vt) is doped p-type. The The source / drain region 152 is formed, for example, by implanting boron ions under the conditions of an acceleration energy of 5 keV and a dose of 4 × 10 ¹⁵ cm ⁻² .

  Next, the photoresist film 150 is removed by, for example, ashing.

  Next, the gate electrodes 112 and 118 and the source / drain regions 148 and 152 are silicided by a known salicide process.

  Thus, eleven types of transistors are completed on the silicon substrate 10 in the case of a semiconductor device in which flash memory is embedded, and six types of transistors are completed in a semiconductor device in which flash memory is not embedded.

  Next, after growing an insulating film 154 on the silicon substrate 10 on which transistors and the like are formed, contact holes 156, electrode plugs 158, wirings 160, and the like are formed to complete the first metal wiring layer (FIG. 20 (FIG. 20). b)).

  Next, the growth of the insulating film and the formation of the wiring and the like are repeated, and the multilayer wiring layer 162 having a desired number of layers is formed on the insulating film 154.

  Next, after growing an insulating film 164 on the multilayer wiring layer 162, contact holes 166, electrode plugs 168, wiring 170, pad electrodes 172, and the like are formed, and the layers up to the uppermost metal wiring layer are completed.

  Next, a passivation film 174 is formed on the insulating film 164 on which the wiring layer 170, the pad electrode 172, and the like are formed, thereby completing the semiconductor device (FIG. 21).

  As described above, according to the present embodiment, the difference in the STI recess amount between the semiconductor device in which the flash memory is not mixed and the semiconductor device in which the flash memory is mixed is taken into consideration, and the semiconductor device in which the flash memory is not mounted based on this difference. By controlling the radius of curvature at the upper end of the active region of the semiconductor device in which the flash memory is embedded, the reverse narrow channel effect due to the increase in the STI recess amount is offset by the narrow channel effect due to the increase in the radius of curvature at the upper end of the active layer Therefore, a common design macro can be applied to the logic transistor included in the semiconductor device not including the flash memory and the logic transistor included in the semiconductor device including the flash memory.

  This enables preferential development of process technology that does not incorporate flash memory. Further, the reliability of the tunnel insulating film of the flash memory can be improved by increasing the radius of curvature of the upper end portion of the active region. Further, by allowing an increase in the recess amount, it is possible to easily form a tunnel oxide film and a gate insulating film of a high voltage transistor.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above-described embodiment, an example of an FPGA that does not include a flash memory and an FPGA that includes a flash memory has been described as an example. However, the present invention is not limited to an FPGA. The present invention is a semiconductor device group including a semiconductor device in which no flash memory is embedded and a semiconductor device in which a flash memory is embedded, and is widely applied to a semiconductor device group in which the identity of logic transistors of both semiconductor devices is important. Can do.

  In the above embodiment, the semiconductor device in which the flash memory is not mixed is configured by six types of transistors, and the semiconductor device in which the flash memory is embedded is configured by eleven types of transistors. However, the number of transistors is limited to this. is not.

  Further, the radius of curvature of the upper end of the active region and the STI recess amount are not limited to the values described in the above embodiment, and are appropriately determined according to the characteristics of the flash memory cell, the type and thickness of the gate insulating film, and the like. Can be set.

  As described above, the features of the present invention are summarized as follows.

(Appendix 1)
A first semiconductor device including a first design macro and a non-volatile memory; and a second semiconductor device including a second design macro having the same identity as the first design macro and not including a non-volatile memory; A semiconductor device group comprising:
The first design macro has a first active region and a first element isolation region formed on a first semiconductor substrate,
The second design macro has a second active region and a second element isolation region formed on a second semiconductor substrate,
The radius of curvature at the upper end of the cross section of the first active region is larger than the radius of curvature at the upper end of the cross section of the second active region,
The difference in height between the surface of the first active region and the surface of the first element isolation region is the difference in height between the surface of the second active region and the surface of the second element isolation region. A group of semiconductor devices characterized by being larger than

(Appendix 2)
In the semiconductor device group according to attachment 1,
The radius of curvature of the first active region is different from a height difference between the surface of the first active region and the surface of the first element isolation region, and the surface of the second active region. The radius of curvature of the second active region is larger than the radius of curvature of the second active region so as to offset the difference in device characteristics caused by the difference in height between the second device isolation region and the surface. A group of semiconductor devices.

(Appendix 3)
In the method for manufacturing a semiconductor device group according to attachment 2,
The element characteristic is channel width dependence of a threshold voltage of a transistor. A method of manufacturing a semiconductor device group.

(Appendix 4)
In the semiconductor device group according to any one of appendices 1 to 3,
The first element isolation region has a groove formed in the first semiconductor substrate and an insulator embedded in the groove,
The second element isolation region includes a groove formed in the second semiconductor substrate and an insulator embedded in the groove.

(Appendix 5)
In the semiconductor device group according to any one of appendices 1 to 4,
The first semiconductor device is an FPGA including the nonvolatile memory,
The semiconductor device group, wherein the second semiconductor device is an FPGA not including a nonvolatile memory.

(Appendix 6)
In the semiconductor device group according to any one of appendices 1 to 5,
The first design macro and the second design macro constitute a main logic circuit unit. A group of semiconductor devices.

(Appendix 7)
A semiconductor device including a first design macro and a nonvolatile memory having a first active region and a first element isolation region formed on a semiconductor substrate,
A second active region formed on another semiconductor substrate; a second element isolation region; a second design macro having the same identity as the first design macro; and a non-volatile memory Configure the semiconductor device group together with other semiconductor devices not
The radius of curvature at the upper end of the cross section of the first active region is larger than the radius of curvature at the upper end of the cross section of the second active region;
The difference in height between the surface of the first active region and the surface of the first element isolation region is the difference in height between the surface of the second active region and the surface of the second element isolation region. A semiconductor device characterized by being larger.

(Appendix 8)
A semiconductor device that includes a first design macro having a first active region and a first element isolation region formed on a semiconductor substrate and does not include a nonvolatile memory,
Others including a second design macro having a second active region and a second element isolation region formed on another semiconductor substrate and having the same identity as the first design macro and a non-volatile memory A semiconductor device group is configured together with the semiconductor device,
The radius of curvature at the upper end of the cross section of the first active region is smaller than the radius of curvature at the upper end of the cross section of the second active region;
The difference in height between the surface of the first active region and the surface of the first element isolation region is the difference in height between the surface of the second active region and the surface of the second element isolation region. A semiconductor device characterized by being smaller than.

(Appendix 9)
A first semiconductor device including a first design macro and a non-volatile memory; and a second semiconductor device including a second design macro having the same identity as the first design macro and not including a non-volatile memory; A method for manufacturing a semiconductor device group including:
The first semiconductor device includes a step of forming a first groove in a first semiconductor substrate, a step of oxidizing the first semiconductor substrate to round an upper end portion of the first groove, A step of embedding a first insulator in one groove, and a step of removing a part of the first insulator buried in the first groove to form a first subsidence region on the surface Manufactured by a method for manufacturing a semiconductor device having
The second semiconductor device includes a step of forming a second groove in a second semiconductor substrate, a step of oxidizing the second semiconductor substrate to round an upper end portion of the second groove, A step of embedding a second insulator in the second groove, and a step of removing a part of the second insulator buried in the second groove to form a second subduction region on the surface Manufactured by a method for manufacturing a semiconductor device having
In the step of rounding the upper end portion of the first groove and the step of rounding the upper end portion of the second groove, the radius of curvature of the upper end portion of the first groove is equal to the upper end portion of the second groove. To be larger than the radius of curvature of
In the step of forming the first subduction region and the step of forming the second subduction region, the subtraction amount in the first subtraction region is greater than the subtraction amount in the second subduction region. A method for manufacturing a semiconductor device group, characterized by:

(Appendix 10)
In the method for manufacturing a semiconductor device group according to attachment 9,
The radius of curvature of the first groove offsets the difference in element characteristics caused by the difference in the amount of subsidence in the first subsidence region and the amount of subsidence in the second subsidence region. In addition, the radius of curvature of the second groove is larger than the curvature radius of the semiconductor device group.

(Appendix 11)
In the method for manufacturing a semiconductor device group according to attachment 10,
The element characteristic is channel width dependence of a threshold voltage of a transistor. A method of manufacturing a semiconductor device group.

(Appendix 12)
In the method for manufacturing a semiconductor device group according to any one of appendices 9 to 11,
The method for manufacturing a semiconductor device group, wherein an oxidation temperature in the step of rounding the upper end portion of the first groove is higher than an oxidation temperature in the step of rounding the upper end portion of the second groove.

It is a top view which shows the structure of the semiconductor device group by one Embodiment of this invention. It is a schematic sectional drawing (the 1) which shows the structure of the semiconductor device group by one Embodiment of this invention. It is a schematic sectional drawing (the 2) which shows the structure of the semiconductor device group by one Embodiment of this invention. It is a graph which shows the curvature radius and STI recess amount dependence of the active region upper end part regarding the threshold voltage of a logic transistor. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 5) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 6) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 7) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 8) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 9) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 10) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 11) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 12) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 13) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 14) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 15) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 16) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention. It is process sectional drawing (the 17) which shows the manufacturing method of the semiconductor device group by one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12, 18, 20, 24, 94, 98 ... Silicon oxide film 14, 110 ... Silicon nitride film 16 ... Groove 22 ... Element isolation films 26, 34, 44, 50, 56, 62, 66, 70, 74, 92, 96, 100, 120, 124, 128, 132, 136, 140, 146, 150 ... Photoresist film 28 ... n-type buried impurity layers 30, 32, 46, 48 ... p-type well impurity layer 36, 58, 64, 68, 72 ... threshold voltage control impurity layer 38 ... tunnel oxide film 40 ... floating gate 42 ... ONO film 52, 54 ... n-type well impurity layer 60 ... channel stop layer 78, 82, 86 ... p-type Well 80, 84, 88, 90 ... n-type well 102, 104, 106 ... gate insulating film 108 ... polysilicon film 112, 118 ... gate electrode 114, 48, 152 ... source / drain regions 116, 144 ... sidewall insulating films 122, 126, 130, 134, 138, 142 ... extensions 154, 164 ... insulating films 156, 166 ... contact holes 158, 168 ... electrode plugs 160, 170 ... Wiring layer 162... Multi-layer wiring layer 172... Pad electrode 174. Passivation film 200 and 300... Semiconductor device 202 and 302... Main logic circuit portion 204 and 304. ... PMOS section 306 ... Flash memory cell section 308 ... Flash memory cell control circuit section

Claims (4)

A semiconductor device including a first design macro and a nonvolatile memory having a first active region and a first element isolation region formed on a semiconductor substrate,
A second design macro having a second active region and a second element isolation region formed on another semiconductor substrate and having the same function as the first design macro; Configure a semiconductor device group together with other semiconductor devices not included,
The radius of curvature of the surface side edge when the first active region is seen in cross section is larger than the radius of curvature of the surface side edge when the second active region is seen in cross section,
The difference in height between the surface of the first active region and the surface of the first element isolation region is the difference in height between the surface of the second active region and the surface of the second element isolation region. A semiconductor device characterized by being larger. A semiconductor device that includes a first design macro having a first active region and a first element isolation region formed on a semiconductor substrate and does not include a nonvolatile memory,
Others including a second design macro and a non-volatile memory having a second active region and a second element isolation region formed on another semiconductor substrate and having the same function as the first design macro A semiconductor device group is configured together with the semiconductor device of
The radius of curvature of the surface side edge when viewing the first active region in cross section is smaller than the radius of curvature of the surface side edge when viewing the second active region in cross section,
The difference in height between the surface of the first active region and the surface of the first element isolation region is the difference in height between the surface of the second active region and the surface of the second element isolation region. A semiconductor device characterized by being smaller than. A first semiconductor device including a first design macro and a non-volatile memory having a first active region and a first element isolation region formed on the first semiconductor substrate; and on the second semiconductor substrate. A second design macro having a second active region and a second element isolation region formed, including a second design macro having the same function as the first design macro, and not including a non-volatile memory; A method for manufacturing a semiconductor device group including a semiconductor device,
The first semiconductor device includes: forming a first groove for forming the first element isolation region in the first semiconductor substrate; oxidizing the first semiconductor substrate; A step of rounding an upper end of one groove, a step of embedding a first insulator in the first groove, and removing a part of the first insulator embedded in the first groove. And manufacturing a semiconductor device having a step of forming a first subduction region on the surface,
The second semiconductor device includes a step of forming a second groove for forming the second element isolation region in the second semiconductor substrate, and an oxidation treatment of the second semiconductor substrate to form the second semiconductor substrate. A step of rounding an upper end portion of the second groove, a step of embedding a second insulator in the second groove, and a part of the second insulator embedded in the second groove are removed. And manufacturing a semiconductor device having a step of forming a second subduction region on the surface,
In the step of rounding the upper end portion of the first groove and the step of rounding the upper end portion of the second groove, the radius of curvature of the upper end portion of the first groove is equal to the upper end portion of the second groove. To be larger than the radius of curvature of
In the step of forming the first subduction region and the step of forming the second subduction region, the subtraction amount in the first subtraction region is greater than the subtraction amount in the second subduction region. A method for manufacturing a semiconductor device group, characterized by: In the manufacturing method of the semiconductor device group according to claim 3 ,
The method for manufacturing a semiconductor device group, wherein an oxidation temperature in the step of rounding the upper end portion of the first groove is higher than an oxidation temperature in the step of rounding the upper end portion of the second groove.

Images