JP5691412B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode having a stack structure in which a floating gate and a control gate are stacked and a manufacturing method thereof.

  As a rewritable nonvolatile memory, a semiconductor memory device having a stack gate structure represented by a flash EEPROM is known. The flash EEPROM is an important semiconductor device because of its convenience, and development of a chip with a larger scale storage capacity and a logic circuit is being actively carried out.

Japanese Patent Laid-Open No. 11-186414 JP 2003-031702 A

  As semiconductor devices are highly integrated and miniaturized, low voltage operation and low power consumption are required. For this reason, a structure and a manufacturing method capable of low voltage operation and low power consumption are also required for a nonvolatile memory having a stack structure gate electrode.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of realizing low voltage operation and low power consumption of a nonvolatile memory having a stack structure gate electrode.

  According to one aspect of the embodiment, a step of forming an element isolation insulating film for defining an element region on a semiconductor substrate, a step of forming a first conductive film on the element isolation insulating film, and the element region Forming a first insulating film; forming a second conductive film on the first insulating film and on the element isolation insulating film on which the first conductive film is formed; The second conductive film and the first conductive film are patterned, and a first portion formed by the second conductive film is located on the element region, and the first conductive film and the first conductive film are formed. A step of forming a floating gate in which a second portion formed by a laminated film of two conductive films is located on the element isolation insulating film; a step of forming a second insulating film on the floating gate; A controller extending in the first direction on the second insulating film. Forming a gate, and etching the second insulating film and the floating gate using the control gate as a mask, the second insulating film formed in a region other than the region where the control gate is formed, and the There is provided a method of manufacturing a semiconductor device including a step of removing a floating gate.

  According to the disclosed method for manufacturing a semiconductor device, the coupling ratio can be increased by increasing the capacitance of the capacitor formed between the floating gate and the control gate. As a result, the operating voltage can be lowered and the boosting time can be shortened, and the semiconductor device can be easily integrated and miniaturized.

FIG. 1 is a plan view showing the structure of the semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view (part 1) showing the structure of the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view (part 2) illustrating the structure of the semiconductor device according to the first embodiment. FIG. 4 is a schematic cross-sectional view showing an example of the structure of a semiconductor device manufactured using a flat STI process. FIG. 5 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 11 is a process cross-sectional view (No. 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 13 is a process cross-sectional view (No. 9) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 14 is a process cross-sectional view (No. 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 15 is a process cross-sectional view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 16 is a process cross-sectional view (No. 12) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 17 is a process cross-sectional view (No. 13) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 18 is a process cross-sectional view (No. 14) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 19 is a process cross-sectional view (No. 15) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 20 is a process cross-sectional view (No. 16) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 21 is a process cross-sectional view (No. 17) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 22 is a process cross-sectional view (No. 18) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 23 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 24 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 25 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment; FIG. 26 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment; FIG. 27 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 28 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a modification of the embodiment.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

  FIG. 1 is a plan view showing the structure of the semiconductor device according to the present embodiment. 2 and 3 are schematic cross-sectional views showing the structure of the semiconductor device according to the present embodiment. FIG. 4 is a schematic cross-sectional view showing an example of the structure of a semiconductor device manufactured using a flat STI process. 5 to 22 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  An element isolation insulating film 20 that defines an element region is formed on the main surface of the silicon substrate 10. In the silicon substrate 10, a P well 28, an N well 32 and an N type buried layer 34 provided so as to surround the P well 28 are formed.

  A floating gate 50 is formed on the element region defined by the element isolation insulating film 20 via the tunnel gate insulating film 36. A control gate 48 is formed on the floating gate 50 via an ONO film 42. N-type impurity layers 56 and 66 serving as source / drain regions are formed in the silicon substrate 10 on both sides of the control gate 48. Thus, a memory cell transistor having a stack structure gate electrode in which the floating gate 50 and the control gate 48 are stacked is formed on the element region.

  A plurality of such memory cell transistors are arranged in a matrix on the silicon substrate 10. Control gates 48 of memory cell transistors adjacent in the X direction are connected to each other to form a word line WL. In the element region between the word lines WL, a source region and a drain region of the memory cell transistor are alternately formed. The source regions of memory cell transistors adjacent in the X direction are connected to each other by an N-type impurity layer 56 (source line) extending in the X direction.

  An interlayer insulating film 72 is formed on the silicon substrate on which the memory cell transistors are formed. In the interlayer insulating film 72, a contact hole 74 reaching the drain region (N-type impurity layer 64) of the memory cell transistor is formed. A contact plug 76 is embedded in the contact hole 74. A bit line 78 extending in the Y direction and connected to the drain region of the memory cell transistor via the contact plug 90 is formed on the interlayer insulating film 80 in which the contact plug 90 is embedded. Thus, the drain regions of the memory cell transistors adjacent in the Y direction are connected to each other by the bit line 78.

  Here, in the semiconductor device according to the present embodiment, the floating gate 50 is formed of two layers of conductive films (silicon films 24 and 38) as shown in FIG. The silicon film 38 is formed over the entire region where the floating gate 50 is formed, and the silicon film 24 is formed at both ends in the X direction of the region where the floating gate 50 is formed. The silicon film 38 is formed on the silicon film 24 at both ends in the X direction of the floating gate 50. Thereby, the surface area of the floating gate 50 in contact with the ONO film 42 is increased, and the capacitance of the capacitor between the floating gate 50 and the control gate 48 formed via the ONO film 42 can be increased.

In a semiconductor device using a flat STI process, for example, as shown in FIG. 4, the floating gate 50 is formed of a single layer of conductive film. In this case, assuming that the thickness of the floating gate 50 is 100 nm, the width of the floating gate 50 in the X direction is 150 nm, and the width of the control gate 48 in the Y direction is 250 nm, the surface area of the floating gate 50 in contact with the ONO film 42 is the 87500nm ^2.

  Note that the flat STI process is a process of reducing the step between the active region and the element isolation region on the floating gate formation surface by etching the surface of the element isolation insulating film after forming the element isolation insulating film. It is.

On the other hand, in the semiconductor device of this embodiment shown in FIG. 3, in addition to the above parameters, assuming that the film thickness of the silicon film 24 is 100 nm and the surface step of the silicon film 38 is 100 nm, the floating gate 50 in contact with the ONO film 42. Has a surface area of 187500 nm ² .

  The capacitance of the capacitor between the floating gate 50 and the control gate 48 is proportional to the surface area of the floating gate 50 in contact with the ONO film 42. Therefore, in the semiconductor device of this embodiment shown in FIG. 3, the capacitance of the capacitor can be increased by about 2.1 times compared to the semiconductor device shown in FIG.

  Here, there is a coupling ratio as one parameter for evaluating the characteristics of the gate electrode of the stack structure. The coupling ratio is defined as CONO / (CTNOX + CONO), where CNOX is the capacitor capacity between the floating gate 50 and the silicon substrate 10, and CONO is the capacitor capacity between the floating gate 50 and the control gate 48. The coupling ratio greatly affects the write / erase operation of the memory cell transistor. That is, when the coupling ratio is small, a large operating voltage is required when data is written or erased by passing a current through the tunnel gate insulating film 36 by the Fowler-Nordheim tunnel phenomenon. Although it is conceivable to compensate for the reduction in the coupling ratio by circuit design, the element area of the booster circuit for boosting from the power supply voltage to the operating voltage increases, resulting in an increase in chip cost and further increase in thickness. It also causes a decrease in processing speed. As the semiconductor device is miniaturized and the voltage is reduced, the necessity for increasing the coupling ratio is further increased.

  According to the semiconductor device according to the present embodiment, the capacitance of the capacitor between the floating gate 50 and the control gate 48 can be increased, and thus the coupling ratio can be increased. This makes it possible to perform a write / erase operation with a lower operating voltage.

  In the semiconductor device according to the present embodiment, as shown in FIG. 3, the side surface of the lower silicon film 24 forming the floating gate 50 has an inversely tapered shape that protrudes outward as it approaches the silicon film 38 side. Yes. This is to prevent the influence of etching residues that may occur when the floating gate 50 is formed by separating the silicon films 24 and 38 in the Y direction.

  During the etching for separating the floating gate 50 in the Y direction, a stringer-like etching residue extending in the Y direction may be generated due to the shape of the floating gate 50 on the element isolation insulating film 20. is there. When such an etching residue is generated, the floating gates 50 adjacent in the Y direction are connected to each other by the etching residue, which may cause malfunction. By making the side surface of the silicon film 24 into an inversely tapered shape, it is possible to prevent the occurrence of stringer-like etching residues extending in the Y direction (see the manufacturing method described later).

  The flat STI process described above is an effective process as a stringer residue countermeasure, but the coupling ratio is significantly reduced.

  On the other hand, according to the semiconductor device of the present embodiment, both the generation of stringer residue and the increase of the coupling ratio can be realized simultaneously. As a result, the operating voltage can be lowered, the boosting time can be shortened, and the manufacturing cost can be reduced, and the semiconductor device can be highly integrated and miniaturized. Further, since the stringer residue can be reduced, the yield and reliability of the semiconductor device can be improved.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 5 to 15, each drawing (a) shows a process sectional view of the memory cell region, and each drawing (b) shows a process sectional view of the peripheral circuit region. 16 to 22 are process sectional views of the memory cell region.

  First, a silicon oxide film 12 having a thickness of, eg, about 50 nm is formed on the silicon substrate 10 by, eg, thermal oxidation.

  Next, a silicon nitride film 14 having a thickness of, eg, about 250 nm is formed on the silicon oxide film 12 by, eg, CVD.

  Next, a photoresist film (not shown) that exposes the element isolation region and covers the element region is formed on the silicon nitride film 14.

  Next, the silicon nitride film 14, the silicon oxide film 12 and the silicon substrate 10 are etched using this photoresist film as a mask to form a trench 16 having a depth of, for example, 600 nm in the element isolation region of the silicon substrate 10.

  Next, the photoresist film is removed by, for example, ashing (FIGS. 5A and 5B).

  Next, a liner film (not shown) of a silicon oxide film is formed on the inner wall of the trench 16 by, for example, a thermal oxidation method.

  Next, a silicon oxide film 18 of, eg, a 800 nm-thickness is deposited on the entire surface by, eg, CVD, and the trench 16 is filled with the silicon oxide film 18 (FIGS. 6A and 6B).

  Next, the silicon oxide film 18 is polished by CMP (Chemical Mechanical Polishing) until the silicon nitride film 14 is exposed, and the excess silicon oxide film 18 on the silicon nitride film 14 is removed. Thus, the element isolation insulating film (STI) 20 is formed by the silicon oxide film 18 buried in the trench 16 (FIGS. 7A and 7B).

  Next, a photoresist film 22 that exposes the memory cell region and covers the peripheral circuit region is formed by photolithography.

  Next, using the photoresist film 22 and the silicon nitride film 14 as a mask, wet etching using, for example, a hydrofluoric acid aqueous solution is performed to etch the surface portion of the element isolation insulating film 20. Thereby, the step between the element region and the element isolation region in the memory cell region is reduced (FIGS. 8A and 8B). This step is the same as a normal flat STI process.

  Next, the photoresist film 22 is removed by, for example, ashing.

Next, a silicon film 24 having a thickness of, for example, 100 nm and a phosphorus concentration of, for example, 1 × 10 ²³ cm ⁻³ is deposited on the entire surface by, eg, CVD (FIGS. 9A and 9B). The silicon film 24 may be a polysilicon film or an amorphous silicon film.

  It should be noted that the impurity concentration of the silicon film 24 is higher than the impurity concentration of the silicon film 38 to be formed in a later step, more preferably higher by one digit or more. This is because the etching rate of the silicon film 24 is made higher than the etching rate of the silicon film 38 when the silicon films 24 and 38 are etched.

  Next, the silicon film 24 is polished by CMP until the silicon nitride film 14 is exposed, and the excess silicon film 24 on the silicon nitride film 14 is removed. At this time, since the element isolation insulating film 20 in the peripheral circuit region has almost the same height as the silicon nitride film 14, all of the silicon film 24 in the peripheral circuit region is removed. On the other hand, since the surface of the element isolation insulating film 20 in the memory cell region is recessed from the surface of the silicon nitride film 14, the silicon film 24 on the element isolation insulating film 20 in the memory cell region remains without being removed. Thereby, the silicon film 24 can be selectively left on the element isolation insulating film 20 in the memory cell region (FIGS. 10A and 10B).

  Next, the silicon nitride film 14 and the silicon oxide film 12 are removed by wet etching, for example.

  Next, a silicon oxide film of, eg, a 20 nm-thickness is formed by thermal oxidation. Thereby, a sacrificial oxide film 26 of a silicon oxide film is formed on the element region (FIGS. 11A and 11B).

  Next, a predetermined well is formed in the high voltage transistor formation region in the memory cell region and the peripheral circuit region by photolithography and ion implantation.

For example, first, using a photoresist film (not shown) that exposes the memory cell region and the N-type high-voltage transistor formation region as a mask, for example, boron ions (B ⁺ ) are accelerated energy 450 keV and dose 1 × 10 ^13. Ion implantation is performed under the condition of cm ⁻² (TPW). Further, for example, boron ions are ion-implanted under the conditions of an acceleration energy of 10 keV and a dose of 4 × 10 ¹² cm ⁻² (NVT1). Further, for example, phosphorus ions (P +) are formed by ion implantation under the conditions of an acceleration energy of 2 MeV and a dose amount of 2 × 10 ¹³ cm ⁻² (BNW).

Next, for example, phosphorus ions are ion-implanted under the conditions of an acceleration energy of 600 keV and a dose of 4 × 10 ¹² cm ⁻² using a photoresist film (not shown) that exposes the P-type high-voltage transistor formation region as a mask (NW1 ). Further, for example, phosphorus ions are ion-implanted (PVT) under conditions of an acceleration energy of 50 keV and a dose of 4 × 10 ¹² cm ⁻² .

Next, using a photoresist film (not shown) that exposes the memory cell region as a mask, for example, boron ions are ion-implanted (CVT) under the conditions of an acceleration energy of 50 keV and a dose of 6 × 10 ¹³ cm ⁻² .

Next, for example, boron ions are ion-implanted under the conditions of an acceleration energy of 10 keV and a dose of 2 × 10 ¹² cm ⁻² using a photoresist film (not shown) exposing the N-type high-voltage transistor formation region as a mask ( NVT2).

  Next, for example, heat treatment is performed in a nitrogen atmosphere to activate the implanted impurities. As a result, a P well 28 including a channel impurity layer for threshold voltage control is formed in the memory cell region by the impurities of TPW, NTV1, and CVT ion implantation. Further, a P well 30 including a channel impurity layer for controlling the threshold voltage is formed in the N-type high voltage transistor formation region using impurities of TPW, NTV1, and NVT2 ion implantation. Further, an N well 32 including a channel impurity layer for threshold voltage control is formed in the P-type high voltage transistor formation region by NW1 and PVT ion implantation impurities. Also, a buried N-type layer 34 is formed below the P wells 28 and 30 by BNW ion implantation impurities. The P wells 28 and 30 are double wells surrounded by the N well 32 and the buried N-type layer 34, and are separated from other regions of the silicon substrate 10 (FIGS. 12A and 12B).

  Next, the sacrificial oxide film 26 is removed by, for example, wet etching using a hydrofluoric acid aqueous solution.

  Next, for example, heat treatment is performed in an oxidizing atmosphere, the surface of the silicon substrate 10 is thermally oxidized, and a silicon oxide film of, eg, a 10 nm-thickness is grown in the element region to form a gate insulating film 36 of a silicon oxide film.

Next, a silicon film 38 having a thickness of, for example, 100 nm and a phosphorus concentration of, for example, 1 × 10 ²² cm ⁻³ is deposited on the entire surface by, eg, CVD (FIGS. 13A and 13B). The silicon film 38 may be a polysilicon film or an amorphous silicon film.

  Next, the silicon film 38 in the peripheral circuit region is removed by photolithography, and a photoresist film 40 for patterning the silicon films 24 and 38 in the memory cell region into stripes extending in the Y direction is formed (FIG. 14). (A), (b)), FIG. 21 (a)).

  Next, the silicon films 38 and 24 are sequentially etched using the photoresist film 40 as a mask to remove the silicon film 38 in the peripheral circuit region, and the silicon films 24 and 38 in the memory cell region are formed in stripes extending in the Y direction. Patterning is performed (FIGS. 21B and 22A).

  At this time, since the impurity concentration contained in the silicon film 24 is about one digit higher than the impurity concentration contained in the silicon film 38, the etching rate of the silicon film 24 is higher than the etching rate of the silicon film 38. For this reason, when the etching conditions are set so that the etching surface of the silicon film 38 is vertical, the silicon film 24 is etched more than the vertical shape, and the etching surface becomes a reverse taper shape.

  Next, the photoresist film 40 is removed by, for example, ashing (FIGS. 15A, 15B, and 22B).

  The stripe-shaped silicon films 24 and 38 extending in the Y direction are divided in the X direction to form the floating gate 50 in a later process. However, for convenience of explanation in this specification, the stripe-shaped silicon films 24 and 38 extend in the Y direction. These silicon films 24 and 38 are sometimes called floating gates.

  Next, a 10 nm-thickness silicon oxide film is formed on the entire surface by, for example, a CVD method, a 10 nm-thickness silicon nitride film is formed by, for example, a CVD method, and a 10 nm-thickness silicon oxide film is sequentially formed by, for example, a thermal oxidation method. Thereby, an ONO film 42 having a silicon oxide film / silicon nitride film / silicon oxide film structure is formed.

  Next, the ONO film 42 and the tunnel gate insulating film 36 in the peripheral circuit region are selectively removed by etching using a photoresist film (not shown) that covers the memory cell region and exposes the peripheral circuit region as a mask.

  Next, a predetermined well (not shown) and a gate insulating film (not shown) are formed in the peripheral circuit region. Since the subsequent manufacturing process of the peripheral circuit transistor is the same as the normal manufacturing process, description thereof is omitted here.

Next, a silicon film 44 having a thickness of, for example, 200 nm and a phosphorus concentration of, for example, 5 × 10 ²⁰ cm ⁻³ is deposited on the entire surface by, eg, CVD. The silicon film 44 may be a polysilicon film or an amorphous silicon film.

  Next, a silicon nitride film 46 of, eg, a 100 nm-thickness is formed on the silicon film 44 by, eg, CVD (FIG. 16).

  Next, a photoresist film (not shown) is formed on the silicon nitride film 46 by photolithography so as to cover the peripheral circuit region and to have a control gate pattern in the memory cell region.

  Next, the silicon nitride film 46 and the silicon film 44 in the memory cell region are etched using this photoresist film as a mask. As a result, a control gate 48 made of the silicon film 44 whose upper surface is covered with the silicon nitride film 46 is formed in the memory cell region. The gate length of the control gate 48 is, for example, 0.25 μm.

  Next, using the photoresist film as a mask, the ONO film 42 and the silicon films 38 and 24 are further etched to divide the silicon films 38 and 24 in the Y direction. As a result, the floating gate 50 made of the silicon films 38 and 24 is formed under the control gate 48.

  At this time, since the side surface of the silicon film 24 has an inversely tapered shape, there is no problem that the silicon film 24 cannot be etched behind the ONO film 42 formed on the side surface of the silicon film 24. Further, in the step shown in FIG. 8, the surface portion of the element isolation insulating film 20 is etched to reduce the level difference between the element region and the element isolation region. Thereby, it is possible to prevent the occurrence of a stringer-like etching residue extending in the Y direction.

  Next, the photoresist film is removed by, for example, ashing.

Next, by photolithography and ion implantation, a P-type impurity layer 52 is formed in the source region of the memory cell transistor, and an N-type impurity layer 54 is formed in the source region of the memory cell transistor (FIG. 17). The P-type impurity diffusion layer 52 is formed, for example, by implanting boron ions under conditions of an acceleration energy of 50 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The N-type impurity diffusion layer 54 is formed, for example, by ion-implanting arsenic ions (As ⁺ ) under the conditions of an acceleration energy of 50 keV and a dose amount of 5 × 10 ¹⁴ cm ⁻² .

  Next, annealing is performed in an oxidizing atmosphere, for example, and a silicon oxide film (not shown) having a thickness of 1 nm, for example, is formed on the element region of the memory cell region and on the side walls of the control gate 48 and the floating gate 50.

  Next, by photolithography, a photoresist film that covers the peripheral circuit region and alternately exposes the regions between the control gates 48 in the memory cell region, that is, exposes a region that becomes a source line connecting the sources of the memory cell transistors (FIG. (Not shown).

  Next, the element isolation insulating film 20 in the source line formation region is etched using the photoresist film and the control gate 48 as a mask.

  Next, the photoresist film is removed by, for example, ashing.

Next, an N-type impurity layer 56 serving as a source line is formed in the source line formation region by photolithography and ion implantation. The N-type impurity layer is formed, for example, by ion-implanting arsenic ions (As ⁺ ) under conditions of an acceleration energy of 50 keV and a dose of 1 × 10 ¹⁶ cm ⁻² .

  Next, annealing is performed in, for example, an oxidizing atmosphere, and a silicon oxide film 58 of, eg, a 1 nm-thickness is formed on the side walls of the control gate 48 and the floating gate 50 on the element region of the memory cell region.

  Next, a silicon nitride film (not shown) having a thickness of, for example, 50 nm is grown on the entire surface by, eg, CVD.

  Next, the silicon nitride film and the silicon nitride film 46 are etched back, and sidewall spacers 60 of silicon nitride film are formed on the side walls of the control gate 48 and the floating gate 50 (FIG. 18).

  Next, a 50 nm-thickness silicon oxide film (not shown) is grown on the entire surface by, eg, CVD.

  Next, the silicon oxide film is etched back to form a silicon oxide side wall spacer 62 on the side wall portion of the side wall spacer 60.

Next, by photolithography and ion implantation, ion implantation is performed using the control gate 48 and the side wall spacers 60 and 62 as a mask to form an N-type impurity layer 64 serving as a source / drain region (FIG. 19). The N-type impurity layer 64 is formed, for example, by implanting phosphorus ions under the conditions of an acceleration energy of ¹⁵ keV and a dose of 2 × 10 ¹⁵ cm ⁻² .

  Next, a metal silicide film 66 is formed on the control gate 48 and the N-type impurity layer 64 by a salicide process.

  Thus, a memory cell transistor is formed in the memory cell region of the silicon substrate 10.

  Next, a silicon nitride film 68 having a thickness of, for example, 1 nm and a BPSG film 70 having a thickness of, for example, 2000 nm are deposited on the silicon substrate 10 on which the memory cell transistor is formed by, for example, a CVD method, thereby forming an interlayer insulating film 72. To do.

  Next, a contact hole 74 exposing the drain region of the memory cell transistor is formed in the interlayer insulating film 72.

  Next, a predetermined wiring process is performed to form a contact plug 76 embedded in the contact hole 74, a bit line 78 connected to the memory cell transistor via the contact plug 76, and the like, thereby completing the semiconductor device according to the present embodiment. (FIG. 20).

  As described above, according to the present embodiment, since the surface area is increased by forming the end portion of the floating gate as a two-layer structure, the capacitance of the capacitor formed between the floating gate and the control gate is increased to increase the coupling ratio. Can be increased. As a result, the operating voltage can be lowered and the boosting time can be shortened, and the semiconductor device can be easily integrated and miniaturized.

  In addition, since the lower portion of the side wall of the floating gate has an inversely tapered shape, the generation of stringer residues when forming the stack gate structure can be suppressed. Thereby, the yield and reliability of the semiconductor device can be improved.

  In addition, since the silicon film 24 is selectively left in the element isolation region by using the mask film used in forming the element isolation insulating film 20, the end portion is 2 without significant change in the manufacturing process. A floating gate 50 having a layer structure can be formed. Thereby, a memory cell transistor having a large coupling ratio can be formed without a significant increase in manufacturing cost.

[Second Embodiment]
A method for fabricating a semiconductor device according to the second embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 22 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  23 to 27 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  In the present embodiment, another method for manufacturing the semiconductor device according to the first embodiment shown in FIG. 1 will be described.

  First, in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 5 to 9, the element isolation insulating film 20, the silicon film 24, etc. are formed (FIG. 23).

  Next, the silicon film 24 is etched back by dry etching until the surface of the silicon nitride film 14 is exposed, and the silicon film 24 is selectively left on the side wall portion of the silicon nitride film 14 (FIG. 24).

  Since the surface heights of the element isolation insulating film 20 and the silicon nitride film 14 formed in the peripheral circuit region are substantially equal (see FIG. 9B), the silicon film 24 formed in the peripheral circuit region is etched. It is removed in the back process.

  Next, the silicon nitride film 14 and the silicon oxide film 12 are removed by wet etching, for example.

  Next, a silicon oxide film of, eg, a 20 nm-thickness is formed by thermal oxidation. Thus, a sacrificial oxide film 26 of a silicon oxide film is formed on the element region (FIG. 25).

  Next, a predetermined well is formed in the high voltage transistor formation region in the memory cell region and the peripheral circuit region by photolithography and ion implantation.

  Next, the sacrificial oxide film 26 is removed by, for example, wet etching using a hydrofluoric acid aqueous solution.

  Next, for example, heat treatment is performed in an oxidizing atmosphere, the surface of the silicon substrate 10 is thermally oxidized, and a silicon oxide film of, eg, a 10 nm-thickness is grown in the element region to form a tunnel gate insulating film 36 of a silicon oxide film.

Next, a silicon film 38 having a film thickness of, for example, 100 nm and a phosphorus concentration of, for example, 1 × 10 ²² cm ⁻³ is deposited on the entire surface by, eg, CVD.

  Next, the silicon film 38 in the peripheral circuit region is removed by photolithography, and a photoresist film 40 for patterning the silicon films 24 and 38 in the memory cell region into stripes extending in the Y direction is formed (FIG. 26). ).

  Next, the silicon films 38 and 24 are etched using the photoresist film 40 as a mask, the silicon film 38 in the peripheral circuit region is removed, and the silicon films 24 and 38 in the memory cell region are patterned into stripes extending in the Y direction. To do.

  At this time, since the impurity concentration contained in the silicon film 24 is about one digit higher than the impurity concentration contained in the silicon film 38, the etching rate of the silicon film 24 is higher than the etching rate of the silicon film 38. Therefore, when the etching conditions are set so that the etching surface of the silicon film 38 is vertical, the silicon film 24 is etched excessively than the vertical shape, and the etching surface becomes a reverse taper shape (see FIG. 22A). .

  Next, the photoresist film 40 is removed by, for example, ashing (FIG. 27).

  Thereafter, the semiconductor device is completed in the same manner as the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 16 to 20, for example.

  As described above, according to the present embodiment, since the surface area is increased by forming the end portion of the floating gate as a two-layer structure, the capacitance of the capacitor formed between the floating gate and the control gate is increased to increase the coupling ratio. Can be increased. As a result, the operating voltage can be lowered and the boosting time can be shortened, and the semiconductor device can be easily integrated and miniaturized.

  In addition, since the lower portion of the side wall of the floating gate has an inversely tapered shape, the generation of stringer residues when forming the stack gate structure can be suppressed. Thereby, the yield and reliability of the semiconductor device can be improved.

  In addition, since the silicon film 24 is selectively left in the element isolation region by using the mask film used in forming the element isolation insulating film 20, the end portion is 2 without significant change in the manufacturing process. A floating gate 50 having a layer structure can be formed. Thereby, a memory cell transistor having a large coupling ratio can be formed without a significant increase in manufacturing cost.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above embodiment, the sidewall of the silicon film 24 has an inversely tapered shape, but the sidewall of the silicon film 24 does not necessarily have an inversely tapered shape. One object of the above embodiment is to increase the capacitance of the capacitor formed between the floating gate 50 and the control gate 48. This object can be achieved by forming the floating gate 50 with the silicon films 24 and 38 independently of making the side wall of the silicon film 24 into an inversely tapered shape.

  Further, in the above embodiment, the surface of the element isolation insulating film 20 is etched before the silicon film 24 is deposited, thereby reducing the step between the element region and the element isolation region. Therefore, even if the side wall of the silicon film 24 does not necessarily have an inversely tapered shape, the effect of suppressing stringer residue can be expected as in the normal flat STI process.

  The cross-sectional shape of the floating gate 50 is not limited to the shape described in the above embodiment as long as the film thickness at both ends in the X direction is thicker than the film thickness at the center. As for the cross-sectional shape of the floating gate 50, for example, as shown in FIG. Alternatively, for example, as shown in FIG. 28B, the lower side of the end portion in the X direction of the floating gate 50 may have an inversely tapered shape. Alternatively, for example, as shown in FIG. 28C, the lower side of the end portion in the X direction of the floating gate 50 may have a stepped inverse taper shape.

  The shape of the floating gate 50 has a structure in which a central portion located on the element region is formed by a single conductive film and both end portions located on the element isolation insulating film are formed by two conductive films. By doing so, an effect of increasing the coupling ratio can be obtained. The manufacturing method of the floating gate 50 is not limited to the above embodiment.

  In the above embodiment, the flash EEPROM is described as an example of a semiconductor memory device having a stack structure gate electrode. However, the present invention can also be applied to other semiconductor memory devices having a stack structure gate electrode.

  In addition, the structure, constituent materials, manufacturing conditions, and the like of the semiconductor device described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art.

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12, 18, 58 ... Silicon oxide film 14, 46, 68 ... Silicon nitride film 16 ... Element isolation groove 20 ... Element isolation insulating film 22, 40 ... Photoresist film 24, 38, 44 ... Silicon film 26 ... Sacrificial oxide films 28, 30 ... P well 32 ... N well 34 ... N type buried layer 36 ... tunnel gate insulating film 42 ... ONO film 48 ... control gate 50 ... floating gate 52 ... P type impurity layers 54, 56, 64 ... N Type impurity layers 60, 62 ... sidewall spacers 66 ... metal silicide films 70 ... BPSG films 72 ... interlayer insulating films 74 ... contact holes 76 ... contact plugs 78 ... bit lines

Claims (3)

Forming a mask film on the semiconductor substrate to cover the element region and expose the element isolation region;
Etching the semiconductor substrate using the mask film as a mask, and forming an element isolation groove in the element isolation region of the semiconductor substrate;
Burying a first insulating film in the element isolation trench to form an element isolation insulating film;
By the mask layer by etching the element isolation insulating film as a mask, the surface height of the element isolation insulating film lower than the surface height of the mask film, the device isolation insulating film defining the device regions Forming, and
Depositing a first conductive film on the mask film and the element isolation insulating film;
Removing the first conductive film on the mask film and selectively leaving the first conductive film on the element isolation insulating film;
Removing the mask film;
Forming a second insulating film on the element region;
And forming the the second insulating film and said first conductive film is formed the element isolation insulating film, the second conductive film,
The second conductive film and the first conductive film are patterned, and a first portion formed by the second conductive film is located on the element region, and the first conductive film and the second conductive film Forming a floating gate in which the second portion formed by the laminated film of the conductive film is selectively located on the element isolation insulating film;
Forming a third insulating film on the floating gate;
Forming a control gate extending in a first direction on the third insulating film;
Removing the third insulating film and the floating gate is etched, the said control gate is formed in a region other than the forming region third insulating film and the floating gate of the control gate as a mask A method for manufacturing a semiconductor device, comprising: Forming a mask film on the semiconductor substrate to cover the element region and expose the element isolation region;
Etching the semiconductor substrate using the mask film as a mask, and forming an element isolation groove in the element isolation region of the semiconductor substrate;
Burying a first insulating film in the element isolation trench to form an element isolation insulating film;
Etching the element isolation insulating film using the mask film as a mask, and reducing the surface height of the element isolation insulating film to be lower than the surface height of the mask film, thereby forming the element isolation insulating film defining the element region Forming, and
Depositing the first conductive film on the mask film and the element isolation insulating film;
Etching back the first conductive film, and selectively leaving the first conductive film on a side wall portion of the mask film;
Removing the mask film;
Forming a second insulating film on the element region;
Forming a second conductive film on the second insulating film and on the element isolation insulating film on which the first conductive film is formed;
The second conductive film and the first conductive film are patterned, and a first portion formed by the second conductive film is located on the element region, and the first conductive film and the second conductive film Forming a floating gate in which the second portion formed by the laminated film of the conductive film is selectively located on the element isolation insulating film;
Forming a third insulating film on the floating gate;
Forming a control gate extending in a first direction on the third insulating film;
Etching the third insulating film and the floating gate using the control gate as a mask, and removing the third insulating film and the floating gate formed in a region other than the region where the control gate is formed;
A method for manufacturing a semiconductor device, comprising: Forming an element isolation insulating film for defining an element region on a semiconductor substrate;
Forming a first conductive film containing a semiconductor material having a first impurity concentration on the element isolation insulating film;
Forming a first insulating film on the element region;
A second conductive film including a semiconductor material having a second impurity concentration lower than the first impurity concentration on the first insulating film and on the element isolation insulating film on which the first conductive film is formed. Forming a step;
The second conductive film and the first conductive film are patterned, and a first portion formed by the second conductive film is located on the element region, and the first conductive film and the second conductive film Forming a floating gate in which the second portion formed by the laminated film of the conductive film is selectively located on the element isolation insulating film;
Forming a second insulating film on the floating gate;
Forming a control gate extending in a first direction on the second insulating film;
Etching the second insulating film and the floating gate using the control gate as a mask, and removing the second insulating film and the floating gate formed in a region other than the region where the control gate is formed;
A method for manufacturing a semiconductor device, comprising:

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