JP4151992B2 - Semiconductor integrated circuit device - Google Patents

Description

Technical field
The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and in particular, high integration and high performance of a DRAM (Dynamic Random Access Memory) or an electrically rewritable nonvolatile memory, or a logic circuit and a DRAM or electrical rewrite. The present invention relates to a technology that is effective when applied to a highly integrated semiconductor integrated circuit device in which a non-volatile memory capable of being mounted is mounted.
Background art
There is a DRAM as a semiconductor memory that represents a large-capacity memory. The memory capacity of this DRAM tends to increase more and more, and the area occupied by the memory cell is inevitably reduced from the viewpoint of improving the degree of integration of the memory cell of the DRAM.
However, the storage capacity value of the information storage capacitor element (capacitor) in the DRAM memory cell needs a certain amount regardless of the generation from the viewpoint of considering the operation margin of the DRAM, soft error, etc., and generally cannot be proportionally reduced. It is known.
Therefore, the development of a capacitor structure that can secure the necessary storage capacity within a limited small area is underway. As the structure, two layers of electrodes made of polysilicon or the like are stacked via a capacitive insulating film. A three-dimensional capacitor structure such as a so-called stacked capacitor is employed.
A stacked capacitor generally has a structure in which a capacitor electrode is arranged in an upper layer of a memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor). In this case, a large storage capacity can be ensured with a small occupied area, and it is necessary. The storage capacity to be stored is small.
As such a stacked capacitor structure, for example, a so-called capacitor over bit line (hereinafter abbreviated as COB) structure in which a capacitor is disposed above a bit line, and a capacitor is disposed below the bit line. There is a capacitor under bitline (capacitor under bitline; hereinafter abbreviated as CUB) structure.
In these COB and CUB structure DRAMs, it is necessary to form the connection hole so that the conductor film or bit line in the capacitor connection hole does not short-circuit with the word line. In consideration of misalignment of the connection holes, etc., it must be widened to some extent, which hinders the improvement of element integration and the reduction of the chip size. Therefore, in order to realize high integration, advanced alignment technology and process management are required.
Therefore, in order to avoid such a problem, the capacitor connection hole and the bit line connection hole are formed by covering the upper surface and side wall of the word line with an insulating material different from the interlayer insulating film such as a nitride film. There is a technique of forming in a self-aligned manner with respect to a word line by etching.
In the case of this technique, when the capacitor connection hole and the bit line connection hole are formed by etching, even if the connection hole covers the word line in plan view, the nitride film around the word line is an etching stopper. Therefore, the connection hole can be formed without exposing the word line from the connection hole.
A technique for forming the capacitor connection hole and the bit line connection hole in a self-aligned manner with respect to the word line is described in JP-A-9-55479.
By the way, the present inventor has studied a technique for forming the capacitor connection hole or the bit line connection hole in a self-aligned manner with respect to the word line. The following is not a known technique, but is a technique studied by the present inventor, and the outline thereof is as follows.
The aforementioned DRAM is formed by the following process flow.
First, a conductor layer is formed on a semiconductor substrate via a gate insulating film. A first nitride film is deposited on the conductor layer. By patterning the first nitride film and the conductor film with the same mask, the gate electrode of the memory cell selecting MISFET and the gate electrode of the peripheral circuit MISFET are formed. Here, the gate electrodes of the plurality of memory cells arranged in the row direction of the memory cell array are integrally formed and function as a word line of the DRAM. Next, the low concentration semiconductor regions of the memory cell selection MISFET and the peripheral circuit MISFET are formed in a self-aligned manner with respect to the gate electrode of the memory cell selection MISFET and the gate electrode of the peripheral circuit MISFET. Next, a second nitride film is deposited on the semiconductor substrate, and anisotropic etching is performed on the second nitride film, whereby the nitride film is formed on the sidewalls of the gate electrode of the memory cell selection MISFET and the gate electrode of the peripheral circuit MISFET. Side wall spacers are formed. A high-concentration semiconductor region of the peripheral circuit MISFET is formed in a self-aligned manner with respect to the sidewall spacer. An oxide-based interlayer insulating film is deposited on the semiconductor substrate, and a bit line connection hole and a capacitor connection hole are opened in a self-aligned manner with respect to the word line in the memory cell region. The opening process of the bit line connection hole and the capacitor connection hole with respect to the interlayer insulating film is performed under the condition that the etching selection ratio between the nitride film forming the sidewall and the oxide film forming the interlayer insulating film is large. The bit line connection hole and the capacitor connection hole can be formed without exposing the word line.
On the other hand, in order to improve the degree of integration of DRAM memory cells, it is necessary to reduce the word line interval. If the above-described second nitride film is deposited on the word line having a small interval between the word lines to a predetermined thickness or more, the space between the word lines is completely filled with the second nitride film in the memory cell region. Even if anisotropic etching is performed for the formation, the surface of the semiconductor substrate is not exposed. Alternatively, there is a problem that the exposed area is very small and the contact resistance with the bit line or the capacitor electrode becomes large.
Further, the side wall spacer formed on the side walls of the gate electrode of the memory cell selection MISFET and the gate electrode of the peripheral circuit MISFET determines the length of the low concentration semiconductor region of the peripheral circuit MISFET having the LDD structure, When the width of the sidewall spacer is reduced, there are problems that the short channel effect of the peripheral circuit MISFET becomes remarkable and the punch through breakdown voltage between the source and the drain is lowered. Therefore, the film thickness of the second nitride film for forming the sidewall spacer needs to be greater than a predetermined thickness.
In other words, it is necessary to optimize the LDD structure in order to ensure the predetermined performance of the MISFET. In order to prevent the high-concentration semiconductor region of the peripheral circuit MISFET from diffusing beyond the low-concentration semiconductor region when the width of the side-wall spacer is reduced by miniaturization of the DRAM memory cell selection MISFET, The width needs to be equal to or greater than a predetermined width. That is, there is a lower limit on the width of the sidewall spacer.
On the other hand, when the miniaturization of the memory array is advanced, the interval between the gate electrodes, that is, the interval between the selection MISFETs of adjacent memory cells is inevitably reduced, and the width of the self-aligned connection portion is also reduced. Narrowing of the connection area causes a significant increase in contact resistance, so that there is a demand for making the width of the sidewall spacer as small as possible. Such a requirement is contrary to the requirement for realizing an optimized LDD structure, and in an extreme case, if an optimized LDD structure is to be realized, it is adjacent in the memory array region. There are situations where the side wall spacers overlap and self-aligned connection cannot be realized.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit technology capable of high-speed operation while miniaturizing DRAM memory cells in a semiconductor integrated circuit device mounted with a DRAM.
Another object of the present invention is to provide a semiconductor integrated circuit technology in which a memory cell is miniaturized and highly integrated and can operate at high speed in a semiconductor integrated circuit device in which an electrically rewritable nonvolatile memory is mounted in addition to a DRAM. It is to provide.
Still another object of the present invention is to provide a high-performance semiconductor integrated circuit technology that is excellent in DRAM refresh characteristics.
Still another object of the present invention is to provide a highly reliable semiconductor integrated circuit technology by preventing excessive etching of an element isolation region of a semiconductor substrate when a connection hole is opened.
Still another object of the present invention is to provide a technique for simplifying the manufacturing process of a semiconductor integrated circuit device on which a DRAM and an electrically rewritable nonvolatile memory are also mounted.
Still another object of the present invention is to provide a semiconductor integrated circuit device in which a DRAM memory cell can be miniaturized and highly integrated, and the reliability of a peripheral circuit MISFET can be improved. To provide technology.
An object of the present invention is to provide a technique for forming a connection hole in a self-aligned manner even in a highly integrated DRAM memory cell region and preventing excessive etching of an element isolation region at the bottom of the connection hole. .
Another object of the present invention is to provide a technique capable of improving the processing margin of a connection hole when the connection hole is formed in a self-aligning manner and excessive etching of the element isolation region at the bottom of the connection hole is prevented. It is to provide.
Another object of the present invention is to provide a technique capable of suppressing an increase in the number of steps when forming the connection hole in a self-aligning manner and preventing excessive etching of the element isolation region at the bottom of the connection hole. It is in.
Another object of the present invention is to provide a technique capable of realizing high integration of a semiconductor integrated circuit device, improving the refresh characteristics of a DRAM, and improving the transistor characteristics of a memory cell region. .
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Disclosure of the invention
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor integrated circuit device according to the present invention includes a gate electrode formed on a main surface of a semiconductor substrate via a gate insulating film and a semiconductor region in contact with a channel region of the main surface of the semiconductor substrate below the gate electrode. 1 MISFET, a gate electrode formed on the main surface of the semiconductor substrate via a gate insulating film, a low concentration semiconductor region in contact with a channel region of the main surface of the semiconductor substrate below the gate electrode, and provided outside the low concentration semiconductor region A second MISFET including a high-concentration semiconductor region, wherein a cap insulating film is formed on the upper surfaces of the gate electrodes of the first and second MISFETs, and on the side surfaces of the gate electrodes of the second MISFETs, Formed with a first sidewall formed of a first insulating film and a second insulating film formed of a member different from the first insulating film on the outside thereof The second sidewall is formed, and the conductor portion that connects the semiconductor region of the first MISFET and the member formed in the upper layer of the first MISFET is self-conductive to the third sidewall formed of the first insulating film. The high-concentration semiconductor region of the second MISFET formed by matching is formed by self-alignment with respect to the second sidewall formed by the second insulating film.
According to such a semiconductor integrated circuit device, the first and second insulating films are formed on the side surfaces of the gate electrode, and the first MISFET is connected to the member formed in the upper layer thereof as the first insulating film. Since the second MISFET is formed in a self-aligned manner with respect to the second sidewall formed of the second insulating film, the second MISFET is formed in a self-aligned manner. The integration degree of the integrated circuit device can be improved and the performance thereof can be improved.
That is, the self-alignment of the conductor portion connecting the semiconductor region of the first MISFET and the member formed in the upper layer of the first MISFET is secured by the third sidewall formed by the first insulating film, The position of the high-concentration semiconductor region necessary for forming the so-called LDD of the second MISFET can be optimized by the second sidewall formed of the insulating film, so that the performance of the second MISFET can be kept high. That is, as the first insulating film, a material having an etching selection ratio with respect to a silicon oxide film, which is a general interlayer insulating film material, for example, a silicon nitride film can be used, and an LDD is formed as the second insulating film. In this case, a silicon oxide film having a blocking ability of implanted ions necessary for the above can be used. For the first MISFET, the second insulating film does not become an obstacle for the self-aligned junction, For the second MISFET, the first and second insulating films can act as effective spacers for forming the LDD. Therefore, it is not necessary to design the first insulating film in consideration of the space necessary for forming the LDD structure, and it is sufficient to make the film thickness sufficient to realize self-aligned connection. Thus, the first MISFET can be formed with high integration. On the other hand, the second insulating film does not need to consider the interval between the gate electrode wirings in the first MISFET formation region. Therefore, it is possible to form a sidewall spacer spacer having a sufficient film thickness necessary for maintaining the performance of the MISFET, and to improve the performance of the second MISFET.
The first insulating film is first and third sidewall spacers made of a silicon nitride film formed on the side surface of the gate electrode, and the second insulating film is a gate sandwiching the first sidewall spacer. A second sidewall spacer made of a silicon oxide film formed on the side surface of the electrode can be obtained.
The first insulating film is a silicon nitride film formed on the semiconductor substrate including the side surface of the gate electrode, and the second insulating film is a silicon oxide film formed on the side surface of the gate electrode with the silicon nitride film interposed therebetween. The sidewall spacer can be made of In such a case, the first etching process for etching the silicon oxide film and the second etching process for etching the silicon nitride film when the connection hole for connecting to the MISFET is opened. It is possible to use a silicon nitride film as an etching stopper in the first etching process. By separating the etching process into two stages in this way, the first etching process can be surely opened, and excessive etching can be prevented in the second etching process.
Furthermore, the semiconductor integrated circuit device of the present invention may include an N-channel MISFET and a P-channel MISFET in the second MISFET and have a C (Complementary) MISFET structure. According to such a semiconductor integrated circuit device, a high performance and low power consumption semiconductor integrated circuit device can be obtained by the CMISFET structure, and not only the peripheral circuit of the DRAM but also a logic circuit is configured by the second MISFET. It is also possible to provide a memory and logic mixed type semiconductor integrated circuit device.
(2) A semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (1), wherein the first MISFET is a DRAM selection MISFET arranged in a memory array region of a DRAM cell, The member formed in the upper layer of the MISFET is a DRAM storage capacitor or bit line.
According to such a semiconductor integrated circuit device, the integration degree of DRAM memory cells is improved, the performance of the peripheral circuit formed by the second MISFET is improved, and high-performance DRAM integration capable of high-speed operation and the like is possible. It can be a circuit device.
The impurity doped in the semiconductor region of the selective MISFET is phosphorus, and the low-concentration semiconductor region or the high-concentration semiconductor region of the N-channel MISFET in the second MISFET is at least doped with arsenic. it can. The N-channel MISFET includes a first N-channel MISFET and a second N-channel MISFET. The first N-channel MISFET includes a low-concentration semiconductor region doped with arsenic and a high-concentration semiconductor doped with arsenic. The second N-channel MISFET can include a lightly doped semiconductor region doped with phosphorus and a heavily doped semiconductor region doped with arsenic. Further, the first N-channel MISFET includes a semiconductor region doped with boron in a region in contact with the high-concentration semiconductor region below the low-concentration semiconductor region, and the second N-channel MISFET includes a semiconductor region doped with boron. It can not be.
Thus, the withstand voltage of the selected MISFET can be improved by using phosphorus as the impurity doped in the semiconductor region of the selected MISFET, and the refresh current of the DRAM can be improved by reducing the leakage current between the source and drain. Can do. Further, by doping arsenic in both the low-concentration semiconductor region and the high-concentration semiconductor region of the first N-channel MISFET, the channel length of the first N-channel MISFET can be shortened, and the second N-channel MISFET By doping phosphorus in the low-concentration semiconductor region and doping arsenic in the high-concentration semiconductor region, the second N-channel MISFET can be made a high breakdown voltage MISFET. Furthermore, it is possible to further shorten the channel length by forming a semiconductor region doped with boron serving as a punch-through stopper in the first N-channel MISFET, and no punch-through stopper is provided in the second N-channel MISFET. As a result, it is possible to further increase the breakdown voltage.
Further, the silicide layer is not formed on the surface of the semiconductor region of the selective MISFET, and the silicide layer is formed on the surface of the high concentration semiconductor region. By not providing a silicide layer on the surface of the semiconductor region of the selective MISFET, a DRAM having excellent refresh characteristics can be formed by suppressing leakage between channels. By providing a silicide layer on the surface of the high concentration semiconductor region, the first The connection resistance in the connection hole of the second MISFET and the sheet resistance of the semiconductor region can be reduced to obtain a MISFET capable of high speed operation, and the performance of the semiconductor integrated circuit device can be improved.
Furthermore, the thickness of the gate insulating film of the selective MISFET can be made thicker than the thickness of the gate insulating film of the second MISFET. By reducing the thickness of the gate insulating film of the second MISFET, the channel length of the second MISFET can be shortened, and by increasing the thickness of the gate insulating film of the selected MISFET, Therefore, a DRAM having excellent refresh characteristics can be formed. Note that shortening the channel length of the second MISFET has the effect of increasing the drive current of the MISFET, and has the effect that a high-performance semiconductor integrated circuit device capable of high-speed operation can be obtained. is there.
(3) A semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1), in which the first MISFET, the gate insulating film is a tunnel insulating film, and the gate electrode includes a floating gate electrode and The floating gate type MISFET is arranged in a memory array region of a nonvolatile memory cell including a control gate electrode formed on the floating gate electrode through an insulating film.
According to such a semiconductor integrated circuit device, similarly to the DRAM described in the above (2), the memory array region of the nonvolatile memory cell can be highly integrated and the nonvolatile memory configured by the second MISFET It is possible to improve the performance of the MISFET in the peripheral circuit of the memory.
Note that the thickness of the gate insulating film of the second MISFET can be made thicker than the thickness of the gate insulating film of the first MISFET. As described above, by increasing the thickness of the gate insulating film of the second MISFET, the MISFET for a peripheral circuit of a non-volatile memory that is generally driven at a high voltage can be made a high withstand voltage MISFET.
(4) A semiconductor integrated circuit device of the present invention includes both the DRAM and the non-volatile memory described in (2) and (3). That is, the first MISFET includes both the selection MISFET and the floating gate type MISFET.
According to such a semiconductor integrated circuit device, high integration is realized in the memory array region of the DRAM and the nonvolatile memory, and a semiconductor integrated circuit device having high performance in the peripheral circuit or logic circuit region is formed. Can do.
The DRAM bit line and the wiring formed in the upper layer of the floating gate type MISFET can be formed in the same process. Thereby, the process can be shortened.
Further, the film thicknesses of the gate insulating films of the selection MISFET, the floating gate type MISFET, the peripheral circuit or logic circuit MISFET for driving the DRAM, and the MISFET of the peripheral circuit for driving the floating gate type MISFET are different from each other. The film thickness of the gate insulating film of the MISFET of the peripheral circuit that drives the MISFET is larger than the film thickness of the gate insulating film of the floating gate type MISFET. The film thickness of the gate insulating film of the floating gate type MISFET is equal to that of the selected MISFET. The thickness of the gate insulating film of the selected MISFET is thicker than the thickness of the gate insulating film, and the thickness of the gate insulating film of the peripheral circuit or logic circuit driving the DRAM is larger than that of the gate insulating film. Can do. As a result, the gate insulating film thickness is optimum for each MISFET of the selection MISFET, the floating gate type MISFET, the MISFET of the peripheral circuit or logic circuit that drives the DRAM, and the MISFET of the peripheral circuit that drives the floating gate type MISFET. it can.
In the semiconductor integrated circuit device described in (1) to (4), a silicon nitride film that covers the second MISFET and the semiconductor substrate is formed in the region where the second MISFET is formed. Can do.
According to such a semiconductor integrated circuit device, since the silicon nitride film is formed on the semiconductor substrate in the peripheral circuit or logic circuit region, the connection hole is formed in the element isolation region of the semiconductor substrate. However, the element isolation region is not excessively etched, and no leak between elements occurs. As a result, it is possible to prevent the occurrence of defects in the semiconductor integrated circuit device and improve its reliability and performance.
(5) In the method for manufacturing a semiconductor integrated circuit device of the present invention, (a) a step of forming a gate insulating film on the main surface of the semiconductor substrate, (b) forming a gate electrode and a cap insulating film on the gate insulating film. (C) a step of forming low-concentration semiconductor regions of the first and second MISFETs in self-alignment with the gate electrode; (d) a step of forming a first sidewall spacer on the side surface of the gate electrode; Forming a second sidewall spacer outside the first sidewall spacer; (f) forming a high-concentration semiconductor region in a self-aligned manner with respect to the second sidewall spacer of the second MISFET; A step of depositing an interlayer insulating film made of a silicon oxide film on the entire surface of the semiconductor substrate; (h) interlayer insulation by self-alignment with the first sidewall spacer of the first MISFET. The film and the second sidewall spacer by etching, a step of a connection hole is intended to include the step of forming a conductive portion (i) connecting hole.
The method for manufacturing a semiconductor integrated circuit device of the present invention includes (a) a step of forming a gate insulating film on the main surface of the semiconductor substrate, and (b) a step of forming a gate electrode and a cap insulating film on the gate insulating film. (C) forming low-concentration semiconductor regions of the first and second MISFETs in self-alignment with the gate electrode; (d) depositing a silicon nitride film on the entire surface of the semiconductor substrate including the side surfaces of the gate electrode; e) a step of forming a sidewall spacer on the side surface of the gate electrode sandwiching the silicon nitride film, (f) a step of forming a high-concentration semiconductor region in a self-alignment with the sidewall spacer of the second MISFET, and (g) a semiconductor substrate. A step of depositing an interlayer insulating film made of a silicon oxide film on the entire surface of the substrate, and (h) an interlayer insulating film and a sidewall spacer self-aligned with the silicon nitride film Is etched to form an opening, a step of a connection hole further a silicon nitride film of the bottom of the opening is etched, it is intended to include the step of forming a conductive portion (i) connecting hole.
According to such a method for manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device described in (1) above can be formed.
(6) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the step (c), phosphorus is implanted into the semiconductor region of the first MISFET, and at least one of the low-concentration semiconductor regions of the second MISFET. Arsenic can be implanted into the low concentration semiconductor region. According to such a method of manufacturing a semiconductor integrated circuit device, the breakdown voltage of the first MISFET can be improved, and the channel length of the second MISFET in which arsenic is implanted can be shortened. It becomes.
In the step (a), the gate insulating film of the first MISFET and the gate insulating film of the second MISFET can be formed in the same step.
In such a case, the process of forming the gate insulating film can be shortened to simplify the process.
In the step (a), the gate insulating film is formed, the step of forming the first gate insulating film in the region where the first and second MISFETs are formed, and the first region of the region where the second MISFET is formed. The step of selectively removing the gate insulating film and the step of forming the second gate insulating film in a region where the second MISFET is formed can be included. In such a case, the film thicknesses of the gate insulating films of the first and second MISFETs can be different from each other, and the second gate insulating film is formed after the first gate insulating film is formed. The second gate insulating film can be formed thinner than the first gate insulating film.
(7) A method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (5), wherein the gate insulating film is a tunnel insulating film of a floating gate type MISFET constituting a nonvolatile memory. The formation of the gate electrode includes a step of forming a floating gate electrode of the floating gate type MISFET on the tunnel insulating film and a step of forming a control gate electrode of the floating gate type MISFET on the floating gate electrode via the insulating film. Can be included. According to such a method for manufacturing a semiconductor integrated circuit device, it is possible to form a non-volatile memory that is highly integrated in the memory array region and that achieves high performance in the peripheral circuit region.
(8) A method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (5) or (6) above, wherein (a) on the main surface of the semiconductor substrate before the step And forming a floating gate electrode of the floating gate type MISFET on the tunnel insulating film.
According to such a method of manufacturing a semiconductor integrated circuit device, it is possible to manufacture a semiconductor integrated circuit device in which a DRAM and a nonvolatile memory that are highly integrated in the memory array region and have high performance in the peripheral circuit region are mounted together. it can.
The formation of the gate electrode in the step (b) and the formation of the control gate electrode of the floating gate type MISFET can be formed in the same step, and the process can be simplified.
Further, the tunnel insulating film can be formed thicker than the gate insulating film in the step (a).
(9) A method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of (5) to (8) above, wherein the second MISFET is formed before the step (g). A second silicon nitride film is deposited in the region to be formed, and an interlayer insulating film in a region where a conductive portion connecting the second MISFET and a member formed thereon is formed is formed on the second silicon nitride film. Then, etching may be performed under the condition that the etching selectivity can be obtained, and further, a step of etching the second silicon nitride film at the bottom of the opening to form a connection hole to form a conductive portion may be provided. .
According to such a method of manufacturing a semiconductor integrated circuit device, the etching of the interlayer insulating film is stopped by the second silicon nitride film, and the second silicon nitride film that can be made extremely thin as compared with the interlayer insulating film is obtained. Since etching can be performed after that, it is sufficient that the overetching of the etching corresponds to one half of the thickness of the second silicon nitride film, and the connection hole covers the element isolation region of the semiconductor substrate. Even if it exists, an element isolation region is not etched excessively. As a result, the process margin of the etching process is ensured and the element isolation performance of the element isolation region is ensured, and the performance and reliability of the semiconductor integrated circuit device can be ensured.
The second silicon nitride film can be formed in the same process as the silicon nitride film formed as the first insulating film.
The effects obtained by typical ones of the inventions disclosed above will be briefly described as follows.
(1) In a semiconductor integrated circuit device equipped with a DRAM or a nonvolatile memory, it is possible to provide a semiconductor integrated circuit technology capable of high-speed operation while miniaturizing and highly integrating memory cells of the DRAM or nonvolatile memory.
(2) In a semiconductor integrated circuit device equipped with a DRAM and an electrically rewritable nonvolatile memory, it is possible to provide a semiconductor integrated circuit technology capable of high-speed operation while miniaturizing memory cells to achieve high integration.
(3) It is possible to provide a high-performance semiconductor integrated circuit technology that is excellent in the refresh characteristics of the DRAM.
(4) Excessive etching of the element isolation region of the semiconductor substrate at the time of opening the connection hole can be prevented, and a highly reliable semiconductor integrated circuit technology can be provided.
(5) In a semiconductor integrated circuit device on which a DRAM and an electrically rewritable nonvolatile memory are mounted, the manufacturing process can be simplified.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a principal part showing an example of a semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2 shows a memory cell region of a DRAM included in the semiconductor integrated circuit device according to the first embodiment. FIG. 3 is a block diagram of the semiconductor integrated circuit device of the first embodiment, and FIG. 4 is an equivalent circuit diagram of a DRAM included in the semiconductor integrated circuit device of the first embodiment. 5 to 25 are cross-sectional views or plan views showing an example of the manufacturing method of the semiconductor integrated circuit device according to the first embodiment in the order of steps, and FIGS. 48 and 49 are the semiconductor integrated circuit device according to the first embodiment. It is sectional drawing which showed another example of this manufacturing method in process order.
FIG. 26 is a cross-sectional view showing an example of the semiconductor integrated circuit device according to the second embodiment of the present invention. FIGS. 27 to 29 show the semiconductor integrated circuit device according to the second embodiment. It is sectional drawing which showed an example of the manufacturing method in the order of the process.
FIG. 30 is a cross-sectional view showing an example of the semiconductor integrated circuit device according to the third embodiment of the present invention, and FIGS. 31 to 33 show the semiconductor integrated circuit device according to the third embodiment. It is sectional drawing which showed an example of the manufacturing method in the order of the process.
FIG. 34 is a cross-sectional view showing an example of a semiconductor integrated circuit device according to the fourth embodiment of the present invention, and FIG. 35 is an enlarged cross-sectional view of region C and region D in FIG. FIG. 36 is a plan view of a memory array region of an electrically rewritable batch erasable nonvolatile memory so-called flash memory included in the semiconductor integrated circuit device of the fourth embodiment, and FIG. 37 is a part of the flash memory. 38 to 46 are plan views or cross-sectional views showing an example of the manufacturing method of the semiconductor integrated circuit device of the fourth embodiment in the order of steps.
FIG. 47 is a cross-sectional view showing an example of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.
FIG. 50 (a) is a cross-sectional view showing an example of a DRAM according to the sixth embodiment of the present invention in the memory cell region, and FIG. 50 (b) is a peripheral circuit of the DRAM according to the sixth embodiment. FIG. 51 is a plan view of the memory cell region of the DRAM of the sixth embodiment, FIG. 52 (a) is a cross-sectional view taken along line IIIa-IIIa in FIG. 51, and FIG. 52 (b). FIG. 35 is a cross-sectional view taken along the line IIIb-IIIb in FIG. 51, and FIGS. 35 to 79 are cross-sectional views showing an example of the DRAM manufacturing method according to the sixth embodiment in the order of steps.
FIGS. 80 and 81 are cross-sectional views showing an example of a method for manufacturing a DRAM according to the seventh embodiment of the present invention, and FIGS. 82 to 84 show the DRAM according to the eighth embodiment of the present invention. It is sectional drawing which showed an example of the manufacturing method.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
(Embodiment 1)
FIG. 1 is a cross-sectional view of a principal part showing an example of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a plan view of a memory cell region of a DRAM included in the semiconductor integrated circuit device according to the first embodiment. FIG. 3 is a block diagram of the semiconductor integrated circuit device according to the first embodiment. FIG. 4 is an equivalent circuit diagram of a DRAM included in the semiconductor integrated circuit device of the first embodiment.
As shown in region A of FIG. 1, the semiconductor integrated circuit device according to the first embodiment includes storage capacitors C2 and C3 for storing information constituting memory cells of DRAMs, and select MISFETs Qs2 and Qs3 connected thereto. The word lines WL1 and WL4 adjacent to these are included. The cross section of the DRAM shown in FIG. 1 is a cross section taken along line II of the plan view of the memory cell region of the DRAM shown in FIG. Further, the semiconductor integrated circuit device according to the first embodiment includes an N channel MISFET Qn1, a P channel MISFET Qp1, and a peripheral circuit other than DRAM memory cells or other logic circuits as shown in region B of FIG. A second N-channel MISFET Qn2 is included.
Further, as shown in FIG. 3, the semiconductor integrated circuit device according to the first embodiment includes an information processing unit CPU, an input / output unit PORT, an analog / digital circuit unit ADC, other logic circuit units LG such as a timer, an OS, and the like. A microcomputer in which a ROM for data storage and a DRAM as a memory are formed on the same semiconductor substrate 1 are connected to each other via a bus BUS. The N channel MISFET Qn1 and the P channel MISFET Qp1 can be used for a logical configuration of the information processing unit CPU or the like.
Further, as shown in the equivalent circuit of FIG. 4, a 1-bit memory cell includes an information storage capacitor C and a selection MISFET Qs (Qs2, Qs3), and the information storage capacitor C and a selection MISFET Qs (Qs2). , Qs3) are connected in series. The gate electrode of the selection MISFET Qs is electrically connected to the word line WL (WL0, WL1, WLn) and is configured integrally. The word line WL is connected to the word line driver WD. One of the source and drain regions of the selection MISFET Qs is electrically connected to one electrode of the information storage capacitor C. The other of the source or drain regions of the selection MISFET Qs is connected to the bit line BL, and the bit line BL is connected to the sense amplifier SA. Thus, the 1-bit memory cell is arranged at the intersection of the word line WL and the bit line BL. As will be described later, the word line WL extends in the first direction, and the bit line BL extends in the second direction perpendicular to the first direction.
The sense amplifier SA is not particularly limited, but can be composed of the N-channel MISFET Qn1 and the P-channel MISFET Qp1. As will be described later, the N-channel MOSFET constituting the word line driver WD can be composed of an N-channel MISFET Qn2 that is different from the N-channel MISFET Qn1 in impurities in a low concentration semiconductor region. Further, the N-channel MISFET Qn2 is used in a circuit unit that operates at a higher voltage than the N-channel MISFET Qn1, such as a charge pump circuit or an input / output unit PORT if necessary.
Next, the configuration of each part will be described with reference to the cross-sectional view of the main part of FIG.
A 1-bit memory cell includes an information storage capacitor C (C2, C3) and a selection MISFET Qs (Qs2, Qs3). The selection MISFET Qs is formed in a P-type well region 5 formed on the main surface of the P-type semiconductor substrate 1. The P-type well region 5 of the memory cell is electrically isolated from the P-type semiconductor substrate 1 by an N-type N-type semiconductor region 3. Thus, a substrate bias is applied to the P-type well region 5 which is the channel region of the selected MISFET Qs in order to prevent noise from other circuits mounted on the same semiconductor substrate 1 and to reduce the bit line storage capacity of the DRAM. You can.
The selection MISFET Qs is formed in the active region 5b defined by the field insulating film 2 in the P-type well region 5, and includes the P-type well region 5 (channel forming region), the gate insulating film 6, the gate electrode 7, and the source / drain regions. A pair of low-concentration N-type semiconductor regions 9 doped with impurities are formed. The gate electrode 7 has a multi-layer structure in which a silicon film containing impurities such as phosphorus (P) or the like, or a silicon film such as tungsten silicide (WSi) or a metal film such as tungsten (W) is formed on the silicon film to reduce resistance. It can be.
The upper portion of the gate electrode 7 is covered with a silicon nitride film 8, and a first sidewall spacer 14 made of silicon nitride and a second sidewall spacer 15 made of silicon oxide are formed on the side surfaces of the gate electrode 7 and the silicon nitride film 8. Has been. The silicon nitride film 8 is configured to have the same pattern on the gate electrode 7.
The lightly doped N-type semiconductor region 9 can be doped with, for example, phosphorus as an impurity. As a result, the electric field strength between the end portion of the gate electrode 7 and the P-type well region 5 (electric field strength at the drain end portion) is weakened, and further, the generation of crystal defects that occur during impurity implantation is prevented and leakage current is reduced. Can be reduced and the refresh time can be lengthened.
Further, as shown in FIG. 6 described later, the selection MISFET Qs is electrically separated from the memory cell by the field insulating film 2 with two memory cells as a unit, and the active region 5b is defined by the field insulating film 2. .
One low-concentration N-type semiconductor region 9 of the selection MISFET Qs is connected to the conductor 20 through the connection hole 19, and the conductor 20 is connected to one electrode of the information storage capacitor C.
The conductor 20 is formed in self-alignment with the first sidewall spacer 14 made of silicon nitride. That is, the connection hole 19 is formed in self-alignment with the first sidewall spacer 14 made of silicon nitride formed on the side surface of the gate electrode 7. Thus, the conductor 20 can be connected to the low-concentration N-type semiconductor region 9 in a self-aligned manner with respect to the first sidewall spacer 14 because the second sidewall spacer 15 is made of the same material as the insulating film 18 described later. This is because the second sidewall spacer 15 and the insulating film 18 are formed of a material having a different etching rate from that of the first sidewall spacer 14. That is, when the insulating film 18 and the second sidewall spacer 15 are etched, the first sidewall spacer 14 is subjected to a condition that is less likely to be etched than silicon oxide. Thus, when the connection hole 19 is formed by etching, the conductor 20 is connected to the first sidewall spacer 14 in a self-aligned manner, so that the opening of the connection hole 19 can be increased and the margin can be increased. It is possible to improve the degree of integration by reducing the interval 7. That is, as will be described later with reference to FIG. 18, even if the interval between the word lines WL adjacent in the second direction, that is, the interval between the gate electrodes 7 is reduced and the degree of integration is improved, the opening of the connection hole 19 is maintained. The contact resistance can be reduced. Further, when the connection hole 19 is formed by lithography, the alignment margin in the second direction can be reduced, so that the interval in the second direction can be reduced.
In the first embodiment, the connection hole 19 is formed so as not to be positioned above the gate electrode 7. However, since the silicon nitride film 8 is also formed on the gate electrode 7, the connection hole 19 is not formed. You may open so that it may be located in the gate electrode 7. FIG. As a result, the margin can be further increased.
The other low-concentration N-type semiconductor region 9 of the selection MISFET Qs is configured integrally with the bit line BL via the connection hole 21 and connected to the conductor 22.
Similar to the conductor 20, the conductor 22 is formed in a self-aligned manner with respect to the first sidewall spacer made of silicon nitride formed on the side surface of the gate electrode 7. Further, like the connection hole 19, the connection hole 21 to the bit line BL may be extended and positioned above the gate electrode 7. As a result, the opening of the connection hole 21 can be increased and the margin can be increased in the same manner as the connection hole 19, so that the interval between the gate electrodes 7 (interval of the word lines WL) can be reduced to improve the degree of integration. . That is, as will be described later with reference to FIG. 20, even if the interval between the selection MISFETs Qs of the memory cells adjacent in the second direction, that is, the interval between the gate electrodes 7 is reduced to improve the integration degree, the opening of the connection hole 21 is improved. The contact resistance can be reduced. Further, when the connection hole 21 is formed by lithography, the alignment margin in the second direction can be reduced, so that the interval in the second direction can be reduced.
The conductor 20 and the conductor 22 may be silicon containing impurities such as phosphorus or silicide such as WSi in order to reduce resistance.
The storage capacitor C for information storage includes a conductor 25 and a conductor 27 constituting one electrode (lower electrode), a dielectric film 28 and an upper electrode 29 constituting the other electrode. As will be described later with reference to FIG. 22, the conductor 25 and the conductor 27 are connected to the conductor 20 through the connection hole 24, and are electrically connected to one electrode of another storage capacitor C for information storage one by one. Each one electrode is connected to one low-concentration N-type semiconductor region 9 of one selection MISFET Qs corresponding thereto. The other electrode of the storage capacitor C for information storage is electrically connected between the plurality of memory cells, and is connected to a plate potential generating circuit that is, for example, 1/2 of the power supply voltage in a region not shown.
The conductor 25, the conductor 27, and the upper electrode 29 are formed of a silicon film containing impurities such as phosphorus for reducing resistance, for example. The dielectric film 28 is formed of, for example, a laminated film made of a silicon nitride film and a silicon oxide film, or a tantalum oxide film.
The N-channel MISFET Qn1 is formed in the P-type well region 5, and includes a P-type well region 5 (channel formation region), a gate insulating film 6, a gate electrode 7, a pair of low-concentration N-type semiconductor regions 10 and a high It is composed of a concentration N-type semiconductor region 16. A P-type semiconductor region 11 is formed below the low-concentration N-type semiconductor region 10 in order to obtain a short-channel N-channel MISFET by shortening the gate length of the N-channel MISFET Qn1. The P-type semiconductor region 11 functions as a so-called MISFET punch-through stopper.
Similar to the DRAM selection MISFET Qs, a silicon nitride film 8 is formed on the gate electrode 7, and a first sidewall spacer 14 made of silicon nitride and a second sidewall spacer 15 made of silicon oxide are formed on the side surfaces of the gate electrode 7. Is formed. The high-concentration N-type semiconductor region 16 is formed in self-alignment with the second sidewall spacer 15 made of silicon oxide, as will be described later. Since the high-concentration N-type semiconductor region 16 is formed in a self-aligned manner with respect to the second sidewall spacer 15 in this way, the thickness of the second sidewall spacer 15 can be optimized to improve the performance of the N-channel MISFET Qn1. it can.
In the low-concentration N-type semiconductor region 10, for example, arsenic (As) is implanted as an impurity in order to obtain a short-channel N-channel MISFET having a gate length. Since arsenic has a smaller thermal diffusion coefficient than phosphorus, lateral diffusion can be shortened, so that an N-channel MISFET having a short gate length can be obtained. Furthermore, since the thermal diffusion coefficient is small, the concentration of the low-concentration N-type semiconductor region 10 can be increased. As a result, the parasitic resistance can be reduced, so that a high-performance N-channel MISFET can be obtained. The low concentration N-type semiconductor region 10 is formed in a self-aligned manner with respect to the gate electrode 7 and the silicon nitride film 8.
A P-type semiconductor region 11 acting as a punch-through stopper is formed under the low-concentration N-type semiconductor region 10 by implanting boron (B) as an impurity. Since the P-type semiconductor region 11 is provided, the extension of the depletion layer can be suppressed, and the short channel characteristics can be improved.
The P-channel MISFET Qp1 is formed in the N-type well region 4, and includes a pair of low-concentration P-type semiconductor regions 12 constituting the N-type well region 4 (channel forming region), the gate insulating film 6, the gate electrode 7, and the source and drain, and It is composed of a high concentration P-type semiconductor region 17. The low concentration P-type semiconductor region 12 is formed between the channel formation region and the high concentration P-type semiconductor region 17. An N-type semiconductor region 13 is formed below the low-concentration P-type semiconductor region 12 in order to obtain a short-channel P-channel MISFET by shortening the gate length of the P-channel MISFET Qp1. The N-type semiconductor region 13 functions as a so-called MISFET punch-through stopper. Similar to the selection MISFET Qs of the DRAM, a silicon nitride film 8 is formed on the gate electrode 7, and a first sidewall spacer 14 made of silicon nitride and a first oxide made of silicon oxide are formed on the side surfaces of the gate electrode 7 and the silicon nitride film 8. Two side wall spacers 15 are formed. The high-concentration P-type semiconductor region 17 is formed in a self-alignment with the second sidewall spacer 15 made of silicon oxide, as will be described later. Since the high-concentration P-type semiconductor region 17 is formed in a self-aligned manner with respect to the second sidewall spacer 15 in this way, the thickness of the second sidewall spacer 15 can be optimized to improve the performance of the P-channel MISFET Qp1. it can. As a result, the high concentration P-type semiconductor region 17 can be prevented from diffusing beyond the low concentration P-type semiconductor region 12.
The low-concentration P-type semiconductor region 12 is implanted with boron as an impurity. An N-type semiconductor region 13 acting as a punch-through stopper is formed by implanting arsenic or phosphorus as an impurity below the low-concentration P-type semiconductor region 12. Since the N-type semiconductor region 13 is provided, the extension of the depletion layer can be suppressed, and the short channel characteristics can be improved.
The N-channel MISFET Qn2 is formed in the P-type well region 5, and includes a P-type well region 5 (channel forming region), a gate insulating film 6, a gate electrode 7, a pair of low-concentration N-type semiconductor regions 10b constituting the source and drain, and a high It is composed of a concentration N-type semiconductor region 16b. The low concentration N-type semiconductor region 10b is formed between the channel formation region and the high concentration N-type semiconductor region 16b. Similar to the DRAM selection MISFET Qs, a silicon nitride film 8 is formed on the gate electrode 7, and a first sidewall spacer 14 made of silicon nitride and a second sidewall spacer 15 made of silicon oxide are formed on the side surfaces of the gate electrode 7. Is formed. The low-concentration N-type semiconductor region 10b is formed in self-alignment with the gate electrode 7 and the silicon nitride film 8, and the high-concentration N-type semiconductor region 16b is formed on the second sidewall spacer 15 made of silicon oxide as will be described later. On the other hand, it is formed by self-alignment. Thus, the high concentration N-type semiconductor region 16b is formed in a self-aligned manner with respect to the second sidewall spacer 15, and the high concentration N-type semiconductor region 16b does not diffuse beyond the low concentration N-type semiconductor region 10b. In addition, the performance of the N-channel MISFET Qn2 can be improved by optimizing the thickness of the second sidewall spacer 15 so as to reduce the electric field strength and to have a predetermined resistance value in the low-concentration N-type semiconductor region 10b. That is, even if the thickness of the second sidewall spacer 15 is optimized to improve the performance of the N-channel MISFET Qn2, in the memory cell array, the distance between the word lines WL in the second direction, that is, the distance between the gate electrodes 7 of the selected MISFET Qs. Since the opening of the connection holes 19 and 21 can be increased and the margin can be increased, the contact resistance can be reduced.
For example, phosphorus is implanted as an impurity into the low-concentration N-type semiconductor region 10b, and a punch-through stopper for the P-type semiconductor region is not provided therebelow. Thus, since the impurity of the low concentration N-type semiconductor region 10b of the N channel MISFET Qn2 is formed of phosphorus, the breakdown voltage can be higher than that of the N channel MISFET Qn1 in which the same low concentration N type semiconductor region 10 is formed of arsenic. Moreover, since the punch-through stopper is not provided, the withstand voltage can be increased. The N-channel MISFET Qn2 can be used for circuits that require an operation at a higher voltage than the N-channel MISFET Qn1, such as a DRAM word line driver WD, a charge pump circuit, or an input / output unit PORT.
The semiconductor regions constituting the sources and drains of the N-channel MISFET Qn1, the N-channel MISFET Qn2, and the P-channel MISFET Qp1 are connected to the connection member 31 connected to the first wiring 32 through the connection holes 30. The connection member 31 can be formed by self-alignment with the first sidewall spacer 14 made of silicon nitride formed on the side surface of the gate electrode 7 of the MISFET, if necessary. In FIG. 1, the connection region on the left side of the P-channel MISFET Qp1 corresponds.
Further, each first wiring 32 is connected to a connection member 35 connected to the second wiring 36 via the connection hole 34, and each second wiring 36 is connected to the third wiring 36 via the connection hole 38. The connection member 39 connected to the wiring 40 is connected. A passivation film 41 is formed on the upper part, and a bonding region 42 is formed in the passivation film 41.
The connection members 31, 35 and 39 for connecting the upper and lower wirings are not particularly limited, but tungsten (W) can be used. The wirings 32, 36, and 40 are not particularly limited, but can be formed of a laminated film of titanium nitride (TiN) and aluminum (Al) containing copper (Cu).
Each wiring 32, 36, 40 is insulated by insulating films 18, 23, 33, 37, and the insulating films 18, 23, 33, 37 are doped with a silicon oxide film or doped oxide containing one or both of boron and phosphorus. It can be formed of a silicon film. The passivation film 41 can be formed of a silicon oxide film, a doped silicon oxide film containing one or both of boron and phosphorus, or a silicon nitride film formed thereon.
Next, a method for manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. 5 to 25 are sectional views or plan views showing an example of the manufacturing method of the semiconductor integrated circuit device according to the first embodiment in the order of the steps.
First, as shown in FIGS. 5 and 6, a field insulating film 2 is formed in a predetermined region of a P-type semiconductor substrate 1. The field insulating film 2 can be formed by a known LOCOS (Local Oxidation of Silicon) method using a selective oxidation method using silicon nitride, or a shallow trench isolation method described below.
In the shallow trench isolation method, a silicon oxide film and a silicon nitride film (not shown) are sequentially formed on the main plane of the P-type semiconductor substrate 1. Then, after removing the silicon oxide film and the silicon nitride film in the formation region of the field insulating film 2 with a photoresist or the like, a P-type semiconductor substrate 1 is formed with a groove of, for example, 0.3 to 0.4 μm in the depth direction. . Next, thermal silicon oxide is formed on the side and bottom surfaces of the groove using the silicon nitride film as an oxidation mask. Then, after depositing a silicon oxide film on the entire surface by a CVD (Chemical Vapor Deposition) method, the silicon oxide film by the CVD method in a region other than the trench is removed by a CMP (Chemical Mechanical Polishing) method or a dry etching method, Then, silicon oxide is selectively embedded. The silicon oxide film is densified (heat treatment for densification) by the CVD method in an oxidizing atmosphere. Then, by removing the silicon nitride film, the field insulating film 2 can be formed by a shallow groove isolation method. The remaining part forms the active region 5b.
Next, as shown in FIG. 7, an N-type semiconductor region 3 is formed. The N-type semiconductor region 3 is formed by, for example, using a photoresist as a mask, phosphorus by ion implantation, acceleration energy of 500 to 1000 keV, and a dose amount of about 1 × 10 × 10. ¹² atoms / cm ² It can be formed by injecting once under the above conditions or by changing the conditions several times. Thereafter, the impurities are activated by a heat treatment at about 1000 ° C. In this case, it can be performed for about 20 to 30 minutes in a nitrogen atmosphere containing about 1% oxygen. Desirably, the impurity distribution can be controlled by performing heat treatment in a short time by an RTA (Rapid Thermal Annealing) method using infrared heating.
Next, an N-type well region 4 and a P-type well region 5 are formed. The N-type well region 4 is formed by using, for example, a photoresist as a mask and phosphorous is ion-implanted by an acceleration energy of 300 to 500 keV and a dose of about 1 × 10 × 10. ¹³ atoms / cm ² It can be formed by injecting once under the above conditions or by changing the conditions several times. The P-type well region 5 is made of, for example, a photoresist as a mask, and boron is ion-implanted by an acceleration energy of 200 to 300 keV and a dose of about 1 × 10. ¹³ atoms / cm ² It can be formed by injecting once under the above conditions or by changing the conditions several times. Thereafter, the impurities are activated by a heat treatment at about 1000 ° C. In this case, it can be performed for about 20 to 30 minutes in a nitrogen atmosphere containing about 1% oxygen. Preferably, the impurity distribution can be controlled by performing heat treatment for a short time by the RTA method.
Next, as shown in FIGS. 8 and 9, the silicon oxide film on the P-type semiconductor substrate 1 is removed, and a new clean gate insulating film 6 is formed. The gate insulating film 6 is formed by forming a silicon oxide film by a thermal oxidation method at 700 to 800 ° C., and then NO or N ₂ A gate insulating film 6 made of a silicon oxide film containing nitrogen is formed by heat treatment in a nitrogen oxide atmosphere made of O. Heat treatment in a nitrogen oxide atmosphere is 900 to 1000 ° C. in the case of NO atmosphere, N ₂ In the case of O atmosphere, it can be performed at 1000-1100 ° C. for about 20-30 minutes. Alternatively, short-time heat treatment at 1000 to 1100 ° C. is performed by the RTA method. By this heat treatment, the interface between the gate insulating film 6 and the P-type semiconductor substrate 1 is improved, and deterioration of the gate insulating film 6 due to hot carriers generated by the operation of the MISFET can be suppressed. This interface is considered to be good because a Si—N bond having a bond stronger than the Si—O bond is formed at the interface between the gate insulating film 6 and the semiconductor substrate 1.
The film thickness of the gate insulating film 6 is set so that the maximum electric field during operation is 5 MeV / cm or less. For example, 7 to 9 nm can be set when operating at 3.3 V, 5 to 7 nm when operating at 2.5 V, and 4 to 5 nm when operating at 1.8 V.
Next, the gate electrode 7 and the silicon nitride film 8 are sequentially formed. The gate electrode 7 has a multi-layer structure in which a silicide such as WSi or a metal such as W is formed on a silicon film containing impurities such as phosphorus for reducing resistance or on the silicon film. These conductor films are deposited on the entire surface by the CVD method or the sputtering method, and then the silicon nitride film 8 is deposited on the entire surface by the CVD method or the plasma CVD method. The film is sequentially patterned in a predetermined pattern. As a result, the DRAM memory cell selection MISFET Qs, N-channel MISFET Qn1, N-channel MISFET Qn2, gate electrode 7 such as P-channel MISFET Qp1, and the word line WL extending in the first direction are formed. The channel length of the gate electrode 7 is formed to be about 0.2 to 0.4 μm. A silicon nitride film 8 is formed on the gate electrode 7 and the word line WL so as to have the same plane pattern.
The channel impurity for controlling the threshold value (Vth) of the MISFET can be formed by ion implantation before the gate insulating film 6 is formed or after the gate electrode 7 is formed.
Next, as shown in FIGS. 10 and 11, the low-concentration N-type semiconductor region 9 of the selection MISFET Qs and the low-concentration N-type semiconductor region 10b of the N-channel MISFET Qn2 are selectively formed using a photoresist as a mask. The low-concentration N-type semiconductor regions 9 and 10b are formed by, for example, ion implantation using phosphorus as an acceleration energy of 20 to 40 keV and a dose of about 5 × 10. ¹³ atoms / cm ² It is formed by injecting under the following conditions. As described above, the low-concentration N-type semiconductor regions 9 and 10 b are formed by introducing impurities in a self-aligned manner with respect to the gate electrode 7 and the silicon nitride film 8. That is, the low concentration N-type semiconductor regions 9 and 10 b are formed in a self-aligned manner with respect to the gate electrode 7 and the silicon nitride film 8.
Next, the low-concentration N-type semiconductor region 10 of the N-channel MISFET Qn1 and the P-type semiconductor region 11 therebelow are selectively formed using a photoresist as a mask. The low-concentration N-type semiconductor region 10 is formed by, for example, ion implantation using arsenic with an acceleration energy of 20 to 40 keV and a dose of about 1 × 10 ¹⁴ atoms / cm ² It is formed by injecting under the following conditions. In this case, although not particularly limited, implantation can be performed with an inclination of 30 to 50 degrees with respect to the side surface of the gate electrode 7 (an inclination of 30 to 50 degrees with respect to the perpendicular of the P-type semiconductor region). As a result, the low-concentration N-type semiconductor region 10 is also formed below the gate electrode 7, so that hot carrier resistance can be improved. Thus, the low concentration N-type semiconductor region 10 is formed by introducing impurities in a self-aligned manner with respect to the gate electrode 7 and the silicon nitride film 8. That is, the low concentration N-type semiconductor region 10 is formed in a self-aligned manner with respect to the gate electrode 7 and the silicon nitride film 8.
The P-type semiconductor region 11 is formed by, for example, ion implantation using boron as an acceleration energy of 10 to 20 keV and a dose amount of about 1 × 10. ¹³ atoms / cm ² It is formed by injecting under the following conditions. In this case, although not particularly limited, implantation can be performed with an inclination of 30 to 50 degrees with respect to the side surface of the gate electrode 7 (an inclination of 30 to 50 degrees with respect to the perpendicular of the P-type semiconductor region). As a result, it is possible to sufficiently wrap around the lower portion of the low-concentration N-type semiconductor region 10, so that good short channel characteristics can be obtained.
Further, a low-concentration P-type semiconductor region 12 of the P-channel MISFET Qp1 and an N-type semiconductor region 13 therebelow are formed. The low-concentration P-type semiconductor region 12 is formed by, for example, ion implantation using boron as an acceleration energy of 5 to 10 keV and a dose amount of about 5 × 10. ¹³ atoms / cm ² It is formed by injecting under the following conditions. In this case, although not particularly limited, implantation can be performed with an inclination of 30 to 50 degrees with respect to the side surface of the gate electrode 7 (an inclination of 30 to 50 degrees with respect to the perpendicular of the P-type semiconductor region). The N-type semiconductor region 13 is formed by, for example, ion implantation using phosphorus as an acceleration energy of 50 to 80 keV and a dose of about 1 × 10 ¹³ atoms / cm ² It is formed by injecting under the following conditions. In this case, although not particularly limited, implantation can be performed with an inclination of 30 to 50 degrees with respect to the side surface of the gate electrode 7 (an inclination of 30 to 50 degrees with respect to the perpendicular of the P-type semiconductor region). As a result, it is possible to sufficiently wrap around the lower portion of the low-concentration P-type semiconductor region 12, so that good short channel characteristics can be obtained.
Thereafter, the impurities are activated by a heat treatment at about 850 ° C. In this case, it is performed for about 20 to 30 minutes in a nitrogen atmosphere containing about 1% oxygen. Desirably, the impurity distribution can be controlled by performing a short-time heat treatment at about 1000 ° C. by the RTA method.
Preferably, heat treatment can be performed in an oxidizing atmosphere at about 700 to 800 ° C. before forming each of the low-concentration semiconductor regions. Thereby, the edge part of the gate electrode 7 which became thin at the time of patterning of the gate electrode 7 can be reinforced, so that the gate breakdown voltage can be improved.
Next, as shown in FIGS. 12 and 13, first sidewall spacers 14 made of silicon nitride are formed on the side surfaces of the gate electrode 7 and the silicon nitride film 8. The first sidewall spacer 14 can be formed by depositing a silicon nitride film on the entire surface by CVD or plasma CVD and then etching by anisotropic dry etching. The thickness of the first sidewall spacer 14 made of silicon nitride is formed below the gate electrode 7 so that the thickness t1 in the channel length direction (second direction) is about 0.04 to 0.08 μm. As a result, the gate electrode 7 is covered with the first sidewall spacer 14 having the upper portion made of the silicon nitride film 8 and the side surface made of the silicon nitride film, and the self-aligned connection holes are formed when the connection holes 19 and 21 described later are opened. Can be realized. Further, since the thickness t1 of the first sidewall spacer 14 can be formed as thin as about 0.04 to 0.08 μm, the distance between the gate electrodes 7 of the selection MISFETs Qs in the second direction can be reduced to reduce the semiconductor integrated circuit. High integration of the device can be achieved.
Alternatively, the first sidewall spacer 14 made of silicon nitride may be thinly formed, and the low-concentration semiconductor region may be formed after the formation of the first sidewall spacer 14. In this case, the characteristics of a shorter channel can be obtained. That is, as shown in FIG. 48, after the first sidewall spacer 14 is formed, the low-concentration N-type semiconductor regions 9, 10, 10b and the low-concentration P-type semiconductor region 12 are formed on the first side as shown in FIG. By forming in a self-aligned manner with respect to the wall spacer 14, it is formed in a self-aligning manner with respect to the first sidewall spacer 14.
Next, as shown in FIGS. 14 and 15, the second sidewall spacer 15 made of silicon oxide is formed on the side surface of the first sidewall spacer 14. The second sidewall spacer 15 can be formed by depositing a silicon oxide film on the entire surface by CVD or plasma CVD and then etching by anisotropic dry etching. The thickness (width) of the second sidewall spacer 15 is made larger than that of the first sidewall spacer 14. The total thickness t2 of the first sidewall spacer 14 made of silicon nitride and the second sidewall spacer 15 made of silicon oxide is about 0.1 to 0.15 μm in the channel direction below the gate electrode 7. It forms so that it may become. At this time, even if the gap between the two gate electrodes 7 of the selection MISFET Qs in the second direction is filled with the second sidewall spacer 15 made of silicon oxide, there is no problem as will be described later. That is, it is sufficient if there is a gap (space) t3 between the first sidewall spacers 14 made of silicon nitride. That is, since the connection holes 19 and 21 can be opened in a self-aligned manner with respect to the first sidewall spacer 14, as shown in FIG. 13, the interval t3 between the first sidewall spacers 14 in the second direction is the connection hole. 19, 21 openings. That is, the thickness t1 of the first sidewall spacer 14 is made sufficiently small to reduce the thickness t1 in the second direction, and the interval t3 between the first sidewall spacers 14 can take a predetermined contact resistance. Can be made as small as possible.
Next, as shown in FIG. 16, a high-concentration N-type semiconductor region 16 of the N-channel MISFET Qn1 and a high-concentration N-type semiconductor region 16b of the N-channel MISFET Qn2 are formed. The high-concentration N-type semiconductor regions 16 and 16b are formed by, for example, ion implantation using arsenic with acceleration energy of 20 to 60 keV and a dose of about 1 to 5 × 10 ¹⁵ atoms / cm ² It is formed by injecting under the following conditions. At this time, a high concentration semiconductor region is not formed in the selection MISFET Qs. As a result, it is possible to suppress crystal defects caused by ion implantation when forming a high-concentration semiconductor region, and to prevent the occurrence of a problem that the leakage current of the PN junction increases and the refresh time of the DRAM is shortened.
Further, a high concentration P-type semiconductor region 17 of the P channel MISFET Qp1 is formed. The high-concentration P-type semiconductor region 17 is formed by, for example, ion implantation using boron as an acceleration energy of 10 to 20 keV and a dose of about 1 to 5 × 10. ¹⁵ atoms / cm ² It is formed by injecting under the following conditions. Thereafter, the impurities are activated by a heat treatment at about 850 ° C. In this case, it is performed for about 20 to 30 minutes in a nitrogen atmosphere containing about 1% oxygen. Desirably, the impurity distribution can be controlled by performing a short-time heat treatment at about 1000 ° C. by the RTA method.
As described above, since the second sidewall spacer 15 is provided and a high-concentration semiconductor region can be formed with the optimum sidewall spacer length t2, high-performance N-channel MISFETs Qn1, Qn2 and P-channel MISFET Qp1 can be obtained. On the other hand, in the memory array, the thickness t1 of the first sidewall spacer 14 can be reduced, and the interval t3 between the first sidewall spacers 14 can be reduced, so that miniaturization in the second direction can be achieved, and The opening margin of the connection holes 19 and 21 can be increased, and the contact resistance can be reduced.
Next, as shown in FIGS. 17 and 18, an insulating film 18 made of a silicon oxide film or a doped silicon oxide film containing one or both of boron and phosphorus is formed. The insulating film 18 is formed by depositing a silicon oxide film or a doped silicon oxide film containing one or both of boron and phosphorus on the entire surface by, eg, CVD or plasma CVD, and then reflowing or CMP from the surface of the substrate over the entire surface. Flattening so that the height of the is uniform.
Further, a connection hole 19 is formed for connection to one electrode of the storage capacitor element C for information storage of the DRAM memory cell. The connection hole 19 is formed by dry etching, and includes a first sidewall spacer 14 made of silicon nitride film 8 and silicon nitride on the gate electrode 7, a second sidewall spacer 15 made of silicon oxide, and an insulating film 18 made of silicon oxide. This is performed under the condition that the selection ratio is increased. That is, the etching is performed under the etching conditions in which the etching rate (etching amount) of silicon nitride is low and the etching rate (etching amount) of silicon oxide is high. Such etching can be performed by, for example, C _Four F ₈ And O ₂ This can be achieved by using Ar sputtering together with the mixed gas. By performing etching under such conditions, the connection hole 19 can be opened in a self-aligned manner with respect to the first sidewall spacer 14. That is, since the connection hole 19 is formed using photolithography, the alignment margin in the second direction can be reduced, and miniaturization can be achieved in the second direction.
Further, a polycrystalline silicon film containing impurities such as phosphorus for reducing the resistance is formed on the entire surface of the semiconductor substrate 1. Then, the polycrystalline silicon film other than the connection hole 19 is removed by anisotropic etching, and a conductor 20 is formed in the connection hole 19.
Next, an insulating film (silicon oxide film) (not shown) is deposited to cover the conductor 20.
Next, as shown in FIGS. 19 and 20, a connection hole 21 for connecting to the bit line BL of the memory cell of the DRAM is formed. The connection hole 21 is formed by dry etching under the condition that the selection ratio between silicon nitride and silicon oxide is increased as in the case of the connection hole 19. Thereby, the connection hole 21 can be opened with self-alignment with respect to the first sidewall spacer 14. Thereby, like the connection hole 19, when forming the connection hole 21 using optical lithography, the alignment margin in a 2nd direction can be made small and refinement | miniaturization can be achieved in a 2nd direction.
Further, a silicon film containing an impurity such as phosphorus or a silicide film such as WSi is formed to reduce the resistance. Then, using the photoresist as a mask, the conductor 22 is formed in the connection hole 21 and is patterned to extend in the direction (second direction) perpendicular to the word line WL to become the bit line BL.
Next, as shown in FIGS. 21 and 22, an insulating film 23 made of silicon oxide or doped silicon oxide containing both or one of boron and phosphorus is formed. The insulating film 23 is formed by depositing a silicon oxide film or a doped silicon oxide film containing both or one of boron and phosphorus on the entire surface by, for example, the CVD method or the plasma CVD method in the same manner as the insulating film 18, and then performing reflow or CMP. By this method, the entire surface is flattened so that the height from the substrate surface is uniform. Then, a connection hole 24 for connecting to one electrode of the storage capacitor element C for information storage of the DRAM memory cell is formed. The connection hole 24 is etched by dry etching to form a hole reaching the conductor 20. Such etching is CF _Four And CHF _Three This can be achieved by using Ar sputtering together with the mixed gas.
Further, a conductor 25 is formed which becomes one electrode of the information storage capacitor C of the DRAM memory cell. The conductor 25 is formed of a polycrystalline silicon film containing impurities such as phosphorus for reducing the resistance or a silicide film such as WSi. Next, an insulating film 26 made of, for example, silicon oxide is formed, a conductor 25 is formed in the connection hole 24 using a photoresist as a mask, and the insulating film 26 and the conductor 25 are connected to the storage capacitor element C for information storage. Patterning to be one electrode.
Next, as shown in FIG. 23, a polycrystalline silicon film containing an impurity such as phosphorus or a silicide film such as WSi is formed to reduce resistance. Then, by performing anisotropic dry etching, a conductor 27 connected to the conductor 25 is formed on the side surface of the insulating film 26. The conductor 25 and the conductor 27 form one electrode of the information storage capacitor C.
Next, as shown in FIG. 24, after the insulating film 26 is removed, the dielectric film 28 and the upper electrode 29 of the information storage capacitor C are sequentially formed. The dielectric film 28 is a laminated film made of silicon oxide and silicon nitride, or tantalum oxide (Ta ₂ O _Three ) Form with film. The upper electrode 29 is formed with a polycrystalline silicon film containing an impurity such as phosphorus or a silicide film such as WSi for reducing the resistance.
Next, as shown in FIG. 25, a connection hole 30 for connecting the first wiring 32 and the gate electrode or the semiconductor region is formed. Similarly to the formation of the connection holes 19 and 21, the connection holes 30 are the first sidewall spacer 14 made of the silicon nitride film 8 or silicon nitride, the second sidewall spacer 15 made of silicon oxide, and the insulating film made of silicon oxide. 18 under the condition that the selection ratio to 18 is increased. Then, a connection member 31 is formed in the connection hole 30. The connection member 31 is formed by, for example, forming a titanium (Ti) film with a thickness of 10 to 50 nm and a titanium nitride (TiN) film with a thickness of about 100 nm by a sputtering method, then forming a tungsten (W) film by a CVD method, and connecting by dry etching or CMP method. The tungsten film other than the holes 30 is removed.
Further, the first wiring 32 is formed. The first wiring can be formed of a laminated film of a titanium nitride (TiN) film and an aluminum (AL) film containing copper (Cu) by a sputtering method.
Finally, the insulating film 33, the connecting hole 34, the connecting member 35, the second wiring 36, the insulating film 37, the connecting hole 38, the connecting member 39, and the second wiring 40 are sequentially formed. The insulating films 33 and 37 are formed in the same manner as the insulating film 23. The connection holes 34 and 38 are formed in the same manner as the connection hole 30. The connection members 35 and 39 and the second wiring 36 and the third wiring 40 are formed in the same manner as the connection member 31 and the first wiring 32. Then, after a passivation film 41 made of silicon nitride or silicon oxide is formed by plasma CVD, a bonding region 42 is formed, and the semiconductor integrated circuit device shown in FIG. 1 is almost completed.
(Embodiment 2)
FIG. 26 is a cross-sectional view showing an example of a semiconductor integrated circuit device according to another embodiment of the present invention.
The semiconductor integrated circuit device of the second embodiment is different from the semiconductor integrated circuit device of the first embodiment in that a silicon nitride film 104 is formed on the N channel MISFET Qn1, the N channel MISFET Qn2, and the P channel MISFET Qp1, and this nitriding The silicon film 104 is used as an etching stopper when the connection hole 30 is formed. Therefore, the other configuration is the same as that of the first embodiment, and thus the description thereof is omitted. In the semiconductor integrated circuit device of the second embodiment, since the silicon nitride film 104 is provided, even if a part of the connection hole 30 overlaps the field insulating film 2 as shown on the right side of the P channel MISFET Qp1 in FIG. The field insulating film 2 is not excessively etched when the connection hole 30 is opened, and a leak current or the like due to excessive etching is not generated, and the performance and reliability of the semiconductor integrated circuit device can be maintained. .
An example of a method for manufacturing the semiconductor integrated circuit device according to the second embodiment will be described with reference to FIGS. 27 to 29 are cross-sectional views showing an example of the manufacturing method of the semiconductor integrated circuit device according to the second embodiment in the order of steps.
Similar to the manufacturing method of the first embodiment, after forming the selection MISFET Qs, the N channel MISFETs Qn1, Qn2, and the P channel MISFET Qp1 shown in FIG. A silicon nitride film 104 is deposited. Next, using the photoresist or the like as a mask, at least the silicon nitride film 104 in the region where the connection holes 19 and 21 of the DRAM memory cell are to be formed is removed. (FIG. 27).
Thereafter, the process is the same as in the first embodiment until the insulating film 18, the bit line BL, and the information storage capacitor C are formed. Thereafter, when the connection hole 30 is opened, first stage etching is performed (FIG. 28). In the first-stage etching, etching is performed under the condition that the etching rate of silicon oxide is high with respect to silicon nitride and the so-called etching selectivity is increased. Thereby, the connection hole 30 can be reliably opened to the upper surface of the silicon nitride film 104. In addition, since the silicon nitride film 104 acts as an etching stopper during the first stage etching, there is no need to consider the risk of overetching, and etching is performed for a sufficient time to increase the process margin. Can do.
Next, a second stage etching is performed to etch the silicon nitride film 104 on the bottom surface of the connection hole 30 (FIG. 29). This second stage etching condition is a condition in which silicon nitride is etched, but it is not necessary to have an etching selectivity with respect to silicon oxide. The etching amount at this time is slightly larger than the film thickness of the silicon nitride film 104. For example, the thickness is set to 110 to 130% of the thickness of the silicon nitride film 104. Such etching is CF _Four And CHF _Three This can be achieved by using Ar sputtering in combination. As a result, the field insulating film 2 is hardly etched. Thus, the bottom surface of the etched connection hole 30 does not come to a position deeper than the semiconductor region constituting the source and drain. That is, the film thickness of the silicon nitride film 104 can be made sufficiently thin with respect to the film thickness of the field insulating film 2, and even if over-etching is performed to sufficiently etch the silicon nitride film 104, The amount by which the field insulating film 2 is etched is at most half or less of the film thickness of the silicon nitride film 104, and such over-etching hardly causes a problem in the process.
By performing two-stage etching using the silicon nitride film 104 in this way, the connection hole 30 can be reliably opened with a sufficient process margin, and the performance and reliability of the semiconductor integrated circuit device can be maintained. Is possible.
Since the subsequent manufacturing method is the same as that of the first embodiment, the description thereof is omitted.
(Embodiment 3)
FIG. 30 is a cross-sectional view showing the main part of an example of a semiconductor integrated circuit device according to still another embodiment of the present invention.
The semiconductor integrated circuit device according to the third embodiment differs from the first and second embodiments except at least the low-concentration N-type semiconductor region 9 constituting the source and drain of the memory cell selection MISFET Qs of the DRAM. The silicide layer 105 is formed on the semiconductor region. In the third embodiment, a silicon nitride film 104 is also provided as in the second embodiment. As a result, the parasitic resistance of the semiconductor regions constituting the sources and drains of the MISFETs Qn1, Qn2, Qp1 can be reduced and the performance of the MISFETs Qn1, Qn2, Qp1 can be improved without increasing the leakage current of the DRAM memory cells.
Next, an example of a method for manufacturing the semiconductor integrated circuit device according to the third embodiment will be described with reference to FIGS. 31 to 33 are cross-sectional views showing an example of the manufacturing method of the semiconductor integrated circuit device according to the third embodiment in the order of steps.
First, similarly to the first embodiment, the high concentration N-type semiconductor regions 16 and 16b and the high concentration P-type semiconductor region 17 shown in FIG. Next, after the insulating film 106 is formed, at least the insulating film 106 other than the memory cell of the DRAM is removed using a photoresist or the like as a mask (FIG. 31). Note that in the case where an insulating film is formed over the semiconductor region before the insulating film 106 is formed, the insulating film 106 can be selectively removed without being formed.
Next, a metal film 107 made of, for example, titanium (Ti) or cobalt (Co) is deposited on the entire surface by sputtering or the like (FIG. 32). Next, after the first silicide reaction is performed in an inert atmosphere of about 500 ° C., the unreacted metal film 107 other than the semiconductor region is removed. Next, a second silicide reaction is performed in an inert atmosphere at 700 to 900 ° C. to lower the resistance, and a silicide layer 105 is formed (FIG. 33). Thereby, the silicide layer 105 is formed on the semiconductor regions constituting the sources and drains of the MISFETs Qn1, Qn2 and Qp1 except for the low-concentration N-type semiconductor regions 9 constituting the source and drain of the selection MISFET Qs of the DRAM memory cell. Note that the silicide layer 105 does not have to be provided on the semiconductor regions constituting the source and drain of the output MISFET of the output circuit and the input protection MISFET.
Subsequent steps are the same as those in FIG. 27 and subsequent steps in the second embodiment, and a description thereof will be omitted.
(Embodiment 4)
FIG. 34 is a cross sectional view showing an example of a semiconductor integrated circuit device according to another embodiment of the present invention.
The semiconductor integrated circuit device of the fourth embodiment is an example in which a flash memory is used as a ROM in the block diagram of FIG. 3 of the first embodiment. In FIG. This is the same as the first region A and the region B. Therefore, the description of the corresponding part is omitted.
FIG. 35 is an enlarged view of region C and region D in FIG. FIG. 36 is a plan view of a memory array region of an electrically rewritable batch erasable nonvolatile memory so-called flash memory included in the semiconductor integrated circuit device of the fourth embodiment, and FIG. It is an equivalent circuit diagram of the part. This will be described below with reference to FIGS.
In the flash memory according to the fourth embodiment, a 1-bit memory cell includes a tunnel insulating film 202, a floating gate electrode 203, an interlayer insulating film 204, a control gate electrode 7 formed integrally with a word line, and a P-type well region 5 ( A floating gate type MISFET Qf having a channel forming region) and a pair of N type semiconductor regions constituting a source and a drain.
The source of the floating gate type MISFET Qf is formed of a low concentration N type semiconductor region 10 similar to the N channel MISFET Qn1 in the first embodiment, a P type semiconductor region 11 and a high concentration N type semiconductor region 16 therebelow. The drain of the floating gate type MISFET Qf is formed from the high concentration N type semiconductor region 205. The thickness of the tunnel insulating film 202 is set to 9 to 10 nm. The high-concentration N-type semiconductor region 205 has a higher impurity concentration than the low-concentration N-type semiconductor region 10, and the surface of the high-concentration N-type semiconductor region 205 is depleted under the floating gate electrode 203 when information is written. The impurity concentration is high enough to reduce the generation of the impurity.
The drain of the floating gate type MISFET Qf is connected to the first wiring 32 through the connection hole 30. In the fourth embodiment, the first wiring 32 forms a sub bit line subBL. In the sub-bit line subBL, 16-bit to 64-bit memory cells are connected to the main bit line BL including the second wiring 36 via the selection MISFET Qsf. That is, the flash memory according to the fourth embodiment is divided into blocks by the selection MISFET Qsf. The block selection lines tWL1 and tWL2 are configured integrally with the gate electrode 203 of the selection MISFET Qsf.
The source of the memory cell is connected to the source line SL through the connection hole 21 and connected to the block common source line BSL for each of the divided units.
A block is selected by a selection MISFET Qsf. That is, the potential of the main bit line BL is supplied to the memory cell via the selection MISFET Qsf. As shown in FIG. 36, the word line MWL (7), the block selection lines tWL1 and tWL2, and the source line SL extend in the first direction, and the sub bit line subBL (32) extends in the second direction. .
The selection MISFET Qsf includes a gate insulating film 201, a gate electrode 203 in the same layer as the floating gate electrode 203, and a high-concentration N-type semiconductor region 205 constituting a source and a drain. Although the gate electrode has a two-layer structure in FIG. 34, the control gate electrode 7 formed integrally with the word line in the region not shown is connected to the first wiring 32 and further shunted by the third wiring 40. ing. The film thickness of the gate insulating film 201 is set to about 20 nm.
As shown in FIGS. 45 and 46, which will be described later, the connection holes 21 and 30 for connecting to the source and drain of the floating gate type MISFET Qf are the same as the connection holes 19 and 21 of the first embodiment and are made of silicon nitride. It is formed in a self-aligned manner with respect to the one sidewall spacer 14. These memory cells are separated by an N-type semiconductor region 3 in order to perform writing and erasing operations described below.
Writing in the flash memory of the present invention is performed by emitting electrons from the floating gate electrode 203 to lower the threshold value (Vth). That is, a negative voltage of about 9 V is applied to the control gate electrode 7. Then, by applying a positive voltage of about 7 V to the drain, an electron is discharged from the floating gate electrode 203 to the high-concentration N-type semiconductor region 205 by the FN (Fowler-Nordheim) tunnel through the tunnel insulating film. Decrease the value (Vth).
Erasing is performed by injecting electrons into the floating gate electrode 203 to raise the threshold value. That is, a positive voltage of about 9 V is applied to the control gate electrode 7. Then, by applying a negative voltage of about 9 V to the source and the P-type well region 5, electrons are injected from the inversion layer formed in the channel region into the floating gate electrode by the FN tunnel through the tunnel insulating film, and the threshold value is set. increase.
The N channel MISFET Qn3 and the P channel MISFET Qp2 are MISFETs used in a circuit for writing and erasing the flash memory.
With such a semiconductor integrated circuit device, even when a flash memory is mounted, the first sidewall spacer 14 and the second sidewall spacer 15 are formed to make the memory cell region finer, and the MISFETs Qn1, Qn2, Qn3 in the peripheral circuit region are formed. , Qp1 and Qp2 can be formed, and the miniaturization and performance improvement of the semiconductor integrated circuit device can be realized.
Next, an example of a method for manufacturing the semiconductor integrated circuit device according to the fourth embodiment will be described with reference to FIGS. 38 to 46 are cross-sectional views or plan views showing an example of the manufacturing method of the semiconductor integrated circuit device according to the fourth embodiment in the order of steps.
First, as in the first embodiment, a field insulating film 2, an N-type semiconductor region 3, an N-type well region 4 and a P-type well region 5 are formed. FIG. 38 is a plan view of the flash memory area after the field insulating film 2 is formed.
Next, as shown in FIGS. 39 and 40, a gate insulating film 201 is formed by a thermal oxidation method. Then, after removing the gate insulating film 201 other than the selection MISFET Qsf, the N channel MISFET Qn3 and the P channel MISFET Qp2, a tunnel insulating film 202 is newly formed by a thermal oxidation method. By forming the tunnel insulating film 202 after removing the gate insulating film 201 in this manner, the tunnel insulating film 202 having a thickness smaller than that of the gate insulating film 201 can be easily formed. Then, a conductor 206 is formed which becomes the floating gate electrode 203 of the flash memory, the selection MISFET Qsf, the floating gate electrode 203 of the N channel MISFET Qn3 and the P channel MISFET Qp2. The conductor 206 is formed of a silicon film into which impurities such as phosphorus for reducing resistance are implanted. Thereafter, patterning is performed using a photoresist as a mask.
Next, as shown in FIG. 41, an interlayer insulating film 204 between the floating gate electrode 203 and the control gate electrode 7 of the flash memory is formed. The interlayer insulating film 204 is formed of a multilayer film in which a silicon oxide film and a silicon nitride film are sequentially stacked. Next, the interlayer insulating film 204 in the region where the DRAM memory cell selection MISFET Qs, N channel MISFET Qn1, N channel MISFET Qn2 and P channel MISFET Qp1 are formed is selectively removed. Then, using the silicon nitride film above the interlayer insulating film 204 as an oxidation resistant mask, the gate insulating film 6 is formed in the same manner as in the first embodiment.
Next, as shown in FIGS. 42 and 43, the control gate electrode 7 and the silicon nitride film 8 thereabove are formed, and patterning is performed using a photoresist as a mask. Thereby, the floating gate electrode 203 and the control gate electrode 7 of the flash memory are formed.
Subsequent steps are substantially the same as the steps after FIG. 10 in the first embodiment. That is, as shown in FIG. 44, the first sidewall spacer 14 and the second sidewall spacer 15 are formed in the memory cell region of the DRAM and at the same time in the memory cell region of the flash memory. Thereby, a process can be shortened.
Next, after forming the insulating film 18 in the same manner as in the first embodiment, the connection hole 21 is formed as shown in FIG.
Next, after forming the insulating film 23, as shown in FIG. 46, the connection hole 30 is formed.
Since the connection holes 21 and 30 are formed in a self-aligned manner with respect to the first sidewall spacer 14 made of silicon nitride, like the connection holes 19 and 21 of the first embodiment, the word lines WL in the second direction are formed. The interval t3 between the (gate electrode 7), the interval t3 between the word line WL (gate electrode 7) and the block selection lines tWL1 and tWL2, and the interval t3 between the block selection lines tWL1 and tWL2 can be reduced. It can be miniaturized.
In addition, since the alignment margin in the second direction can be reduced, miniaturization in the second direction can be achieved. That is, the interval between the memory cells in the second direction can be reduced, and high integration can be achieved.
Next, the first wiring 32 is formed in the same manner as in the first embodiment. Thereby, the bit line BL of the DRAM memory cell and the source line SL of the flash memory can be formed in the same process, so that the process can be shortened.
According to the semiconductor integrated circuit device manufacturing method of the fourth embodiment, a semiconductor integrated circuit device on which a flash memory is mounted can be manufactured in the same manner as in the first embodiment, and the memory cell array is highly integrated in the flash memory. can do. Further, the film thickness of the gate insulating film can be changed according to the requirements of the MISFET.
Needless to say, the silicon nitride film 104 or the silicide layer 105 described in the second to third embodiments may be combined with the semiconductor integrated circuit device and the manufacturing method according to the fourth embodiment. In the fourth embodiment, the semiconductor integrated circuit device having both the DRAM and the flash memory has been described. Needless to say, the present invention can also be applied to a semiconductor integrated circuit device having only the flash memory.
(Embodiment 5)
FIG. 47 is a cross-sectional view showing an example of a semiconductor integrated circuit device according to still another embodiment of the present invention.
The semiconductor integrated circuit device of the fifth embodiment is different from the semiconductor integrated circuit device of the first embodiment in that a silicon nitride film (first sidewall spacer) 207 is formed instead of the first sidewall spacer 14. Is a point. Therefore, the other configuration is the same as that of the first embodiment, and thus the description thereof is omitted. In the semiconductor integrated circuit device of the fifth embodiment, since the silicon nitride film (first sidewall spacer) 207 having the thickness t1 is provided, the degree of integration of the memory cell region is improved as in the first embodiment. The second sidewall spacer 15 can optimize the LDD structure of the MISFET other than the memory cell region and improve the performance of the semiconductor integrated circuit device.
Note that, in the manufacturing method of the semiconductor integrated circuit device of the fifth embodiment, a silicon nitride film 207 is deposited on the entire surface of the semiconductor substrate 1 instead of the step of forming the first sidewall spacer 14 of FIG. 12 in the first embodiment. This can be done by replacing the process to do. For this reason, processes, such as anisotropic etching, are abbreviate | omitted and a process can be simplified. However, in the process of opening the connection holes 19 and 21, two-stage etching as described in the second embodiment is required. For this reason, although the number of steps is increased, the semiconductor substrate 1 on the bottom surfaces of the connection holes 19 and 21 is not excessively etched, and the contact can be made highly reliable.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
For example, in the first to fifth embodiments, the example in which the peripheral circuit or the logic circuit is configured by the complementary (complementary) MISFET has been described. However, the peripheral circuit or the like may be configured only by the N-channel MISFET or the P-channel MISFET. .
In the first to fifth embodiments, the gate insulating film of the selection MISFET Qs in the DRAM memory cell region has the same thickness as the gate insulating films of the N channel MISFETs Qn1, Qn2 and P channel MISFET Qp1. Although shown, these gate insulating films may have different thicknesses. In particular, if the thickness of the gate insulating film of the N-channel MISFETs Qn1, Qn2 and P-channel MISFET Qp1 is made smaller than the thickness of the gate insulating film of the selected MISFET Qs, the N-channel MISFETs Qn1, Qn2 and the P-channel MISFET Qp1 can be further shortened. Thus, the performance of the semiconductor integrated circuit device can be further improved. As a method for manufacturing the gate insulating film at this time, a manufacturing method similar to the method of forming the gate insulating films of the flash memory region and the DRAM region described in the fourth embodiment in separate steps can be used.
The memory cells of the first to fifth embodiments have been described using a flash memory that is a DRAM or a nonvolatile memory. However, the present invention is not limited to this, and an SRAM (Static RAM), a mask ROM, etc., for example, between word lines Of course, the present invention may be applied to a memory cell structure in which a conductive pair is connected to the source or drain region of the MISFET in a self-aligning manner using a side wall spacer.
(Embodiment 6)
FIG. 50A is a cross-sectional view showing an example of a DRAM according to an embodiment of the present invention for the memory cell region, and FIG. 50B is a cross-sectional view showing the peripheral circuit region. FIG. 51 is a plan view of the memory cell region of the DRAM of the sixth embodiment. 52 is a cross-sectional view of the memory cell region of the DRAM of the sixth embodiment. FIG. 52A is a cross-sectional view taken along line IIIa-IIIa in FIG. 51, and FIG. 52B is a cross-sectional view taken along line IIIb-IIIb in FIG. Indicates. In FIG. 51, in order to make the drawing easy to see, some members are hatched or indicated by broken lines, and the Ia-Ia line in FIG. 51 is a cut portion of the cross-sectional view shown in FIG. Indicates.
In the memory cell region of the DRAM of the sixth embodiment, a memory cell selection MISFET Qt is formed on the main surface of the semiconductor substrate 301, and a charge storage capacitor element and a bit line BL connected to the selection MISFET Qt are provided. Is formed.
An n-type MISFET Qn constituting the peripheral circuit is formed in the peripheral circuit region of the DRAM. Note that a p-type MISFET (not shown) may be formed in the peripheral circuit, and the n-type MISFET Qn and the p-type MISFET may constitute the CMISFET. In addition to the n-type MISFET Qn, a high breakdown voltage n-type MISFET (not shown) may be formed.
The semiconductor substrate 301 is, for example, p ^- The main surface is formed with a shallow groove 302a. The shallow groove 302a has, for example, silicon dioxide (SiO 2). ₂ The element isolation insulating film 302b is embedded to form a shallow groove element isolation region.
A p-well 303 is formed on the semiconductor substrate 301. For example, boron of a p-type impurity is introduced into the p well 303. A deep well 303b is formed below the p well 303 in the region where the memory cell selection MISFET Qt is formed. An n-type impurity phosphorus is introduced into the deep well 303b, and the selection MISFET Qt can be insulated from the substrate potential to improve noise resistance.
When a p-type MISFET is formed, an n-well (not shown) into which, for example, phosphorus is introduced is formed in a region where the p-type MISFET is formed. In addition, a MISFET threshold control layer may be formed in the p-well 303 and the n-well when it exists.
The memory cell selection MISFET Qt is formed on the active region surrounded by the element isolation insulating film 302b, and two selection MISFETs Qt are formed in one active region. The selection MISFET Qt includes a polycrystalline silicon film 305a and tungsten silicide (WSi) formed on the semiconductor substrate 301 through a gate insulating film 304 formed on the active region of the p well 303. ₂ ) And a pair of n-type semiconductor regions 306a and 306b formed in the p-well 303 on both sides of the gate electrode 305 so as to be separated from each other.
The gate electrode 305 functions as a DRAM word line WL. In addition, although n-type impurities are introduced into the n-type semiconductor regions 306a and 306b, either phosphorus or arsenic (As) impurities may be introduced. However, it is preferable to introduce phosphorus in order to improve the channel breakdown voltage of the selection MISFET Qt and improve the refresh characteristics of the DRAM.
The n-type semiconductor region 306a is shared by the two selection MISFETs Qt, and the channel region of the selection MISFET Qt is formed between the n-type semiconductor regions 306a and 306b. For example, the gate insulating film 304 is made of SiO. ₂ The insulating breakdown voltage of the selection MISFET Qt may be improved by making it thicker than the gate insulating film 304 of the n-type MISFET Qn in the peripheral circuit region described later. In such a case, the withstand voltage of the selection MISFET Qt is improved, and the refresh characteristics of the DRAM can be improved.
The upper surface of the gate electrode 305 (which is also the word line WL) is made of, for example, SiO. ₂ A cap insulating film 307b made of, for example, silicon nitride is formed through an insulating film 307a made of. The cap insulating film 307b functions as a blocking film for opening the connection holes in a self-aligned manner with respect to the gate electrode 305 in the opening process of the connection holes 311a and 311b described later. This is to prevent a short circuit between the gate electrode 305 and the gate electrode 305.
The upper surface of the cap insulating film 307b, the side surface of the gate electrode 305, and the main surface of the semiconductor substrate 301 are covered with a self-aligning processing insulating film 309 made of, for example, a silicon nitride film, except for the bottom surfaces of the connection holes 311a and 311b. . The insulating film for self-alignment processing 309 functions as an etching stopper when the connection hole 311a and the connection hole 311b are opened in a self-alignment manner with respect to the word line, and the semiconductor when the connection hole 311a and the connection hole 311b are opened. It has an effect of preventing excessive etching of the substrate 301, particularly the element isolation insulating film 302b.
Note that, for example, SiO at the interface between the side surface of the gate electrode 305 and the insulating film 309 for self-alignment processing. ₂ An insulating film (not shown) may be formed. Such an insulating film and the insulating film 307a are formed by the WSi used when forming the cap insulating film 307b and the self-alignment processing insulating film 309. ₂ The film 305b is provided to prevent contamination of the film forming apparatus with the metal constituting the film 305b and to relieve thermal stress on the cap insulating film 307b and the self-aligning insulating film 309.
The self-alignment processing insulating film 309 is covered with an interlayer insulating film 310a made of, for example, SOG (Spin On Glass). The interlayer insulating film 310a may be BPSG (Boro Phospho Silicate Glass), but is a silicon oxide film that can ensure an etching selectivity with respect to the silicon nitride film. The interlayer insulating film 310a has a connection hole 311a that exposes the n-type semiconductor region 306a in the upper layer portion of the semiconductor substrate 301 and a connection hole 311b that exposes the n-type semiconductor region 306b in the upper layer portion of the semiconductor substrate 301. Is formed.
As described above, the cap insulating film 307b and the self-alignment processing insulating film 309 can act as an etching stopper when the connection hole 311a and the connection hole 311b are opened in a self-alignment manner. Further, a self-alignment processing insulating film 309 is formed, and as will be described later, the connection hole 311a and the connection hole 311b are easily etched by the interlayer insulating film 310a (the etching amount and the etching speed are large). 309 is difficult to etch (low etching amount and low etching rate) The first etching process and the self-aligning insulating film 309 are easily etched, and the interlayer insulating film 310a or the silicon substrate or the element isolating insulating film 302b is difficult to etch. Since the opening is performed by two-stage etching with the second etching process under conditions, the bottoms of the connection hole 311a and the connection hole 311b are removed from the active region of the semiconductor substrate 301 as shown in FIGS. 52 (a) and (b). Even in the case where a part of the element isolation insulating film 302b is applied, Excessive etching of the connection hole 311a and the connection hole 311b of the bottom in such isolation insulating film 302b can be prevented, the bottom of the connection hole 311a and the contact hole 311b is does not lead to deep region of the isolation insulating film 302b. In other words, even if the element isolation insulating film 302b is excessively etched, it can be suppressed to an excessive etching that does not cause a problem in the process, for example, equivalent to or less than the film thickness of the insulating film 309 for self-alignment processing.
In the connection hole 311b, for example, a plug 314 made of polycrystalline silicon into which phosphorus is introduced at a high concentration is formed. The bottom surface of the plug 314 is also formed in a region where the element isolation insulating film 302b is excessively etched, but the depth thereof is not a problem in the process as described above, and the performance such as the refresh characteristics of the DRAM. There is almost no problem.
An interlayer insulating film 310b is formed on the interlayer insulating film 310a and the plug 314. Interlayer insulating film 310b can be a silicon oxide film deposited by thermal CVD using, for example, TEOS (tetraethoxysilane).
A bit line BL is formed on the interlayer insulating film 310b. The bit line BL is formed of a polycrystalline silicon film 312 and WSi. ₂ The film 313 is configured and electrically connected to the n-type semiconductor region 306a through the connection hole 311a. Similar to the plug 314, the bottom surface of the polycrystalline silicon film 312 is also formed in a region where the element isolation insulating film 302b is excessively etched, but its depth does not cause a problem in the process as described above. And there is almost no problem with the performance of the DRAM.
This bit line BL is covered with an interlayer insulating film 310c made of a silicon oxide film deposited by, for example, TEOS using a thermal CVD method. Further, the upper layer of the interlayer insulating film 310c is polished and planarized by, for example, a CMP method. An interlayer insulating film 310d is formed. Interlayer insulating film 310d is obtained by polishing a silicon oxide film deposited by plasma CVD using TEOS, for example, by CMP. Note that SOG, BPSG, or the like can be used for the interlayer insulating film 310d, and an etch-back method or the like can be used for planarization.
On interlayer insulating film 310d, an interlayer insulating film 310e made of, for example, a silicon nitride film is formed. The interlayer insulating film 310e serves as a blocking film when a crown-shaped storage capacitor SN described later is formed.
A storage capacitor SN having a cylindrical crown shape is formed in the upper layer of the interlayer insulating film 310d. The storage capacitor SN includes a capacitor electrode 320 including a first electrode 320a connected to the n-type semiconductor region 306b through the connection hole 311c and a second electrode 320b erected in a direction perpendicular to the semiconductor substrate 301, and a capacitor The insulating film 321 is composed of a plate electrode 322 electrically connected to a predetermined wiring. The first electrode 320a and the second electrode 320b can be, for example, a polycrystalline silicon film into which phosphorus is introduced at a high concentration. The capacitor insulating film 321 is made of, for example, SiO on a silicon nitride film. ₂ Although a stacked film in which films are deposited can be used, a high dielectric constant thin film such as tantalum oxide may be used. The plate electrode 322 can be, for example, a polycrystalline silicon film in which phosphorus is introduced at a high concentration, but a metal compound such as tungsten silicide may be used.
Note that a polycrystalline silicon film 320 c and a side wall 320 d made of polycrystalline silicon are formed below the first electrode 320 a and form part of the capacitor electrode 320. The polycrystalline silicon film 320c and the side wall 320d serve as a hard mask when the connection hole 311c is opened, and the connection hole 311c can have a small opening diameter that is smaller than the resolution of photolithography. .
On the other hand, the n-type MISFET Qn in the peripheral circuit region is formed on the active region surrounded by the element isolation insulating film 302b, and is formed on the semiconductor substrate 301 via the gate insulating film 304 formed on the active region of the p well 303. Polycrystalline silicon film 305a and WSi formed on ₂ It has a gate electrode 305 made of a film 305b and a pair of n-type semiconductor regions 306c formed in the p-well 303 on both sides of the gate electrode 305 so as to be separated from each other.
The gate electrode 305 is formed simultaneously with the word line WL. The n-type semiconductor region 306c includes a low-concentration n-type semiconductor region 306c-1 and a high-concentration n-type semiconductor region 306c-2 (low-concentration n) formed in a self-alignment with a second sidewall 323b described later. Higher concentration than the semiconductor region 306c-1). That is, the n-type semiconductor region 306c has a so-called LDD (Lightly Doped Drain) structure. A p-type semiconductor region 306d that functions as a punch-through stopper is formed between the high-concentration n-type semiconductor region 306c-2 and the channel region below the low-concentration n-type semiconductor region 306c-1. For example, phosphorus or arsenic is introduced into the n-type semiconductor region 306c. However, it is preferable to introduce arsenic in order to shorten the channel length of the n-type MISFET Qn and improve its performance. When forming a high breakdown voltage n-type MISFET, it is preferable that the impurity introduced into the low-concentration n-type semiconductor region 306c-1 is phosphorus. Thereby, the breakdown voltage between the channels can be improved.
Since the gate insulating film 304 is the same as that of the selection MISFET Qt, description thereof is omitted.
Since the cap insulating film 307b is formed on the upper surface of the gate electrode 305 via the insulating film 307a, since it is the same as that of the selection MISFET Qt, the description thereof is omitted.
A first sidewall 323a is formed on the side surface of the gate electrode 305, and a second sidewall 323b is formed outside the first sidewall 323a.
As will be described later, the first sidewall 323a is formed by anisotropically etching the self-aligning insulating film 309, and is made of, for example, a silicon nitride film. The first sidewall 323a can also act as a sidewall for opening the connection hole in a self-aligned manner with respect to the gate electrode 305 when the connection hole is formed in the peripheral circuit region.
The second sidewall 323b is made of, for example, a silicon oxide film, and acts as a mask for ion implantation of impurities for forming the high-concentration n-type semiconductor region 306c-2, so that the high-concentration n-type semiconductor region 306c-2. Can be used in a self-aligned manner. By controlling the film thickness of the second sidewall 323b, the LDD structure can be optimized and the performance of the n-type MISFET Qn can be improved.
As described above, the self-alignment processing insulating film 309 on the semiconductor substrate 301 is removed by anisotropic etching, and the self-alignment processing insulating film 309 is not provided in the peripheral circuit region. Thereby, it is not necessary to open the connection hole in the peripheral circuit region in two stages, and it can be easily opened. Further, when the gate electrode 305 in the peripheral circuit region and the upper layer wiring are connected, the connection hole can be easily opened. Thus, it is not necessary to provide the insulating film 309 for self-alignment processing in the peripheral circuit region because the MISFET formed in the peripheral circuit region does not require a very high degree of integration, and there is a margin in the arrangement interval. This is based on the fact that there is a margin in the formation of the active region, and the active region can be designed in consideration of the disconnection of the connection hole. Therefore, when high integration is also required in the peripheral circuit region, the etching stopper 104 described in Embodiment 2 may be selectively formed in the peripheral circuit region after forming the second sidewalls 323b. Needless to say.
Needless to say, when a p-type MISFET is formed, the p-type MISFET has the same configuration as that of the n-type MISFET Qn and has a conductivity reversed.
In addition, at the interface between the side surface of the gate electrode 305 and the first sidewall 323a, for example, SiO ₂ An insulating film (not shown) made of may be formed, and such an insulating film and the insulating film 307a are made of WSi when the cap insulating film 307b and the first sidewall 323a are formed. ₂ The film 305b is provided to prevent contamination of the film forming apparatus by the metal constituting the film 305b and to relieve thermal stress on the cap insulating film 307b and the first sidewall 323a.
The n-type MISFET Qn is covered with an interlayer insulating film 310f made of a silicon oxide film deposited by a thermal CVD method using TEOS, for example, and an interlayer insulating film planarized by a CMP method, for example, is formed on the interlayer insulating film 310f. 310 g is formed. Interlayer insulating film 310g can be a silicon oxide film deposited by plasma CVD using TEOS, for example. Note that SOG, BPSG, or the like can be used for the interlayer insulating film 310g, and an etch back method or the like can also be used for planarization.
The interlayer insulating film 310b is formed on the interlayer insulating film 310g, and the bit line BL is formed on the interlayer insulating film 310b. The bit line BL is covered with the interlayer insulating film 310c, and the interlayer insulating film 310d is formed on the interlayer insulating film 310c.
Over the interlayer insulating film 310d and the plate electrode 322, an interlayer insulating film 324 made of, for example, BPSG is formed. The interlayer insulating film 324 is planarized by reflow.
A first wiring layer 325 is formed on the interlayer insulating film 324 in the peripheral circuit region. The first wiring layer 325 is connected to the high-concentration n-type semiconductor region 306c-2 of the n-type MISFET Qn through the connection hole 326. The first wiring layer 325 can be a laminated film of a metal film such as titanium nitride, titanium, or aluminum, and can be deposited by sputtering, for example. Note that a plug made of, for example, tungsten may be formed in the connection hole 326. The tungsten plug can be formed by a tungsten CVD method. At this time, it is preferable to form titanium nitride in the connection hole 326 in advance as an adhesive layer.
The first wiring layer 325 is covered with an interlayer insulating film 327, and a second wiring layer 328 is formed on the interlayer insulating film 327. The second wiring layer 328 is connected to the first wiring layer 325 through the connection hole 329. The interlayer insulating film 327 can be, for example, a silicon oxide film made of a silicon oxide film and SOG, and is a laminated film having a structure in which the silicon oxide film is sandwiched with a silicon oxide film deposited by plasma CVD using TEOS. It is preferable that Note that the second wiring layer 328 can have a structure similar to that of the first wiring layer 325.
The second wiring layer 328 is covered with an interlayer insulating film 330, and a third wiring layer 331 is formed on the interlayer insulating film 330. The third wiring layer 331 is connected to the second wiring layer 328 through the connection hole 332. The interlayer insulating film 330 can have the same configuration as the interlayer insulating film 327, and the third wiring layer 331 can have the same configuration as the first wiring layer 325.
The third wiring layer 331 is covered with a passivation film 333. The passivation film 333 can be a laminated film of a silicon oxide film and a silicon nitride film.
Next, a method for manufacturing the DRAM will be described with reference to FIGS. 53 to 79 are cross-sectional views showing an example of the manufacturing method of the DRAM of the sixth embodiment in the order of steps. FIGS. 53 to 79, except for FIGS. 63, 65, 67, 69, and 71, show a portion corresponding to the cross section taken along line Ia-Ia in FIG. 51 in FIG. The cross section of a circuit area is represented. 63, FIG. 65, FIG. 67, FIG. 69, and FIG. 71 show a portion corresponding to the section taken along the line IIIa-IIIa in FIG. 51 in (a), and FIG. The corresponding part is shown.
First, as shown in FIG. 53, a shallow trench isolation region is formed in a predetermined region of the semiconductor substrate 301. In the shallow trench isolation region, a silicon oxide film and a silicon nitride film (not shown) are sequentially formed on the main surface of the semiconductor substrate 301. Then, after removing the silicon oxide film and the silicon nitride film in the formation region of the shallow groove 302a with a photoresist or the like, the semiconductor substrate 301 is formed with a groove of, for example, 0.3 to 0.4 μm in the depth direction. Next, thermal silicon oxide (not shown) is formed on the side and bottom surfaces of the groove using the silicon nitride film as an oxidation mask. Then, after depositing a silicon oxide film on the entire surface of the semiconductor substrate 301 by a CVD (Chemical Vapor Deposition) method, the silicon oxide film in a region other than the shallow groove 302a is removed by a CMP (Chemical Mechanical Polishing) method or a dry etching method. Then, a silicon oxide film is selectively embedded in the shallow groove 302a.
Note that the element isolation insulating film 302b is preferably densified in an oxidizing atmosphere. Then, the silicon nitride film is removed with hot phosphoric acid to form an element isolation insulating film 302b. At this time, the element isolation insulating film 302 b is also slightly etched by the hot phosphoric acid and becomes lower than the active region of the semiconductor substrate 301. Thereby, the patterning of the gate electrode 305 becomes good, and the performance of the MISFET can be improved.
Next, as shown in FIG. 54, using the photoresist as a mask, an n-type impurity such as phosphorus is introduced into the formation region of the memory cell array of the semiconductor substrate 301 by ion implantation, and after removing the photoresist, p Type impurities such as boron are introduced by ion implantation into the region of the semiconductor substrate 301 where the memory cell array is formed and the region where the n-type MISFET Qn is formed. Further, after removing the photoresist, the semiconductor substrate 301 is subjected to a thermal diffusion process to form the deep well 303b and the p well 303. When a p-type MISFET is formed, for example, phosphorus is introduced into the region to form an n-well.
In order to optimize the impurity concentration in the channel region and obtain the desired threshold voltage of the memory cell selecting MISFET Qt or n-type MISFET Qn, p-type impurities such as boron are added to the main surface of the active region of the p-well 303. Ions can be implanted.
Next, as illustrated in FIG. 55, a gate insulating film 304 is formed on the surface of the semiconductor substrate 301. The gate insulating film 304 is formed by a thermal oxidation method and has a thickness of about 7 nm. Furthermore, the polycrystalline silicon film 305a and WSi in which phosphorus is introduced over the entire surface of the semiconductor substrate 301. ₂ A film 305b is sequentially deposited. Polycrystalline silicon film 305a and WSi ₂ The film 305b is formed by a CVD method, and these film thicknesses are, for example, 40 nm and 100 nm, respectively. Next, WSi ₂ An insulating film 307a made of a silicon oxide film and a cap insulating film 307b made of a silicon nitride film are sequentially deposited on the film 305b. The insulating film 307a and the cap insulating film 307b are formed by a CVD method, and the film thicknesses thereof are, for example, 10 nm and 160 nm, respectively.
Next, as shown in FIG. 56, using the photoresist as a mask, the cap insulating film 307b, the insulating film 307a, and the WSi ₂ By sequentially etching the laminated film composed of the film 305b and the polycrystalline silicon film 305a, the polycrystalline silicon film 305a and the WSi ₂ The gate electrode 305 of the memory cell selection MISFET Qt and the peripheral circuit MISFET Qn made of the film 305b is formed.
Next, after removing the photoresist, the semiconductor substrate 301 is subjected to a thermal oxidation process to thereby form the polycrystalline silicon film 305a and the WSi constituting the gate electrode 305. ₂ A thin silicon oxide film can be formed on the sidewall of the film 305b.
Next, as shown in FIG. 57, p-type impurities such as boron are ion-implanted into the main surface of the p-well 303 in the region where the n-type MISFET Qn is formed in the peripheral circuit region using the laminated film and the photoresist as a mask. Then, an n-type impurity such as arsenic is ion-implanted. Further, after removing the photoresist, an n-type impurity such as phosphorus is ion-implanted into the main surface of the p-well 303 where the selection MISFET Qt is formed using the laminated film and the photoresist as a mask. By extending and diffusing these impurities, the low-concentration n-type semiconductor region 306c-1 and p-type semiconductor region 306d of the n-type MISFET Qn and the n-type semiconductor regions 306a and 306b of the selection MISFET Qt are formed. Note that when an n-type MISFET for high breakdown voltage is formed, phosphorus is implanted into the region. When a p-type MISFET is formed, arsenic for a punch-through stopper and boron for a low-concentration semiconductor region (BF ₂ ). The low-concentration n-type semiconductor region 306c-1 of the peripheral circuit MISFET Qn and the n-type semiconductor regions 306a and 306b of the memory cell selection MISFET Qt are formed in a self-aligned manner on the gate electrode.
Next, as shown in FIG. 58, a silicon nitride film 334 is deposited. The film thickness of the silicon nitride film 334 can be set to 80 nm, for example. Next, an SOG film 335 is deposited, and then the SOG film 335 and the silicon nitride film 334 are etched by masking the memory array region with a photoresist. For the etching, anisotropic etching such as RIE (Reactive Ion Etching) can be used, whereby the SOG film 335 and the silicon nitride film 334 in the peripheral circuit region are removed, and an insulating film for self-alignment processing is formed in the memory array region. 309 and an interlayer insulating film 310a are formed. Since the interlayer insulating film 310a is made of SOG, the surface recess formed by the gate electrode 305 and the cap insulating film 307b can be filled and planarized. In addition, since anisotropic etching is used for etching, a first sidewall 323a made of a silicon nitride film is formed on the side surfaces of the gate electrode 305 and the cap insulating film 307b of the n-type MISFET Qn in the peripheral circuit region.
Next, as shown in FIG. 59, a TEOS silicon oxide film (not shown) is formed on the entire surface of the semiconductor substrate 301, and this is etched by anisotropic etching to form the first sidewall 323a on the side surface. 2 side walls 323b are formed. The thickness (width) of the second sidewall 323b is larger than the thickness (width) of the first sidewall 323a. As a result, the memory cell can be miniaturized and the characteristics of the peripheral circuit MISFET can be improved.
Next, as shown in FIG. 60, the gate electrode 305, the cap insulating film 307b, the second sidewall 323b, and the photoresist are used as a mask to form an n-type impurity in the region where the n-type MISFET Qn is formed in the peripheral circuit region. Ion implantation of arsenic and phosphorus. Further, after removing the photoresist, the impurity is stretched and diffused to form a high-concentration n-type semiconductor region 306c-2 of the n-type MISFET Qn. When a p-type MISFET is formed, boron (BF) for a high concentration semiconductor region is formed in the region. ₂ ). The high concentration n-type semiconductor region 306c-2 is formed in a self-aligned manner with respect to the second sidewall 323b.
Next, as shown in FIG. 61, a TEOS silicon oxide film is deposited to form an interlayer insulating film 310f. Further, a silicon oxide film is deposited using TEOS by plasma CVD, and the silicon oxide film is planarized by CMP (polishing) to form an interlayer insulating film 310g. In the memory cell portion, the TEOS silicon oxide film 310f and the silicon oxide film are deposited while the SOG film 335 remains, and is planarized by the CMP method. After planarization, the SOG film 335, the TEOS silicon oxide film 310f, and the polished silicon oxide film remain in the memory cell portion. This three-layer insulating film is referred to as an interlayer insulating film 310g.
Next, as shown in FIGS. 62 to 65, the interlayer insulating film 310a is etched using the photoresist as a mask to form connection holes 311b. The connection hole 311b is opened by two-stage etching.
First, as a first etching step, etching is performed under conditions where the silicon oxide film is easily etched and the silicon nitride film is difficult to etch. Such etching can be performed by, for example, C _Four F ₈ Further, it can be realized by anisotropic plasma etching using a mixed gas containing argon and a raw material gas. In this first etching process, since the silicon nitride film is difficult to be etched, the etching of the interlayer insulating film 310a made of the silicon oxide film proceeds to the stage where the self-aligned insulating film 309 made of the silicon nitride film is exposed. . This state is shown in FIGS. That is, the self-alignment processing insulating film 309 functions as an etching stopper in the first etching step.
Next, as a second etching step, etching is performed under the condition that the silicon nitride film is etched. Such etching is performed, for example, by CHF. _Three , CF _Four Further, it can be realized by anisotropic plasma etching using a mixed gas containing argon and a raw material gas. In this second etching step, since the thick interlayer insulating film 310a has already been removed by the first etching step, only the thin self-alignment processing insulating film 309 needs to be etched. That is, it is possible to suppress the over-etching of the insulating film for self-alignment processing 309 to the base and perform the etching with a sufficient process margin. That is, under the conditions for etching the silicon nitride film, the etching selectivity between the silicon nitride film and the silicon oxide film cannot be obtained, and the silicon nitride film is etched and the silicon oxide film is etched. As shown at 65, when the bottom of the connection hole 311b covers the element isolation insulating film 302b, the element isolation insulating film 302b made of a silicon oxide film is also etched. Ideally, it is desirable to etch only the insulating film 309 for self-alignment processing and just etch to finish the etching immediately after the removal of the insulating film 309 for self-alignment processing. In general, it is difficult to ensure that the connection hole 311b is opened in all regions in the substrate surface and to perform just etching. Therefore, a certain amount of overetching is required. For this reason, when the bottom portion of the connection hole 311b protrudes from the active region and covers the element isolation insulating film 302b, the element isolation insulating film 302b may be excessively etched. Since the insulating film 309 is as thin as about 80 nm and only the insulating film 309 for self-alignment processing may be etched, an amount of overetching of about 30 to 50% of the thickness of the insulating film 309 for self-alignment processing is sufficient. At most, the film thickness equivalent to the insulating film 309 for self-alignment processing is sufficient. Therefore, excessive etching of the element isolation insulating film 302b can be suppressed to a minimum, and as a result, the refresh characteristics of the DRAM can be improved and the performance of the DRAM can be improved.
In the second etching step, as shown in FIG. 64, since the gate electrode 305 is covered with the self-aligning processing insulating film 309 and the cap insulating film 307b, the connection hole 311b is formed in the gate electrode. The gate electrode 305 is not exposed even if it is designed to cover 305, and thus the connection hole 311b can be opened in a self-aligning manner. That is, the self-alignment processing insulating film 309 has a function of opening the connection hole 311b in a self-aligning manner with respect to the gate electrode 305 and a function of suppressing excessive etching of the element isolation insulating film 302b. is there.
Such a method of performing two-step etching using the self-aligned insulating film 309 is particularly effective in a DRAM in which the degree of integration is improved and the interval between the gate electrodes 305 is narrow. That is, when a sidewall for self-aligned opening with respect to the gate electrode 305 is formed on the side surface of the gate electrode 305, a stopper film for suppressing excessive etching of the element isolation insulating film 302b is further formed. Then, the space between the gate electrodes 305 in which the connection holes 311b are to be formed is filled, or even if it is not filled, the bottom area of the connection holes 311b becomes extremely small and it is difficult to ensure sufficient connection conductivity. However, in the manufacturing method of the sixth embodiment, the side wall for the self-alignment opening with respect to the gate electrode 305 is not formed, and the self-alignment processing insulating film 309 has a function for the self-alignment opening. Therefore, a sufficient space can be secured between the gate electrodes 305, and sufficient connection reliability can be obtained while maintaining a process margin for opening the connection hole 311b.
Next, as shown in FIGS. 66 and 67, a plug 314 is formed in the connection hole 311b. The plug 314 can be polycrystalline silicon into which phosphorus has been introduced, and can be formed by depositing a polycrystalline silicon film over the entire surface of the semiconductor substrate 301 and then etching it back. Note that since the bottom of the connection hole 311b is not formed as deep as the element isolation insulating film 302b, the bottom surface of the plug 314 is a shallow region even in a region where the connection hole 311b covers the element isolation insulating film 302b. The reliability of the DRAM can be improved.
Next, as shown in FIGS. 68 and 69, an interlayer insulating film 310b made of a TEOS silicon oxide film is formed on the entire surface of the semiconductor substrate 301, and then a connection hole 311a is formed. The connection hole 311a is formed by a two-step etching process as in the case of the connection hole 311b. Similarly to the connection hole 311b, the connection hole 311a is not formed in a deep portion of the element isolation insulating film 302b.
Next, as shown in FIGS. 70 and 71, the polycrystalline silicon film 312 and WSi into which phosphorus has been introduced. ₂ The film 313 is sequentially deposited by the CVD method and patterned to form the bit line BL. The bit line BL is connected to one n-type semiconductor region 306a of the memory cell selection MISFET Qt through the connection hole 311a. Similarly to the plug 314, the bottom surface of the polycrystalline silicon film 312 is formed in a shallow region even in a region where the connection hole 311a covers the element isolation insulating film 302b, so that the reliability of the DRAM can be improved.
Next, as shown in FIG. 72, an interlayer insulating film 310c and an interlayer insulating film 310d made of a silicon oxide film are deposited on the semiconductor substrate 301 by a CVD method, and then the surface of the interlayer insulating film 310d is formed by, for example, a CMP method. Then, an interlayer insulating film 310e made of a silicon nitride film is formed on the semiconductor substrate 301.
Next, as shown in FIG. 73, after depositing a silicon oxide film 336, a polycrystalline silicon film 320c is deposited, and the polycrystalline silicon film 320c is patterned using a photoresist as a mask. Further, a polycrystalline silicon film (not shown) is deposited and etched by anisotropic etching to form sidewalls 320d. By forming the sidewall 320d in this manner, an opening having a smaller diameter than the opening of the polycrystalline silicon film 320c patterned with the minimum resolution of photolithography can be obtained.
Next, as shown in FIG. 74, a connection hole 311c is opened using the polycrystalline silicon film 320c and the side wall 320d as a mask.
Next, as shown in FIG. 75, a first electrode 320a into which phosphorus is introduced and a silicon oxide film 337 are sequentially deposited on the semiconductor substrate 301 by a CVD method. The first electrode 320 a is deposited in the connection hole 311 c and connected to the plug 314.
Next, as shown in FIG. 76, using the photoresist as a mask, the silicon oxide film 337 is etched, and then the first electrode 320a and the polycrystalline silicon film 320c are sequentially etched. The processed first electrode 320a and polycrystalline silicon film 320c form part of the storage electrode of the information storage capacitor element in the memory cell region.
Next, after removing the photoresist, as shown in FIG. 77, a polycrystalline silicon film (not shown) is deposited on the semiconductor substrate 301 by the CVD method and anisotropically etched to form the second electrode. 320b is formed. Further, for example, the silicon oxide films 336 and 337 are removed by wet etching using a hydrofluoric acid solution, and a crown-shaped capacitor electrode including the first electrode 320a, the second electrode 320b, the polycrystalline silicon film 320c, and the sidewall 320d is formed. 320 is formed.
Next, as shown in FIG. 78, polycrystalline silicon grains having a grain size of about 40 nm are grown on the capacitor electrode 320, and then a silicon nitride film (not shown) is deposited on the semiconductor substrate 301 by the CVD method. By performing oxidation treatment, a silicon oxide film is formed on the surface of the silicon nitride film, and a capacitor insulating film 321 made of the silicon oxide film and the silicon nitride film is formed on the surface of the capacitor electrode 320. Thereafter, a polycrystalline silicon film (not shown) is deposited on the semiconductor substrate 301 by a CVD method, and the polycrystalline silicon film is etched using a photoresist as a mask to form a plate electrode 322.
Next, as shown in FIG. 79, a BPSG film is deposited and annealed to form an interlayer insulating film 324, and etching is performed using a photoresist as a mask to open connection holes 326. When the connection hole 326 is opened, the connection hole 326 can be opened in a self-aligned manner with respect to the gate electrode 305 in the peripheral circuit region by using the first sidewall 323a. Further, titanium, titanium nitride, aluminum and titanium are sequentially deposited and patterned to form the first wiring layer 325. Note that a tungsten plug may be formed by depositing titanium nitride on the inner surface of the connection hole 326, forming a tungsten film by a CVD method, and etching it back. Note that sputtering can be used for deposition of titanium, titanium nitride, aluminum, and titanium.
Finally, a TEOS silicon oxide film is deposited by plasma CVD, and after coating an SOG film, a TEOS silicon oxide film is deposited by plasma CVD to form an interlayer insulating film 327. Thereafter, as in the case of the first wiring layer, a connection hole 329, a second wiring layer 328, an interlayer insulating film 330, a connection hole 332, and a third wiring layer 331 are formed, and a TEOS silicon oxide film and silicon by a plasma CVD method are formed. A nitride film is deposited to form a passivation film 333, and the DRAM shown in FIG. 50 is almost completed.
According to the DRAM of the sixth embodiment, since the connection holes 311a and 311b are opened by the two-step etching using the self-alignment processing insulating film 309, the plug 314 and the bit line are self-aligned with respect to the gate electrode 305. BL can be formed, over-etching of the element isolation insulating film 302b can be prevented, and its performance such as refresh characteristics of DRAM can be improved. In addition, since a sidewall is not formed on the side surface of the gate electrode 305 in the memory cell region, it is possible to cope with high integration of DRAM.
In addition, since the self-alignment processing insulating film 309 has both the function of forming a self-aligned contact with respect to the gate electrode 305 and the function of preventing excessive etching of the element isolation insulating film 302b, the individual functions can be realized. There is no need to form individual members, the number of steps can be reduced, and an increase in processes can be suppressed.
In the sixth embodiment, an example in which the plug 314 is used is shown, but the capacitor electrode 320 is directly connected to the n-type semiconductor region 306b through the connection hole 311b without using the plug 314. Also good. In this case, since the depth of the connection hole 311b becomes considerably large, the etching margin becomes small and the processing becomes difficult. However, by using the two-step etching of the manufacturing method of the sixth embodiment, the etching margin is reduced. It is possible to cope with the opening of deep connection holes. That is, the effect of the present invention becomes more remarkable when the plug 314 is not used.
Needless to say, the two-stage etching described above may be performed in a continuous process.
In FIG. 60, after forming the high-concentration n-type semiconductor region 6c-2 of the n-type MISFET Qn, the silicon nitride film 104 shown in the second embodiment is selectively formed in the peripheral circuit region, and thereafter, FIG. It is also possible to deposit a TEOS silicon oxide film 61 to form an interlayer insulating film 310f and to carry out subsequent steps.
In FIG. 60, the third embodiment can be implemented after the high-concentration n-type semiconductor region 6c-2 of the n-type MISFET Qn is formed.
That is, after the high-concentration n-type semiconductor region 6c-2 of the n-type MISFET Qn is formed, a refractory metal such as molybdenum or cobalt is deposited on the peripheral circuit region, and the high-concentration n-type semiconductor of the n-type MISFET Qn for the peripheral circuit is deposited. A silicide layer is formed on the surface of the region 6c-2, and then an unreacted refractory metal is removed, and then a TEOS silicon oxide film shown in FIG. 61 is deposited to form an interlayer insulating film 310f, followed by It is also possible to carry out the process.
The above example can also be applied to the case of Embodiment 7 or 8 described later.
(Embodiment 7)
80 and 81 are cross-sectional views showing an example of a method for manufacturing a DRAM which is another embodiment of the present invention.
The manufacturing method of the seventh embodiment is the same as the manufacturing method of the sixth embodiment up to the formation of the gate electrode 305 and the cap insulating film 307b (FIG. 57), and therefore the description thereof is omitted.
The manufacturing method of the seventh embodiment shows a case where the arrangement of the gate electrodes 305 in the memory array region is dense, and shows an example in which the self-alignment processing insulating film 309 is removed without a mask in the peripheral circuit region. It is.
After the formation of the gate electrode 305 and the cap insulating film 307b, as shown in FIG. 80, a silicon nitride film to be a self-aligning insulating film 309 is deposited, and a silicon oxide film 339 is further deposited. In the memory array region, as shown in FIG. 80A, since the gate electrodes 305 are densely arranged, the silicon oxide film 339 is completely embedded in the recess, and the surface thereof is flat. On the other hand, in the peripheral circuit region, as shown in FIG. 80B, the gate electrode 305 is formed sparsely as compared with the memory array region, and thus has a surface shape that almost faithfully reflects the uneven shape. Yes.
Next, as shown in FIG. 81, the silicon nitride film 309 and the silicon oxide film 339 are etched by anisotropic etching. Etching is performed under conditions for etching the silicon nitride film, for example, CHF. _Three , CF _Four Etching using a mixed gas of argon and argon. In the memory array region, since the surface of the silicon oxide film 339 is flat, the flat surface of the silicon oxide film 339 and the silicon nitride film 309 on the surface of the cap insulating film 307b are only etched. Therefore, the silicon nitride film 309 remains on the main surface of the semiconductor substrate 301 in the memory array region, and functions as a self-alignment processing insulating film 309. On the other hand, in the peripheral circuit region, except for the side surface of gate electrode 305, silicon nitride film 309 and silicon oxide film 339 on the main surface of semiconductor substrate 301 and on the surface of cap insulating film 307b are etched, so that silicon nitride film 309 and silicon nitride film 309 are etched. The oxide film 339 only remains as the first sidewall 323a and the second sidewall 323b on the side surface of the gate electrode 305.
That is, according to the manufacturing method of the seventh embodiment, the self-alignment processing insulating film 309 is formed in the memory cell array region without using a photomask or the like, and at the same time, the second electrode is formed on the side surface of the gate electrode 305 in the peripheral circuit region. One sidewall 323a and a second sidewall 323b can be formed. This makes it possible to simplify the process.
Note that the subsequent steps are the same as the steps after FIG.
(Embodiment 8)
82 to 84 are cross-sectional views showing an example of a method for manufacturing a DRAM which is still another embodiment of the present invention.
The manufacturing method of the eighth embodiment is the same as the manufacturing method of the sixth embodiment up to the formation of the gate electrode 305 and the cap insulating film 307b (FIG. 57), and the description thereof will be omitted.
The manufacturing method of the eighth embodiment shows a case where the arrangement of the gate electrodes 305 in the memory array region is sparse, and shows an example in which the self-alignment processing insulating film 309 is removed using a mask in the peripheral circuit region. Is.
After the formation of the gate electrode 305 and the cap insulating film 307b, as shown in FIG. 82, a silicon nitride film to be a self-aligning insulating film 309 is deposited, and a photomask 340 is formed in the memory array region.
Next, as shown in FIG. 83, the insulating film 309 for self-alignment processing is etched by anisotropic etching using the photomask 340 as a mask. Etching is performed under conditions for etching the silicon nitride film, for example, CHF. _Three , CF _Four Etching using a mixed gas of argon and argon. Thus, the first sidewall 323a is formed on the side surface of the gate electrode 305 in the peripheral circuit region.
Further, after the photomask 340 is removed, a silicon oxide film 341 is deposited on the entire surface of the semiconductor substrate 301.
Next, as shown in FIG. 84, the silicon oxide film 341 is etched by anisotropic etching. Etching is performed under conditions where the silicon nitride film is difficult to etch, such as _Four F ₈ Etching using a mixed gas of argon and argon. As a result, the second sidewall 323b is formed on the side surface of the gate electrode 305 in the memory cell array region as well as in the peripheral circuit region.
According to such a manufacturing method, the insulating film 309 for self-alignment processing in the peripheral circuit region can be removed, and the second sidewall 323b can be formed on the side surface of the gate electrode 305. Note that the LDD structure can be optimized by adjusting the thickness of the second sidewall 323b as described in Embodiment 6.
Note that the subsequent steps are the same as the steps after FIG.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
For example, in the sixth to eighth embodiments, the case where the element isolation region is a shallow trench element isolation region has been described. However, the element isolation region may be an element isolation region using a thick field insulating film by a LOCOS method. In the present invention, since the shallow groove of the shallow groove element isolation region is formed steeper than the bird's beak of the field insulating film, the shallow groove element isolation region which is highly likely to be greatly affected by slight deviation. Although a remarkable effect can be obtained by applying to the above, the effect can be obtained even if it is applied to an element isolation region by a field insulating film.
The present invention includes the following inventions.
(1) A semiconductor integrated circuit device according to the present invention includes a gate insulating film and a gate insulating film formed on a main surface of a semiconductor substrate having an element isolation region and an active region surrounded by the element isolation region on the main surface. A MISFET including a gate electrode formed thereon, a cap insulating film formed on the gate electrode, and a semiconductor region formed in active regions on both sides of the gate electrode is formed. A semiconductor integrated circuit device having an interlayer insulating film that insulates a member, wherein an interlayer is formed on a main surface of a semiconductor substrate including an upper surface and a side surface of a cap insulating film and a side surface of a gate electrode in all or a part of the MISFET. An insulating film for self-alignment processing having an etching selectivity with respect to the insulating film is formed, and the conductive film and the semiconductor region are connected to the insulating film for self-alignment processing In addition to opening the connection hole for the gate electrode in a self-aligned manner, the bottom of the connection hole is intended to prevent excessive etching of the portion of the element isolation region that is out of the active region It is.
According to such a semiconductor integrated circuit device, the insulating film for self-alignment processing is formed on the side surface of the gate electrode and the main surface of the semiconductor substrate, and as a sidewall of the gate electrode for processing the connection hole in a self-alignment manner, And a highly integrated semiconductor integrated circuit device having a short interval between the gate electrodes, particularly a memory mat region of a highly integrated DRAM, for use as a stopper film for preventing excessive etching of the element isolation region of the semiconductor substrate Even in the MISFET, a sufficient connection region on the bottom surface of the connection hole can be secured. As a result, even in a highly integrated semiconductor integrated circuit device, both the self-aligned contact technology and the technology for preventing excessive etching of the element isolation region can be used, and high integration and high reliability of the semiconductor integrated circuit device can be achieved. It can be realized.
(2) In the semiconductor integrated circuit device, the insulating film for self-alignment processing is a thin film that is in contact with the side surfaces of the cap insulating film and the gate electrode or is sufficiently thin as compared with the film thickness of the insulating film for self-alignment processing. It is not necessary to form a sidewall between the insulating film for self-alignment processing, the cap insulating film, and the side surface of the gate electrode. That is, the insulating film for self-alignment processing can be used as the sidewall of the gate electrode, and it is not necessary to form a separate sidewall. For this reason, the opening margin of the connection hole can be increased, and the number of steps can be minimized by simplifying the steps.
(3) The insulating film for self-alignment processing can be a silicon nitride film, and the interlayer insulating film can be a silicon oxide film. As described above, by using a silicon nitride film and a silicon oxide film that are frequently used in the conventional manufacturing process of a semiconductor integrated circuit device and have a well-known physical property, the process design and conditions can be determined using an established manufacturing process. It is possible to make a selection easily and to quickly start a production process.
(4) The element isolation region can be a shallow groove element isolation region having a shallow groove element isolation structure, or an element isolation region having a thick field insulating film formed by using a selective oxidation method. In particular, in the case of the shallow groove element isolation region, the shallow groove element isolation region is formed steeply in the boundary region between the active region and the element isolation region. The excessively etched portion formed in the isolation region becomes deeper than a thick field insulating film or the like, and the problem of excessive etching due to misalignment becomes significant. Therefore, when the present invention of the semiconductor integrated circuit device having the shallow trench element isolation region is applied to prevent excessive etching of the element isolation region, the effect is remarkable.
(5) Also, the semiconductor integrated circuit device of the present invention includes a memory mat region of a DRAM, and an insulating film for self-alignment processing is formed only in the memory mat region. In other words, the insulating film for self-alignment processing is formed only in the memory mat area where the demand for high integration is strong, realizing high integration and high reliability of the memory mat area, and the demand for relatively high integration is strong. An insulating film for self-alignment processing is not formed in a peripheral circuit region that does not exist.
According to such a semiconductor integrated circuit device, high integration and high reliability are realized in the memory mat region, and since the insulating film for self-alignment processing is not formed in the peripheral circuit region or the like, it is formed simultaneously with the gate electrode. The connecting hole forming step between the wiring layer and the upper layer or the connecting hole forming step between the semiconductor region of the MISFET in the peripheral circuit region and the upper layer can be simplified. In other words, when the insulating film for self-alignment processing is formed also in the peripheral circuit region, it is necessary to perform two-step etching for etching the insulating film for self-alignment processing when forming the connection hole between the semiconductor region and the upper layer. In addition, when forming the connection hole between the wiring layer and the upper layer formed simultaneously with the gate electrode, the insulating film for self-alignment processing is etched in addition to the etching of the cap insulating film formed on the upper surface of the gate electrode. It is necessary and the process may be complicated. However, in the present invention, since the insulating film for self-alignment processing is not formed in the peripheral circuit region, the process is not complicated.
(6) Further, the semiconductor integrated circuit device of the present invention includes the memory mat region of the DRAM, and the side surface of the gate electrode of the MISFET formed in the region other than the memory mat region has the same process as the insulating film for self-alignment processing. A sidewall is formed through the insulating film deposited in step 1 or in contact with the side surface.
According to such a semiconductor integrated circuit device, the LDD (Lightly Doped Drain) structure of the MISFET formed in the area other than the memory mat area is optimized, and the MISFET in the area other than the memory mat area is shortened. The performance can be improved.
(7) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a step of forming an element isolation region on the main surface of the semiconductor substrate; (b) a silicon oxide film serving as a gate insulating film on the entire surface of the semiconductor substrate; A conductive film mainly composed of a polycrystalline silicon film to be an electrode and a silicon nitride film to be a cap insulating film are sequentially deposited to form a laminated film, and the laminated film is patterned to form a gate insulating film, a gate electrode and a cap insulating film. A step of forming a film; (c) a step of ion-implanting impurities using the gate electrode as a mask to form a semiconductor region in an active region of the main surface of the semiconductor substrate surrounded by the element isolation region; and (d) an entire surface of the semiconductor substrate. (E) depositing an interlayer insulating film over the entire surface of the semiconductor substrate on which the self-alignment processing insulating film is formed, and (f) depositing an insulating film for self-alignment processing. A first etching step of selectively etching the interlayer insulating film under a condition that the etching rate is sufficiently smaller than the etching rate of the interlayer insulating film, and opening a part of the connection hole in a self-aligned manner with respect to the gate electrode; (G) including a second etching step of anisotropically etching the insulating film for self-alignment processing at the bottom of the connection hole.
According to such a method of manufacturing a semiconductor integrated circuit device, after forming the gate electrode and the cap insulating film, the insulating film for self-alignment processing is deposited without forming the sidewall, so that the contact margin between the gate electrodes is increased. It is possible to take enough. As a result, the connection reliability between the member formed in the connection hole of the semiconductor integrated circuit device and the semiconductor region formed in the active region can be improved.
Further, since the connection hole is opened in two stages of the first etching process and the second etching process, the connection hole can be opened in a self-aligned manner with respect to the gate electrode, and at the bottom of the connection hole. Excessive etching of the element isolation region can be prevented. As a result, the degree of integration of the semiconductor integrated circuit device can be improved, the characteristics of the MISFET of the semiconductor integrated circuit device can be improved, and the reliability can be improved. Needless to say, the first etching step and the second etching step may be continuous steps.
(8) In addition, in the step (a), the element isolation region is formed by filling the shallow groove with a silicon oxide film after the shallow groove is formed and polishing the silicon oxide film by etch back or CMP. Either a first configuration in which only a silicon oxide film is left, or a second configuration in which a thick field insulating film is selectively formed by a thermal oxidation method using a patterned silicon nitride film as a mask. it can. According to such a method for manufacturing a semiconductor integrated circuit device, a semiconductor integrated circuit device having a shallow groove element isolation region or a thick field insulating film by a LOCOS method can be manufactured.
(9) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the self-alignment processing insulating film is a silicon nitride film, the interlayer insulating film is a silicon oxide film, and the etching in the first etching step is C. _Four F ₈ Etching in the second etching step is performed by plasma etching using a mixed gas containing oxygen and argon. _Three , CF _Four And plasma etching using a mixed gas containing argon.
According to such a method of manufacturing a semiconductor integrated circuit device, the first etching step is performed by C. _Four F ₈ Since the etching is performed by plasma etching using a mixed gas containing argon and argon, the silicon oxide film can be etched under a condition that the silicon nitride film is difficult to be etched, that is, under a condition having a sufficient etching selectivity with respect to the silicon nitride film. The silicon oxide film can be etched, and the interlayer insulating film in the connection hole region can be etched with a sufficient processing margin to the insulating film for self-alignment processing on the main surface of the semiconductor substrate as a stopper film. . In addition, the second etching process is CHF. _Three , CF _Four Since the etching is performed by plasma etching using a mixed gas containing argon and argon, the self-aligning insulating film made of a silicon nitride film can be easily etched. Since only the relatively thin silicon nitride film is etched in the second etching step, the connection hole is opened with a sufficient processing margin, and as a result, excessive etching of the element isolation region can be reduced.
(10) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the second etching step, an over-etching less than an etching time required for etching the entire film thickness of the insulating film for self-alignment processing is added. .
Such over-etching can be applied to open the connection hole by two-step etching using the self-aligned insulating film as a stopper film as described above. Although the etching is performed, the connection hole can be reliably opened, and the connection reliability at the bottom of the connection hole can be improved. Note that the amount of etching in the active region is less than or equal to the thickness of the insulating film for self-alignment processing because the overetching applied is less than the etching time required to etch the entire film thickness of the insulating film for self-alignment processing. Since the thickness of the insulating film for self-alignment processing can be reduced to 30 to 50 nm, such excessive etching does not cause a problem in the process.
(11) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes a DRAM memory mat region in a semiconductor integrated circuit device, and a gate electrode and a cap insulating film other than the memory mat region after the deposition of the self-alignment processing insulating film. The method includes a step of forming a side wall with an insulating film for self-alignment processing interposed therebetween.
According to such a method of manufacturing a semiconductor integrated circuit device, it is possible to form an appropriate LDD structure in the MISFET other than the memory mat region. As a result, the MISFET other than the memory mat region, for example, the MISFET in the peripheral circuit region can be shortened to improve the performance of the MISFET. Since there is generally a sufficient space between the gate electrodes in the peripheral circuit region, it is possible to form a sidewall even if the insulating film for self-alignment processing is formed on the side surface of the gate electrode of the MISFET in the peripheral circuit region. It is.
(12) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the semiconductor integrated circuit device includes a DRAM memory mat region, and after the deposition of the self-alignment processing insulating film, at least a semiconductor substrate other than the memory mat region is formed. The method includes a step of removing the insulating film for self-alignment processing on the main surface.
According to such a method of manufacturing a semiconductor integrated circuit device, since it includes a step of removing at least the insulating film for self-alignment processing on the main surface of the semiconductor substrate other than the memory mat region, for example, self-alignment of the peripheral circuit region of the DRAM The processing insulating film can be removed, and the connection hole connected to the semiconductor region or gate electrode of the MISFET in the peripheral circuit region can be easily formed.
(13) The sidewall is formed by depositing the self-alignment processing insulating film, etching the self-alignment processing insulating film using the photoresist covering the memory mat region as a mask, removing the photoresist, and then forming the semiconductor. An insulating film can be deposited on the entire surface of the substrate, and the insulating film can be anisotropically etched. The etching of the insulating film for self-alignment processing may be anisotropic etching that remains as a sidewall on the side surface of the gate electrode, or isotropic etching that does not remain as a sidewall.
In addition, the sidewall is formed by depositing an insulating film for embedding the gate electrode and cap insulating film formed in the memory mat region after depositing the insulating film for self-alignment processing, and anisotropically etching the insulating film. Can be done. In such a case, since the space between the gate electrodes in the memory mat region is filled with an insulating film, an insulating film for self-alignment processing formed on the main surface of the semiconductor substrate between the gate electrodes in the memory mat region is formed by subsequent anisotropic etching. On the other hand, the insulating film for self-alignment processing in the area other than the memory mat area, for example, the peripheral circuit area, has a margin in the distance between the gate electrodes in the peripheral circuit area. It is possible to perform etching simultaneously with anisotropic etching. That is, it is possible to omit the mask formation process for etching only the insulating film for self-alignment processing in the peripheral circuit region. Thereby, a process can be simplified.
Among these inventions, effects obtained by typical ones will be briefly described as follows.
(1) Even in the memory cell region of a highly integrated DRAM, the connection hole can be formed in a self-aligning manner, and excessive etching of the element isolation region at the bottom of the connection hole can be prevented.
(2) When the connection hole is formed in a self-aligning manner and excessive etching of the element isolation region at the bottom of the connection hole is prevented, the processing margin of the connection hole can be improved.
(3) When forming the connection hole in a self-aligning manner and preventing excessive etching of the element isolation region at the bottom of the connection hole, an increase in the number of steps can be suppressed.
(4) High integration of the semiconductor integrated circuit device can be realized, the refresh characteristics of the DRAM can be improved, and the transistor characteristics of the memory cell region can be improved.
As a result of investigation of known examples conducted by the present inventor after the present invention, a technique for forming a connection hole of one electrode of a capacitor and a bit line connection hole in a self-aligned manner with respect to a word line is disclosed in Japanese Patent Laid-Open No. 4-342164. It is described in the gazette.
Also, there is a technique for preventing overetching of a semiconductor substrate or an element isolation insulating film by providing a silicon nitride film when opening a connection hole and a bit line connection hole of one electrode of a capacitor with respect to an interlayer insulating film. No. 8-264075 and Japanese Patent Application No. 8-344906. Japanese Patent Laid-Open No. 6-53162 discloses a technique of providing a silicon nitride film when opening a connection hole to the source or drain in the insulating film on the MOSFET.
Further, a method for manufacturing a semiconductor device having a double side wall film made of a silicon nitride film and a silicon oxide film on the side wall of a gate electrode is disclosed in Japanese Patent Laid-Open Nos. 3-276729 and 6-168955 and US Pat. No. 804.
Industrial applicability
As described above, the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention are suitable for microfabrication, high integration, and high reliability, and in particular, a DRAM or an electrically rewritable nonvolatile memory or logic. The present invention is suitable for application to a highly integrated semiconductor integrated circuit device in which a circuit and a DRAM or an electrically rewritable nonvolatile memory are mounted together.

Claims (4)

A first MISFET including a gate electrode formed on a main surface of a semiconductor substrate via a gate insulating film and a semiconductor region in contact with a channel region of the main surface of the semiconductor substrate below the gate electrode;
A gate electrode formed on a main surface of the semiconductor substrate via a gate insulating film, a low concentration semiconductor region in contact with a channel region of the main surface of the semiconductor substrate below the gate electrode, and provided outside the low concentration semiconductor region A semiconductor integrated circuit device having a second MISFET including a high-concentration semiconductor region,
A cap insulating film is formed on the upper surfaces of the gate electrodes of the first and second MISFETs, and a first sidewall spacer formed of a first insulating film made of a silicon nitride film on the side surfaces of the gate electrodes of the second MISFETs. And a second sidewall spacer formed of a second insulating film made of a silicon oxide film, which covers the first sidewall spacer, is formed on the outside of the gate electrode of the first MISFET. A third sidewall spacer formed of the first insulating film is formed;
First conductor portion, a self-aligned manner with respect to the first of the third sidewall spacer formed of an insulating film for connecting the first 1MISFET member formed on an upper layer of the semiconductor region and the second 1MISFET of Embedded in the connection hole formed by simple etching ,
A second conductor portion connecting the semiconductor region of the second MISFET and a member formed in an upper layer of the second MISFET is formed;
The first conductor part and the second conductor part have different embedded members,
The high-concentration semiconductor region of the second MISFET is formed by ion implantation that is self-aligned with the second sidewall spacer formed of the second insulating film;
The first MISFET is a DRAM selection MISFET disposed in a memory array region of a DRAM cell, and a member formed in an upper layer of the first MISFET is a storage capacitor or a bit line of the DRAM.
The second MISFET is included in a peripheral circuit that drives the DRAM,
The impurity doped in the semiconductor region of the selective MISFET is phosphorus,
The N-channel MISFET of the second MISFET includes a first N-channel MISFET and a second N-channel MISFET, and the first N-channel MISFET is a lightly doped semiconductor region doped with arsenic and arsenic doped The second N-channel MISFET includes a low-concentration semiconductor region doped with phosphorus and a high-concentration semiconductor region doped with arsenic;
The semiconductor integrated circuit device, wherein the first conductor portion is a conductor portion in which polycrystalline silicon is embedded, and the second conductor portion is a conductor portion in which a refractory metal is embedded. The semiconductor integrated circuit device according to claim 1 ,
The first N-channel MISFET includes a semiconductor region doped with boron in a region in contact with the high-concentration semiconductor region below the low-concentration semiconductor region, and the second N-channel MISFET is a semiconductor doped with boron. A semiconductor integrated circuit device characterized by not including a region. The semiconductor integrated circuit device according to claim 1 or 2 ,
2. A semiconductor integrated circuit device according to claim 1, wherein no silicide layer is formed on the surface of the semiconductor region of the selective MISFET, and a silicide layer is formed on the surface of the high-concentration semiconductor region of the second MISFET. A semiconductor integrated circuit device according to claim 1, 2 or 3 ,
The semiconductor integrated circuit device according to claim 1, wherein a thickness of the gate insulating film of the selection MISFET is larger than a thickness of the gate insulating film of the second MISFET.

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