CN102412206B - Manufacture method of flash memory - Google Patents
Manufacture method of flash memory Download PDFInfo
- Publication number
- CN102412206B CN102412206B CN 201010292464 CN201010292464A CN102412206B CN 102412206 B CN102412206 B CN 102412206B CN 201010292464 CN201010292464 CN 201010292464 CN 201010292464 A CN201010292464 A CN 201010292464A CN 102412206 B CN102412206 B CN 102412206B
- Authority
- CN
- China
- Prior art keywords
- sidewall
- circuit region
- peripheral circuit
- region
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacture method of a flash memory. The method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a memory cell array and a periphery circuit region, the memory cell array and the periphery circuit region are in a gate structure respectively; forming insulation sidewalls on the gate structure surfaces of thememory cell array and the periphery circuit region; forming a sacrifice sidewall on the insulation sidewall surface of the periphery circuit region only and carrying out ion doping process, so as to form an active region of the periphery circuit region. With the adoption of the sacrifice sidewall on the insulation sidewall surface of the periphery circuit region, the requirement on device pressure resistance during ion doping process of the periphery circuit region is met, so that a process window for forming the insulation sidewall is enlarged and the yield is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of flash memory.
Background technology
In present semiconductor industry, integrated circuit mainly can be divided into the three major types type: analog integrated circuit, digital integrated circuit and DA combination integrated circuit.An important kind as digital integrated circuit, memory device, especially flash memory (flash memory, be called for short flash memory) development particularly rapid, main because flash memory have under situation about not powering up can long preservation information and have integrated level height, access speed fast, be easy to wipe and advantage such as rewriting.
The patent No. is the Chinese patent of ZL99106789.4, namely discloses a kind of flash memory and manufacture method thereof.As shown in Figure 1, existing flash memory is divided according to device area, generally include memory cell array region I and peripheral circuit region II two parts, for the integrated level that improves chip and be convenient to wiring, memory cell is arranged in array among the memory cell array region I, and its device pitch is usually less than peripheral circuit region II.For example, among Fig. 1 the spacing d between each memory cell grid structure 1 less than the space D between the peripheral circuit cmos device grid 2.In existing flash memory manufacturing process, the gate lateral wall of said memory cells and the gate lateral wall of cmos device form simultaneously, no matter carry out the making of active area then respectively in memory cell array region I and peripheral circuit region II, be that memory cell array region I or peripheral circuit region II all have consistent sidewall thickness therefore.
Existing flash memory manufacturing process has following shortcoming: peripheral circuit region II is behind the sidewall that forms grid 2, need to adopt ion doping technology to carry out the making of source/active areas such as drain electrode, above-mentioned ion doping arts demand adopts higher operating voltage, in order to improve the resistance to pressure of device, the thickness requirement of the sidewall of described grid 2 is also bigger.And in memory cell array region I, because the device closeness is higher, the spacing of control gate structure 1 is less, to cause the sidewall between the adjacent grid structure 1 to connect if form blocked up sidewall, even form empty, subsequent technique is caused bad influence, and therefore the sidewall thickness of described control gate structure 1 requires thinner.The different demands of above oppose side wall thickness cause in the existing flash memory manufacturing method, and the process window of sidewall formation technology is less, and then have influenced the yield of product.
Summary of the invention
The problem that the present invention solves is existing flash memory manufacturing method, and it is too small that sidewall forms process window, is difficult to satisfy simultaneously the different-thickness demand of memory array region and peripheral circuit region oppose side wall, and influences the problem of product yield.
The manufacture method of a kind of flash memory provided by the invention comprises:
Semiconductor structure is provided, and described semiconductor structure comprises memory cell array district and peripheral circuit region, and described memory cell array district and peripheral circuit region have grid structure respectively; Grid structure surface at memory cell array district and peripheral circuit region forms insulative sidewall; Only form on the insulative sidewall surface of described peripheral circuit region and sacrifice sidewall, carry out ion doping technology then, to form the active area of peripheral circuit region.
Optionally, described peripheral circuit region comprises first device region and second device region, forms earlier on the insulative sidewall of peripheral circuit region surface to sacrifice the step that sidewall is manufactured with the source region then and comprise: in the memory cell array district that forms insulative sidewall and the peripheral circuit region surface form first sacrificial dielectric layer; Etching is positioned at first sacrificial dielectric layer of first device region, forms first on the insulative sidewall surface of first device region and sacrifices sidewall, and utilize patterned photoresist to carry out the first ion doping technology in first device region; Remove described photoresist, first sacrificial dielectric layer and the first sacrifice sidewall; In described memory cell array district and peripheral circuit region surface form second sacrificial dielectric layer; Etching is positioned at second sacrificial dielectric layer of second device region, form second on the insulative sidewall surface of second device region and sacrifice sidewall, and utilize patterned photoresist in second device region, to carry out the second ion doping technology, the described second ion doping technology is opposite with the doping type of the first ion doping technology; Remove described photoresist, second sacrificial dielectric layer and the second sacrifice sidewall.
Optionally, the material of described insulative sidewall is silicon nitride, silica or its combination.Concrete, described insulative sidewall is silica-silicon-nitride and silicon oxide composite construction.
Optionally, described first device region is the nmos pass transistor district, and described second device region is the PMOS transistor area.The active area that forms peripheral circuit region comprises: carry out N-type ion doping and P type ion doping respectively in nmos pass transistor district and PMOS transistor area.
Optionally, the material of described first sacrificial dielectric layer and second sacrificial dielectric layer is amorphous carbon.Described removal mask, first sacrificial dielectric layer, second sacrificial dielectric layer and first are sacrificed sidewall, the second sacrifice sidewall comprises: under the oxygen gas plasma environment, carry out cineration technics.The temperature range of described cineration technics is 100 ℃～350 ℃.
Optionally, also be included in the memory cell array district and carry out the step that ion doping is formed with the source region.
The present invention sacrifices sidewall by forming on the insulative sidewall of peripheral circuit region surface, when carrying out ion doping technology to solve peripheral circuit region to the demand of device withstand voltage, thereby enlarged the process window that forms insulative sidewall, improve the yield of product.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 is existing flash memory cross-sectional view;
Fig. 2 is the schematic flow sheet of flash memory manufacturing method of the present invention;
Fig. 3 is the schematic flow sheet of step S3 among Fig. 2;
Fig. 4 to Figure 16 is the generalized section of embodiment of the invention flash memory manufacturing method.
Embodiment
In the existing flash memory manufacturing method, because the sidewall of memory cell array district and peripheral circuit region forms simultaneously, thereby is difficult to satisfy the different demands of above-mentioned zone oppose side wall thickness, caused sidewall formation process window too small.The present invention forms by the insulative sidewall surface at peripheral circuit region and sacrifices sidewall, carry out the ion doping technology of peripheral circuit region again, thereby device withstand voltage in the raising peripheral circuit region has reduced the thickness requirement to insulative sidewall, has enlarged the formation process window of insulative sidewall.
Fig. 2 is the schematic flow sheet of flash memory manufacturing method of the present invention, and basic step comprises:
S1, provide semiconductor structure, described semiconductor structure comprises memory cell array district and peripheral circuit region;
Wherein, described memory cell array district and peripheral circuit region are formed with the different semiconductor device of integrated level.Usually, the gate pitch in memory cell array district is less than the gate pitch in the peripheral circuit region.
S2, form insulative sidewall at the grid structure of memory cell array district and peripheral circuit region;
Wherein, the insulative sidewall of memory cell array district and peripheral circuit region forms simultaneously, bag expands at above-mentioned semiconductor structure surface deposition one deck insulating medium layer, the described insulating medium layer of etching then, side at grid structure forms insulative sidewall, the insulative sidewall consistency of thickness of described memory cell array district and peripheral circuit region.
S3, form on the insulative sidewall of described peripheral circuit region surface and to sacrifice sidewall, carry out ion doping technology then, to form the active area of peripheral circuit region, remove described sacrifice sidewall then.
Wherein, in order to form the active area of corresponding doping type in the different components zone in peripheral circuit region, described ion doping technology needs to carry out twice at least, supposes that peripheral circuit region comprises first device region and second device region.After the active area that finishes peripheral circuit region is made, sacrificing sidewall will be removed.As shown in Figure 3, concrete steps comprise:
S301, in the memory cell array district that forms insulative sidewall and peripheral circuit region surface form first sacrificial dielectric layer; Above-mentioned sacrificial dielectric layer is overlying on insulative sidewall and other part surfaces of memory cell array district and peripheral circuit region.
S302, etching are positioned at first sacrificial dielectric layer of first device region, form first on the insulative sidewall surface of first device region and sacrifice sidewall, and use mask to carry out the first ion doping technology in first device region; Remove described mask, first sacrificial dielectric layer and the first sacrifice sidewall then.
S303, in described memory cell array district and peripheral circuit region surface form second sacrificial dielectric layer; For simplifying technology, described second sacrificial dielectric layer is with the first sacrificial dielectric layer material, thickness, formation technology can be identical.
S304, etching are positioned at second sacrificial dielectric layer of second device region, insulative sidewall surface in second device region forms second and sacrifices sidewall, and use mask in second device region, to carry out the second ion doping technology, the described second ion doping technology is opposite with the doping type of the first ion doping technology; Remove described mask, second sacrificial dielectric layer and the second sacrifice sidewall.
Below in conjunction with specific embodiment, the present invention is done further introduction.Fig. 4 to Figure 16 is the generalized section of embodiment of the invention flash memory manufacturing method.
As shown in Figure 4, semiconductor structure is provided, described semiconductor structure is divided into memory cell array district I and peripheral circuit region II, and each district includes Semiconductor substrate 100 and is formed at semiconductor device (for example transistor, memory cell etc.) on the Semiconductor substrate 100.Wherein, the semiconductor device integrated level of memory cell array district I is greater than peripheral circuit region II, and is concrete, and the spacing of grid 201 is greater than the spacing of grid 202 among the peripheral circuit region II among the described memory cell array district I.Present embodiment is example with the cmos device of routine, and described peripheral circuit region II comprises nmos transistor region II-1 and PMOS transistor area II-2.
Need be pointed out that separately that present embodiment does not represent described semiconductor device and only comprises grid with the size of the gate pitch integrated level with the signal device.In addition, in memory cell array district I, usually grid 201 also comprises structures such as control gate, floating boom and erase gate, with the structure of grid 202 among the peripheral circuit region II, size etc. and inequality.But be simplified model in Fig. 4, only simply illustrate the grid of memory cell array district I and peripheral circuit region II, explanation hereby.Follow-up described each regional insulative sidewall is formed at the vertical side surface of above-mentioned grid.
As shown in Figure 5, (being the surface of Semiconductor substrate 100 and grid 201, grid 202) forms insulating medium layer 300 on semiconductor structure surface shown in Figure 4.
Described insulating medium layer 300 is used for etching and forms insulative sidewall, and its material can be silica, silicon nitride or its combination.In the present embodiment, described insulating medium layer is silica-silicon-nitride and silicon oxide (O-N-O) composite bed.Concrete formation technology comprises: on above-mentioned semiconductor structure surface, at first adopt chemical vapor deposition method or high-temperature thermal oxidation method (HTO) to form first silicon oxide film 301; Adopt chemical vapor deposition method to form silicon nitride film 302 on the surface of first silicon oxide film 301 then; Adopt chemical vapor deposition method to form tetraethoxysilane (TEOS) layer on the surface of described silicon nitride film 302 at last, described TEOS layer is carried out heat treated, make it be decomposed to form second silicon oxide film 303.
It is pointed out that above-mentioned insulating medium layer 300 (silica-silicon-nitride and silicon oxide composite bed) is used for etching and forms insulative sidewall, and the thickness of the thickness of described insulative sidewall and insulating medium layer 300 is basic identical.Therefore the thickness of described insulating medium layer 300 should guarantee that the insulative sidewall that forms satisfies the demand of memory cell array district I, to avoid forming defective between the neighboring gates in memory cell array district I.
As shown in Figure 6, adopt plasma etching industrial, the described insulating medium layer 300 of etching forms insulative sidewall 400 in the vertical side surface of the grid 202 of the grid 201 of memory cell array district I and peripheral circuit region II.
As optional scheme, in above-mentioned silica-silicon-nitride and silicon oxide composite bed, first silicon oxide film 301 can be used as etching barrier layer, simultaneously the semiconductor device of protection bottom.Further carry out the plasma etching of substep, etching second silicon oxide film 303 at first is until exposing silicon nitride film 302; The etch silicon nitride film 302 then, until exposing first silicon oxide film 301.Through behind the above-mentioned step etching; form the insulative sidewall 400 of silica-silicon-nitride and silicon oxide composite construction on the vertical side surface of grid 201 and grid 202; and top portions of gates, Semiconductor substrate 100 surfaces all remain with first silicon oxide film 301, and described first silicon oxide film 301 can be protected grid in follow-up etching technics.
Usually after the making of finishing insulative sidewall 400, just can carry out the making of active area among the memory cell array district I.With respect to peripheral circuit region II, the semiconductor device of memory cell array district I is more intensive, and the active area degree of depth is more shallow, and the resistance to pressure requirement to semiconductor device when ion doping is also lower, and described insulative sidewall 400 can satisfy memory cell array district I and carry out the demand that active area forms technology.In addition, the active area of described memory cell array district I forms technology, can also carry out after the active area of finishing peripheral circuit region II forms technology.
As shown in Figure 7, the semiconductor structure surface that forms in the described step of Fig. 6 forms first sacrificial dielectric layer 501, makes described first sacrificial dielectric layer 501 be covered in insulative sidewall 400 surfaces.Described first sacrificial dielectric layer is used for forming the sacrifice sidewall on insulative sidewall 400 surfaces of peripheral circuit region II, has insulating property (properties), should have any different so that the subsequent technique selective removal with insulative sidewall 400 simultaneously.In the present embodiment, the material of described first sacrificial dielectric layer 501 is amorphous carbon.
As shown in Figure 8, at the surperficial spin coating photoresist of memory cell array district I, peripheral circuit region II, and carry out patterning, expose the nmos transistor region II-1 among the peripheral circuit region II.Photoresist described in the figure is only to block the relevant range with signal.
As shown in Figure 9, in described nmos transistor region II-1, as etching barrier layer, first sacrificial dielectric layer 501 is carried out etching with first silicon oxide film 301, form first on these regional insulative sidewall 400 surfaces and sacrifice sidewall 502.
As shown in figure 10, at described nmos transistor region II-1, carry out the N-type ion doping in the Semiconductor substrate 100 of grid 202 both sides, be formed with source region (source/drain electrode of nmos pass transistor).
As shown in figure 11, photoresist, first sacrifice layer of removing on memory cell array district I, the peripheral circuit region II 501 and first sacrificed sidewall 502.In the present embodiment, the material that described first sacrifice layer 501/ first is sacrificed sidewall 502 is amorphous carbon, therefore can be under the oxygen gas plasma environment, adopt cineration technics that above-mentioned photoresist, first sacrifice layer 501 and first are sacrificed sidewall 502 and remove in the lump, temperature range is 100 ℃～350 ℃.Because amorphous carbon forms carbon monoxide or carbon dioxide after ashing, so can remove fully and can be not residual.
As shown in figure 12, form second sacrificial dielectric layer 601 on the surface of memory cell array district I, peripheral circuit region II, make described second sacrificial dielectric layer 601 be covered in insulative sidewall 400 surfaces.For simplifying technology, the material of described second sacrificial dielectric layer 601 is identical with first sacrificial dielectric layer 501.
As shown in figure 13, at the surperficial spin coating photoresist of memory cell array district I, peripheral circuit region II, and carry out patterning, expose the PMOS transistor area II-2 among the peripheral circuit region II.
As shown in figure 14, in described PMOS transistor area II-2, as etching barrier layer, second sacrificial dielectric layer 601 is carried out etching with first silicon oxide film 301, form second on these regional insulative sidewall 400 surfaces and sacrifice sidewall 602.
It is pointed out that described second thickness and first of sacrificing sidewall 602 is sacrificed sidewall 601 can be inequality, with satisfied requirement to device withstand voltage when carrying out dissimilar ion doping.
As shown in figure 15, at described PMOS transistor area II-2, carry out P type ion doping in the Semiconductor substrate 100 of grid 202 both sides, be formed with source region (the transistorized source of PMOS/drain electrode).
As shown in figure 16, photoresist, second sacrifice layer of removing on memory cell array district I, the peripheral circuit region II 601 and second sacrificed sidewall 602.This step is identical with the described step of Figure 11, can adopt cineration technics.
In addition, nmos transistor region II-1 among the peripheral circuit region II and PMOS transistor area II-2 are carried out the ion doping of respective type, be not limited to the order of above-described embodiment, can also carry out the ion doping of PMOS transistor area II-2 earlier, carry out the ion doping of MOS transistor zone II-1 again, only need to change the sequencing of technological process, repeat no more herein.
Through after the above-mentioned technology, form the active area of flash memory.The present invention is the requirement of satisfying the device withstand voltage of peripheral circuit region II, only outside the insulative sidewall of peripheral circuit region II, form the sacrifice sidewall, make when peripheral circuit region II carries out ion doping that the actual sidewall thickness of grid 202 is insulative sidewall and the thickness sum of sacrificing sidewall.And after finishing ion doping, remove described sacrifice sidewall.When not influencing device architecture, enlarged the formation process window of insulative sidewall, improved the yield of product.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the manufacture method of a flash memory is characterized in that, comprising:
Semiconductor structure is provided, and described semiconductor structure comprises memory cell array district and peripheral circuit region,
Described memory cell array district and peripheral circuit region have grid structure respectively;
Grid structure surface at memory cell array district and peripheral circuit region forms insulative sidewall;
Only form on the insulative sidewall surface of described peripheral circuit region and sacrifice sidewall, carry out ion doping technology then, to form the active area of peripheral circuit region;
Wherein, described peripheral circuit region comprises first device region and second device region, and the step that is manufactured with the source region at the insulative sidewall surface of peripheral circuit region elder generation formation sacrifice sidewall then comprises:
In the memory cell array district that forms insulative sidewall and peripheral circuit region surface form first sacrificial dielectric layer;
Etching is positioned at first sacrificial dielectric layer of first device region, forms first on the insulative sidewall surface of first device region and sacrifices sidewall, and utilize patterned photoresist to carry out the first ion doping technology in first device region;
Remove described photoresist, first sacrificial dielectric layer and the first sacrifice sidewall;
In described memory cell array district and peripheral circuit region surface form second sacrificial dielectric layer;
Etching is positioned at second sacrificial dielectric layer of second device region, form second on the insulative sidewall surface of second device region and sacrifice sidewall, and utilize patterned photoresist in second device region, to carry out the second ion doping technology, the described second ion doping technology is opposite with the doping type of the first ion doping technology;
Remove described photoresist, second sacrificial dielectric layer and the second sacrifice sidewall.
2. manufacture method as claimed in claim 1 is characterized in that, the material of described insulative sidewall is silicon nitride, silica or its combination.
3. manufacture method as claimed in claim 2 is characterized in that, described insulative sidewall is silica-silicon-nitride and silicon oxide composite construction.
4. manufacture method as claimed in claim 1 is characterized in that, described first device region is the nmos pass transistor district, and described second device region is the PMOS transistor area.
5. manufacture method as claimed in claim 4 is characterized in that, the active area that forms peripheral circuit region comprises: carry out N-type ion doping and P type ion doping respectively in nmos pass transistor district and PMOS transistor area.
6. manufacture method as claimed in claim 1 is characterized in that, the material of described first sacrificial dielectric layer and second sacrificial dielectric layer is amorphous carbon.
7. manufacture method as claimed in claim 6 is characterized in that, described removal photoresist, first sacrificial dielectric layer, second sacrificial dielectric layer and first are sacrificed sidewall, the second sacrifice sidewall comprises: under the oxygen gas plasma environment, carry out cineration technics.
8. manufacture method as claimed in claim 7 is characterized in that, the temperature range of described cineration technics is 100 ℃～350 ℃.
9. manufacture method as claimed in claim 1 is characterized in that, also is included in the memory cell array district and carries out the step that ion doping is formed with the source region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010292464 CN102412206B (en) | 2010-09-19 | 2010-09-19 | Manufacture method of flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010292464 CN102412206B (en) | 2010-09-19 | 2010-09-19 | Manufacture method of flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102412206A CN102412206A (en) | 2012-04-11 |
| CN102412206B true CN102412206B (en) | 2013-10-09 |
Family
ID=45914216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010292464 Active CN102412206B (en) | 2010-09-19 | 2010-09-19 | Manufacture method of flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102412206B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952803A (en) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998045876A1 (en) * | 1997-04-10 | 1998-10-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and method for manufacturing the same |
| CN1420542A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Method for mfg. semiconductor devcie used in system chip |
| KR20040071527A (en) * | 2003-02-06 | 2004-08-12 | 삼성전자주식회사 | Method of fabricating a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit fabricated thereby |
| CN101238559A (en) * | 2005-08-02 | 2008-08-06 | 美光科技公司 | Method of forming memory circuitry with different insulative sidewall spacers |
| CN101459138A (en) * | 2008-12-30 | 2009-06-17 | 上海宏力半导体制造有限公司 | Manufacturing method for mask read only memory device |
-
2010
- 2010-09-19 CN CN 201010292464 patent/CN102412206B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998045876A1 (en) * | 1997-04-10 | 1998-10-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and method for manufacturing the same |
| CN1420542A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Method for mfg. semiconductor devcie used in system chip |
| KR20040071527A (en) * | 2003-02-06 | 2004-08-12 | 삼성전자주식회사 | Method of fabricating a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit fabricated thereby |
| CN101238559A (en) * | 2005-08-02 | 2008-08-06 | 美光科技公司 | Method of forming memory circuitry with different insulative sidewall spacers |
| CN101459138A (en) * | 2008-12-30 | 2009-06-17 | 上海宏力半导体制造有限公司 | Manufacturing method for mask read only memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102412206A (en) | 2012-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100490158C (en) | Semiconductor strcture and its making method | |
| CN102104044B (en) | Separate gate flash memory and manufacturing method thereof | |
| KR100801078B1 (en) | Non volatile memory integrate circuit having vertical channel and fabricating method thereof | |
| US8450789B2 (en) | Memory array with an air gap between memory cells and the formation thereof | |
| KR100894772B1 (en) | Semiconductor memory device and Method of manufacturing thereof | |
| CN106653758B (en) | Method for manufacturing flash memory | |
| US9530683B2 (en) | Forming source/drain zones with a dielectric plug over an isolation region between active regions | |
| US8193576B2 (en) | Semiconductor memory device and method of fabricating the same | |
| CN110310926B (en) | Method for solving defect formation of metal silicide of SRAM unit device | |
| CN102364675B (en) | Method for forming flash memory | |
| CN103178019A (en) | Method for manufacturing word lines of embedded flash memory | |
| CN102412206B (en) | Manufacture method of flash memory | |
| CN100353527C (en) | Method for producing elements with memory cells and memory cell array | |
| TWI288462B (en) | One time programmable memory and the manufacturing method thereof | |
| KR100393306B1 (en) | Semiconductor device and method of manufacturing the same | |
| TWI685948B (en) | Memory structure and manufacturing method thereof | |
| KR100852236B1 (en) | Eeprom device and method of manufacturing the eeprom device | |
| US7183607B1 (en) | Non-volatile memory structure | |
| CN102522408B (en) | Disposable programmable memory and manufacture method | |
| KR100733144B1 (en) | Non-volatile memory device and method of forming non-volatile memory device | |
| KR20090092927A (en) | Semiconductor memory device and manufacturing method thereof | |
| US7294548B2 (en) | Semiconductor device and fabricating method thereof | |
| CN105244321B (en) | A kind of semiconductor devices and its manufacturing method and electronic device | |
| US8236649B2 (en) | Semiconductor memory device with spacer shape floating gate and manufacturing method of the semiconductor memory device | |
| CN100397597C (en) | Method for producing metal-oxide semiconductor electric crystal and memory body elements |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA Effective date: 20121101 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121101 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |