CN102104044B - Separate gate flash memory and manufacturing method thereof - Google Patents
Separate gate flash memory and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a separate gate flash memory and a manufacturing method thereof. The separate gate flash memory comprises a semiconductor substrate, a tunnelling oxidation layer, a floating gate, a gate dielectric layer, a control gate, a control gate side wall layer, a side wall oxidation layer, a source electrode, a drain electrode, an erasure gate oxidation layer, an erasure gate, a word line and a raised vertex angle, wherein the tunnelling oxidation layer, the floating gate, the gate dielectric layer and the control gate are sequentially formed on the semiconductor substrate; the control gate side wall layer covers on the side wall of the control gate; the side wall oxidation layer covers on the surface of the control gate side wall layer and the side wall of the floating gate; the source electrode and the drain electrode are formed in the semiconductor substrate and respectively positioned at both sides of the tunnelling oxidation layer; the erasure gate oxidation layer is formed on the source electrode; the erasure gate is formed on the erasure gate oxidation layer; the word line is formed on the drain electrode; and the raised vertex angle is positioned at one side of the floating gate, which is adjacent to the erasure gate. The separate gate flash memory has high erasure efficiency, can integrally greatly enhance the efficiency of a device, does not need to intentionally increase the width of the word line during layout design because the width of the word line is not influenced and has the advantages of good amalgamation with the traditional process and stable product property without increasing redundant mask plates.
Description
Technical field
The present invention relates to a kind of separated grid electrode type quick flashing storage and manufacture method thereof, belong to technical field of semiconductors.
Background technology
Along with the development of semiconductor technology, flash memory (flash memory) is widely used as a kind of non-volatility memorizer.Flash memory has increased a floating boom and one deck tunnel oxide on traditional mos transistor structure basis, and utilizes floating boom to come stored charge, thereby has realized the non-volatile of memory contents.
Fig. 1 is a typical separate gate flash memory, it comprises the semiconductor base 100 with source electrode 111 and drain electrode (not shown), be formed on tunnel oxide 101 on the semiconductor base 100 in the mode of storehouse successively, floating boom 102, dielectric layer 103 between grid, control gate 104, control gate silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107, also comprise the control gate side wall layer 108 that is formed on control gate 104 both sides, be formed on the sidewall oxide 109 of control gate side wall layer 108 surfaces and floating boom 102 both sides, be formed with erase gate oxide layer 113 on the source electrode 111, be formed with erase gate 121 on the erase gate oxide layer 113, be formed with word line 122 in the drain electrode.
The action principle of above-mentioned separate gate flash memory is: when flash memory is carried out data write operation, apply a high positively biased and be pressed on control gate, so that hot electron passes tunnel oxide and injects floating boom from source electrode, programming time is generally the microsecond rank; When flash memory is carried out data erase, apply a high negative bias and be pressed on control gate, so that the aforementioned hot electron that is injected into floating boom utilizes Fu Lenuohai (Fowler-Nordheim, hereinafter to be referred as FN) the tunneling effect effect, pass sidewall oxide and flow into source electrode, erasing time is subject to the impact of FN tunneling effect, will be longer than programming time far away, sometimes even reach a millisecond rank.The long bottleneck that becomes the raising of restriction separate gate flash memory operating efficiency of erasing time.
Having put down in writing a kind of floating boom base angle in publication number is the patent of invention " separated grid electrode type quick flashing storage and manufacture method thereof " of CN1466224 is the device of acute angle, but it mainly can improve programming efficiency, little to the contribution that improves efficiency of erasing.
Summary of the invention
Technical problem to be solved by this invention is to improve the efficiency of erasing of separate gate flash memory, and does not affect other performance of device.
The technical solution adopted in the present invention is: a kind of separate gate flash memory comprises: Semiconductor substrate; Be formed on dielectric layer, control gate between tunnel oxide on the described Semiconductor substrate, floating boom, grid in the mode of storehouse successively; Cover the control gate side wall layer of the sidewall of dielectric layer and control gate between grid; Cover the sidewall oxide of control gate side wall layer surface and floating boom, tunnel oxide sidewall; Be formed in the described semiconductor base and lay respectively at source electrode and the drain electrode of described tunnel oxide both sides; Be formed on erase gate oxide layer on the source electrode, be formed on the erase gate oxide layer and the erase gate that contacts with sidewall oxide, be formed on the word line that drain electrode is upper and contact with sidewall oxide, feature is that the side that described floating boom and erase gate are adjacent has the drift angle of protrusion.
Preferably, described drift angle is that angle is 85 °～89 ° acute angle.
Preferred described drift angle overlaps with erase gate in the horizontal direction.The distance of described coincidence can be 10～90 dusts.
The present invention also proposes a kind of manufacture method of separate gate flash memory, comprises the steps:
Semiconductor base is provided, is forming successively dielectric layer between tunnel oxide, floating gate polysilicon, grid, control gate polysilicon, the first photoresist on the described semiconductor base;
Take the first photoresist as mask, adopt etching technics with dielectric layer between graphical control gate polysilicon, grid, the exposure floating gate polysilicon forms a plurality of the first grooves and the second groove, and patterned control gate polysilicon formation control grid are removed the first photoresist;
The sidewall formation control grid side wall layer of dielectric layer between control gate and grid forms sacrifice layer on control gate side wall layer surface;
In the first groove and the control gate hard mask layer of the first groove notch form the second photoresist, the floating gate polysilicon take the second photoresist as mask to the second groove bottom land carries out the first Implantation;
Take the second photoresist as mask, remove the sacrifice layer of the second recess sidewall, remove the second photoresist;
Take the control gate side wall layer of the sacrifice layer of control gate hard mask layer, the first recess sidewall, the second recess sidewall as mask, adopt etching technics with graphical floating gate polysilicon, tunnel oxide, the exposure semiconductor base, described patterned floating gate polysilicon forms floating boom;
Remove the sacrifice layer of the first recess sidewall, be positioned at this moment and form the drift angle that protrudes on the floating boom of the first recess sidewall;
Form sidewall oxide on the sidewall of floating boom and tunnel oxide, the surface of control gate side wall layer, in the first groove, form and form the word line in erase gate, the second groove.
Because the employing of technique scheme, the present invention has the following advantages: (1) efficiency of erasing is high, can significantly improve on the whole the performance of memory; (2) floating boom only has drift angle in a side adjacent with erase gate, and have the structure identical with traditional separate gate flash memory in a side adjacent with the word line, the width that can guarantee like this word line is unaffected, need not deliberately increase the live width of word line when layout-design, other device performance is unaffected except efficiency of erasing; (3) memory of employing the present embodiment explained hereafter, have advantages of good with existing technique amalgamation, properties of product are stable, and this technique does not increase any unnecessary mask, do not increase photoetching process yet, can greatly improve performance of devices in the situation that the production cost increase is few.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the schematic diagram of an existing separate gate flash memory;
Fig. 2 to Figure 11 is the manufacture process schematic diagram of separate gate flash memory of the present invention;
Figure 12 is the enlarged drawing of drift angle among Figure 11.
Embodiment
The present invention at first provides a kind of manufacture process of separate gate flash memory, comprises the steps:
S1, semiconductor base is provided, form successively dielectric layer between tunnel oxide, floating gate polysilicon, grid, control gate polysilicon, control gate silicon nitride layer, control gate silicon oxide layer, control gate hard mask layer on the described semiconductor base, forming patterned the first photoresist at the control gate hard mask layer;
S2, take the first photoresist as mask, adopt dry etching with dielectric layer between graphical control gate hard mask layer, control gate silicon oxide layer, control gate silicon nitride layer, control gate polysilicon, grid, the exposure floating gate polysilicon, form a plurality of the first grooves and the second groove, described patterned control gate polysilicon formation control grid are removed the first photoresist;
S3 in control gate sidewall formation control grid side wall layer, forms sacrifice layer on control gate side wall layer surface;
S4, in the first groove and the control gate hard mask layer of the first groove notch form the second photoresist, the floating gate polysilicon take the second photoresist as mask to the second bottom portion of groove carries out the first Implantation;
S5 take described the second photoresist as mask, removes the sacrifice layer of the second recess sidewall, removes the second photoresist;
S6, take the control gate side wall layer of the sacrifice layer of control gate hard mask layer, the first recess sidewall, the second recess sidewall as mask, adopt dry etching with graphical floating gate polysilicon, tunnel oxide, the exposure semiconductor base, described patterned floating gate polysilicon forms floating boom;
S7 removes the sacrifice layer of the first recess sidewall, is positioned at this moment on the floating boom of the first recess sidewall to form the drift angle that protrudes;
S8 forms sidewall oxide on sidewall, the control gate side wall layer surface of floating boom, forms in the first groove and forms the word line in erase gate, the second groove.
Be described in detail below in conjunction with 2 to 11 pairs of above-mentioned manufacturing steps of accompanying drawing.
S1, semiconductor base is provided, form successively dielectric layer between tunnel oxide, floating gate polysilicon, grid, control gate polysilicon, control gate silicon nitride layer, control gate silicon oxide layer, control gate hard mask layer on the described semiconductor base, forming patterned the first photoresist at the control gate hard mask layer;
Referring to Fig. 2, provide semiconductor base 100, such as substrate (part that comprises integrated circuit and other elements) of silicon chip, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes etc.Adopt existing technique (for example chemical vapour deposition (CVD), thermal oxidation method), forming successively dielectric layer 103, control gate polysilicon 104 between tunnel oxide 101, floating gate polysilicon 102, grid on the described semiconductor base 100, afterwards can also be on control gate polysilicon 104 successively formation control grid silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107.Wherein tunnel oxide 101 can be silicon oxide layer, thickness 50～200 dusts, floating gate polysilicon 102 and control gate polysilicon 104 thickness can be 500～2000 dusts, and dielectric layer 103 is generally the oxide layer-nitride layer-oxide layer composite bed of (being called for short ONO), thickness 50～500 dusts between grid.Control gate silicon nitride layer 105, control gate silicon oxide layer 106 mainly play the effect of isolation, protection control gate polysilicon 104, and control gate hard mask layer 107 will at first be etched in S2, and after step in play the effect of mask.
Spin coating photoresist on described control gate hard mask layer 107, and utilize developing manufacture process to form patterned the first photoresist 201.
S2, take the first photoresist as mask, adopt dry etching with dielectric layer between graphical control gate hard mask layer, control gate silicon oxide layer, control gate silicon nitride layer, control gate polysilicon, grid, the exposure floating gate polysilicon, form a plurality of the first grooves and the second groove, described patterned control gate polysilicon formation control grid are removed the first photoresist;
At first take the first photoresist 201 as mask, adopt dry etching to form patterned control gate hard mask layer 107, then again take the first photoresist 201 and control gate hard mask layer 107 as mask, adopt dry etching with dielectric layer 103 between graphical control gate silicon oxide layer 106, control gate silicon nitride layer 105, control gate polysilicon 104, grid, exposure floating gate polysilicon 102, form a plurality of the first grooves 401 and the second groove 402, wherein the first groove 401 is corresponding with the final erase gate that forms, and the second groove 402 is corresponding with the final word line that forms.Above-mentioned graphical control gate polysilicon 104 is with regard to the formation control grid, and in order to embody the contact of the two, control gate polysilicon and control gate all represent with label 104.Can adopt ashing method to remove the first photoresist this moment, and this step forms structure shown in Figure 3 after finishing.
S3 in control gate sidewall formation control grid side wall layer, forms sacrifice layer on control gate side wall layer surface;
Referring to Fig. 4, at first in the sidewall formation control grid side wall layer 108 of control gate 104, this control gate side wall layer 108 can be silica-silicon nitride composite construction of (being called for short ON), thickness 100～500 dusts.When adopting existing technique (for example chemical vapour deposition (CVD), thermal oxidation) formation control grid side wall layer 108, this control gate side wall layer 108 is dielectric layer 103, control gate silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107 between covering gate also.
Then, form sacrifice layer 300 on control gate side wall layer 108 surfaces, sacrifice layer 300 has with control gate side wall layer 108 selective etchings than high characteristic, above-mentioned control gate side wall layer 108 is the composite construction of ON, then sacrifice layer 300 can be selected the silica of silica or doping, has with the silicon nitride selective etching than high characteristics.
S4, in the first groove and the control gate hard mask layer of the first groove notch form the second photoresist, take the second photoresist as mask the floating gate polysilicon in the second groove is carried out the first Implantation;
Referring to Fig. 5, spin coating photoresist in the first groove 401, the second groove 402 and on the control gate hard mask layer 107, utilize developing technique to form patterned the second photoresist 202, this second photoresist 202 covers the control gate hard mask layer 107 of the first groove 401 and the first groove 401 notches.
Take above-mentioned the second photoresist 202 as mask, the floating gate polysilicon 102 of the second groove 402 bottom lands is carried out the first Implantation, what for example inject is the boron ion, and energy is 10～30KeV, and dosage is 5～10E12/cm
2Can comprise the step of annealing after the first Implantation to impel ion to diffuse to semiconductor base 100, this Implantation mainly plays the effect of adjusting threshold voltage.
S5 take described the second photoresist as mask, removes the sacrifice layer of the second recess sidewall, removes the second photoresist;
Referring to Fig. 6, take described the second photoresist 202 as mask, wet method is removed the sacrifice layer 300 that is exposed to outer the second groove 402 sidewalls.When the material of this sacrifice layer 300 is silica, can be that the solution of hydrofluoric acid carries out wet etching by active ingredient, the mass concentration of the HF in this solution is carried out wet etching less than or equal to 2% with room temperature, and etch rate is 20～60nm/ minute.When the sacrifice layer in the second groove 402 be removed complete after, the sacrifice layer of the first groove 401 sidewalls is owing to the protection with second photoresist 202 keeps intact.Certainly, if the material of sacrifice layer 300 changes, lithographic method also may change thereupon, and the present embodiment is not for the removal method that limits sacrifice layer 300.
Referring to Fig. 7, ashing method is removed the second photoresist 202.
S6, take the control gate side wall layer of the sacrifice layer of control gate hard mask layer, the first recess sidewall, the second recess sidewall as mask, adopt dry etching with graphical floating gate polysilicon, tunnel oxide, the exposure semiconductor base, described patterned floating gate polysilicon forms floating boom;
Referring to Fig. 8, take the control gate side wall layer 108 of the sacrifice layer 300 of the reservation of control gate hard mask layer 107, the first recess sidewall 401, the 402 sidewall exposures of the second groove as mask, adopt dry etching with graphical floating gate polysilicon 102, tunnel oxide 101, exposure semiconductor base 100, described patterned floating gate polysilicon 102 forms floating boom, for keeping continuity, floating boom is also with label 102 expressions.
Can find out in Fig. 8, the floating boom 102 that is positioned at the first groove 401 sidewalls is compared the floating boom 102 relative control gates 104 that are positioned at the second groove 402 sidewalls and is more protruded in the horizontal direction, and the width of protrusion is the thickness of sacrifice layer 300.And because dry etching inevitably also causes micro etch to the sidewall of floating boom 102, so that the sidewall of floating boom 102 slightly caves inward, and the top of floating boom 102 is subject to the protection of sacrifice layer 300 or control gate side wall layer 108 and remain intact.
S7 removes the sacrifice layer of the first recess sidewall, is positioned at this moment on the floating boom of the first recess sidewall to form the drift angle that protrudes;
Referring to Fig. 9, still adopting active ingredient is the sacrifice layer 300 that the solution wet etching of hydrofluoric acid is removed the first groove 401 sidewalls, is positioned at this moment on the floating boom 102 of the first groove 401 sidewalls to form the drift angle 102a that protrudes.Above-mentioned S6 dry etching forms in the process of floating boom 102; the sidewall of floating boom 102 is subject to micro etch; so that the vertical edge of described drift angle 102a is slightly to floating boom 102 inboard depressions; and the horizontal sides of drift angle 102a caves in not obvious owing to obtaining the protection of sacrifice layer 300 to floating boom 102 inboards; comprehensive result is the acute angle state that drift angle 102a is 85 °～89 ° of scopes, but not theoretic right angle.
S8 forms sidewall oxide on sidewall, the control gate side wall layer surface of floating boom, forms in the first groove and forms the word line in erase gate, the second groove.
Referring to Figure 10, adopt chemical vapour deposition (CVD) or thermal oxidation method to form sidewall oxide 109 on sidewall, control gate side wall layer 108 surfaces of floating boom 104, such as silica, the distance that the thickness of this sidewall oxide 109 should stretch out less than the relative control gate side wall layer 108 of drift angle 102a.
Referring to Figure 11, form erase gate oxide layers 113 at the semiconductor base 100 of the bottom land of the second groove 401, such as silica.In the first groove 401 and the second groove 402 interior deposit spathic silicons, with at the first groove 401 interior formation erase gates 121, at the second groove 402 interior formation word lines 122.The follow-up making step that can also comprise interconnection line repeats no more.
In Figure 10, because the distance that the thickness of sidewall oxide 109 should stretch out less than the relative control gate side wall layer 108 of drift angle 102a, then in Figure 11, drift angle 102a and erase gate 121 partially overlap in the horizontal direction, this coincidence be 10 during to 90 dust apart from F (referring to the enlarged drawing of Figure 12), more preferably during 50 dust, has more excellent effect at the boost device efficiency of erasing.
The present embodiment also proposes a kind of separate gate flash memory, referring to Figure 11, comprising: semiconductor base 100; Be formed on dielectric layer 103, control gate 104, control gate silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107 between tunnel oxide 101 on the semiconductor base 100, floating boom 102, grid in the mode of storehouse successively; Cover the control gate side wall layer 108 of dielectric layer 103 between grid, control gate 104, control gate silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107 sidewalls; Cover the sidewall oxide 109 of described control gate side wall layer 108 surfaces and tunnel oxide 101, floating boom 102 sidewalls; Be formed in the described semiconductor base 100 and lay respectively at source electrode 111 and the drain electrode of tunnel oxide 101 both sides; Be formed on erase gate oxide layer 113 on the source electrode 111, be formed on the erase gate oxide layer 113 and the erase gate 121 that contacts with sidewall oxide 109, being formed on drain electrode upper and contact with sidewall oxide 109 word line 122, wherein floating boom 102 and erase gate 121 adjacent sides have the drift angle 102a of protrusion.
Adopt the memory of above structure, have advantages of that efficiency of erasing is high, this is that drift angle 102a can reduce the channel voltage of FN tunneling effect because of the first, flows into erase gates 121 so that hot electron is easier from floating boom 102; The second, drift angle 102a stretches in the erase gate 121, is conducive to point discharge, can promote the electric current that hot electron forms in the erase process, further promotes efficiency of erasing.
Above-mentioned memory also has another characteristics, floating boom 102 only has drift angle in a side adjacent with erase gate 121, and have the structure identical with traditional separate gate flash memory with word line 122 adjacent sides, the width that can guarantee like this word line is unaffected, need not deliberately increase the live width of word line when layout-design, other device performance is unaffected except efficiency of erasing.
Adopt the memory of the present embodiment explained hereafter, have advantages of good with existing technique amalgamation, properties of product are stable, and this technique do not increase any unnecessary mask, do not increase photoetching process yet, in the situation that production cost increases and seldom can greatly improve performance of devices.
Although the present invention with preferred embodiment openly as above; but it is not to limit claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (5)
1. the manufacture method of a separate gate flash memory comprises the steps:
Semiconductor base is provided, is forming successively dielectric layer between tunnel oxide, floating gate polysilicon, grid, control gate polysilicon, control gate hard mask layer, the first photoresist on the described semiconductor base;
Take the first photoresist as mask, adopt etching technics with dielectric layer between graphical control gate polysilicon, grid, the exposure floating gate polysilicon forms a plurality of the first grooves and the second groove, and patterned control gate polysilicon formation control grid are removed the first photoresist;
The sidewall formation control grid side wall layer of dielectric layer between control gate and grid forms sacrifice layer on control gate side wall layer surface;
In the first groove and the control gate hard mask layer of the first groove notch form the second photoresist, the floating gate polysilicon take the second photoresist as mask to the second groove bottom land carries out the first Implantation;
Take the second photoresist as mask, remove the sacrifice layer of the second recess sidewall, remove the second photoresist;
Take the control gate side wall layer of the sacrifice layer of control gate hard mask layer, the first recess sidewall, the second recess sidewall as mask, adopt etching technics with graphical floating gate polysilicon, tunnel oxide, the exposure semiconductor base, described patterned floating gate polysilicon forms floating boom;
Remove the sacrifice layer of the first recess sidewall, be positioned at this moment and form the drift angle that protrudes on the floating boom of the first recess sidewall;
Form sidewall oxide on the sidewall of floating boom and tunnel oxide, the surface of control gate side wall layer, in the first groove, form and form the word line in erase gate, the second groove.
2. manufacture method according to claim 1 is characterized in that: described sacrifice layer for control gate side wall layer selective etching than high material.
3. manufacture method according to claim 2, it is characterized in that: described control gate side wall layer is the composite construction of silica-silicon nitride.
4. manufacture method according to claim 3, it is characterized in that: described sacrifice layer is silica.
5. manufacture method according to claim 4, it is characterized in that: the sacrifice layer of described removal the first recess sidewall and the sacrifice layer of the second recess sidewall are for adopting wet etching, etching solution is that active ingredient is the etching solution of hydrofluoric acid, and the mass concentration of HF is less than or equal to 2% in this etching solution.
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| CN102097384B (en) * | 2009-12-15 | 2013-05-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing storage device |
| CN103165615B (en) * | 2011-12-19 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Split-gate flash memory and forming method thereof |
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| CN105355601B (en) * | 2014-08-21 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | The production method and nonvolatile memory of nonvolatile memory |
| CN105470127B (en) * | 2014-09-12 | 2018-11-09 | 上海华虹宏力半导体制造有限公司 | The production method for removing the method and flash memory of residual photoresist in deep trench |
| CN106298672B (en) * | 2015-05-15 | 2019-05-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof |
| CN106298483B (en) * | 2015-05-31 | 2019-08-27 | 中芯国际集成电路制造(上海)有限公司 | The production method of the production method and embedded flash memory of polysilicon gate |
| CN108257964B (en) | 2016-12-29 | 2020-11-10 | 无锡华润上华科技有限公司 | Flash memory device and manufacturing method thereof |
| CN106847818B (en) * | 2017-02-14 | 2020-05-01 | 上海华虹宏力半导体制造有限公司 | Preparation method of split-gate flash memory |
| US10658479B2 (en) | 2017-11-15 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flash memory cell structure with step-shaped floating gate |
| CN109830481A (en) * | 2019-03-20 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and its manufacturing method |
| CN110047943B (en) * | 2019-05-13 | 2022-12-20 | 武汉新芯集成电路制造有限公司 | Flash memory device and manufacturing method thereof |
| CN112234096A (en) * | 2020-10-27 | 2021-01-15 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and preparation method thereof |
| CN113013255A (en) * | 2021-03-24 | 2021-06-22 | 上海华虹宏力半导体制造有限公司 | Split-gate memory and manufacturing method thereof |
| CN113206010B (en) * | 2021-04-30 | 2023-10-24 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor device and method for manufacturing the same |
| CN113903789A (en) * | 2021-09-29 | 2022-01-07 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method and operating method thereof |
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