CN105355601B - The production method and nonvolatile memory of nonvolatile memory - Google Patents
The production method and nonvolatile memory of nonvolatile memory Download PDFInfo
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- CN105355601B CN105355601B CN201410414972.5A CN201410414972A CN105355601B CN 105355601 B CN105355601 B CN 105355601B CN 201410414972 A CN201410414972 A CN 201410414972A CN 105355601 B CN105355601 B CN 105355601B
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Abstract
This application discloses a kind of production method of nonvolatile memory and nonvolatile memories.Wherein, which includes the following steps：Basal body structure is formed, basal body structure includes substrate, the oxide skin(coating) and first grid material layer being sequentially formed on substrate, and at least a pair of of the second grid structure being formed in first grid material layer；Side wall medium layer is formed on the both sides side wall of each second grid structure, and forms sacrificial dielectric layer in first grid material layer；Etches sacrificial dielectric layer and first grid material layer are to exposing oxide skin(coating)；Removal is located at the side wall medium layer and first grid material layer in the outside of each pair of second grid structure, and using remaining first grid material layer as first grid；Etching oxidation nitride layer is to exposing substrate, and using remaining oxide skin(coating) as the first gate oxide layers.The production method can balance the etching degree of the inner side and outer side of second grid structure.
Description
Technical field
This application involves the technical fields of semiconductor integrated circuit, in particular to a kind of nonvolatile memory
Production method and nonvolatile memory.
Background technology
Nonvolatile memory (non-volatile memory) is that one kind remains to after power supply closing in retention tab
The memory of information, including electrically programmable read-only memory (EPROM) and flash memory (flash) etc..Nonvolatile memory has
System electric erasable, repeatable programming, the advantages that operating voltage is low and at low cost, it is made to be widely used in every field, example
Such as embedded system (including PC, network interconnection device and instrument and meter) and emerging voice, image, data store class product
Deng.
The production method that Fig. 1 to Fig. 4 shows existing nonvolatile memory.The production method includes the following steps：It is first
First, basal body structure is formed, basal body structure includes substrate 10 ', the oxide skin(coating) 21 ' and the first grid being sequentially formed on substrate 10 '
Pole material layer 31 ', and (including the gate medium of at least a pair of of second grid structure 40 ' that is formed in first grid material layer 31 '
Layer 41 ', second grid 42 ' and offset by gap wall 43 '), structure is as shown in Figure 1；Then, in each second grid structure 40 '
Side wall medium layer 51 ' is formed on the side wall of both sides, and above forms sacrificial dielectric layer 53 ' in first grid material layer 31 ', and then is formed
Basal body structure as shown in Figure 2；Next, forming side wall medium layer of the covering positioned at the inside of each pair of second grid structure 40 '
51 ' and oxide skin(coating) 21 ' photoresist layer 60 ', and then form basal body structure as shown in Figure 3；Next, removal is positioned at each pair of
The side wall medium layer 51 ' and first grid material layer 31 ' in the outside of second grid structure 40 ', and photoresist layer 60 ' is removed, into
And form basal body structure as shown in Figure 4；Finally, first grid material of the etching positioned at the outside of each pair of second grid structure 40 '
The bed of material 31 ' and oxide skin(coating) 21 ', and etch the sacrificial dielectric layer 53 ' positioned at the inside of each pair of second grid structure 40 ', first
Gate material layers 31 ' and oxide skin(coating) 21 ' are used as the first grid to exposing substrate 10 ', and by remaining first grid material layer 31 '
Pole 33 ' regard remaining oxide skin(coating) 21 ' as the first gate oxide layers 23 ', and then forms basal body structure as shown in Figure 5.
Form first grid 33 ' above by etching technics and the step of the first gate oxide layers 23 ' in, due to each pair of the
The outside of two gate structures 40 ' is formed with first grid material layer 31 ' and oxide skin(coating) 21 ', and each pair of second grid structure 40 '
Inside be formed with sacrificial dielectric layer 53 ', first grid material layer 31 ' and oxide skin(coating) 21 ', therefore be difficult by controlling etching
Step balances the etching degree of the inner side and outer side of second grid structure 40 '.If the degree of etching is excessive, it can make second gate
The substrate 10 ' in the outside of pole structure 40 ' will produce the defects of pit (pitting), and the of the outside of second grid structure 40 '
One gate material layers 31 ' also will produce the defects of notch (undercut).If the degree of etching is too small, second grid knot can be caused
The etch amount of the inside of structure 40 ' is inadequate, to generate the residue etc. of oxide skin(coating) 21 '.In view of the above-mentioned problems, not having also at present
There is effective solution method.
Invention content
The application is intended to provide a kind of production method and nonvolatile memory of nonvolatile memory, to balance second
The etching degree of the inner side and outer side of gate structure.
To achieve the goals above, this application provides a kind of production method of nonvolatile memory, the production methods
Include the following steps：Basal body structure is formed, basal body structure includes substrate, the oxide skin(coating) and the first grid being sequentially formed on substrate
Pole material layer, and at least a pair of of second grid structure for being formed in first grid material layer；In each second grid structure
Side wall medium layer is formed on the side wall of both sides, and forms sacrificial dielectric layer in first grid material layer；Etches sacrificial dielectric layer and
First grid material layer is to exposing oxide skin(coating)；Side wall medium layer and first of the removal positioned at the outside of each pair of second grid structure
Gate material layers, and using remaining first grid material layer as first grid；Etching oxidation nitride layer will be remained to exposing substrate
Remaining oxide skin(coating) is as the first gate oxide layers.
Further, it forms side wall medium layer and the step of sacrificial dielectric layer includes：Formed covering second grid structure and
The layer of dielectric material of first grid material layer；Etch media material layer, the medium that will be located on the side wall of second grid structure
Material layer as side wall medium layer, and using positioned at the layer of dielectric material of first grid material layer as sacrificial dielectric layer.
Further, the technique of etch media material layer is dry etching.
Further, after etch media material layer, using etching technics etches sacrificial dielectric layer in situ and first grid
Material layer is to exposing oxide skin(coating).
Further, it removes side wall medium layer and the step of first grid material layer includes：It forms covering and is located at each pair of the
The side wall medium layer of the inside of two gate structures and the photoresist layer of oxide skin(coating)；Removal is positioned at the outer of each pair of second grid structure
The side wall medium layer and first grid material layer of side；Remove photoresist layer.
Further, in the step of removing side wall medium layer and first grid material layer, first removal is located at each pair of second gate
The first grid material layer in the outside of pole structure, then removal are located at the side wall medium layer in the outside of each pair of second grid structure.
Further, the technique of removal first grid material layer is wet etching or dry etching.
Further, the technique of removal side wall medium layer is wet etching.
Further, second grid structure includes gate dielectric layer, the second grid being formed on gate dielectric layer, and is formed
Offset by gap wall on the both sides side wall of second grid and gate dielectric layer.
Further, nonvolatile memory is flush memory device, and first grid is floating boom, second grid grid in order to control.
Present invention also provides a kind of nonvolatile memories, and the nonvolatile memory is by the above-mentioned making side of the application
Method is made.
Include substrate by being formed using the technical solution of the application, the oxide skin(coating) that is sequentially formed on substrate and the
One gate material layers, and the basal body structure of at least a pair of of second grid structure that is formed in first grid material layer, then
Side wall medium layer is formed on the both sides side wall of each second grid structure, and forms sacrificial dielectric in first grid material layer
Layer and etches sacrificial dielectric layer and first grid material layer are to oxide skin(coating) is exposed, in the inside of second grid structure
The oxide skin(coating) with same thickness is formed with outside；Next, in removal positioned at the side in the outside of each pair of second grid structure
After wall dielectric layer and first grid material layer, since the oxide skin(coating) of the inner side and outer side of second grid structure is having the same
Thickness, therefore the oxide skin(coating) for the inner side and outer side for completely removing second grid structure can be realized by controlling etch step,
And the substrate of the inner side and outer side of second grid structure will not be caused to damage, to realize in balance second grid structure
The purpose of the etching degree of side and outside.
Description of the drawings
The accompanying drawings which form a part of this application are used for providing further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 shows in the production method of existing nonvolatile memory that formation includes substrate, is sequentially formed on substrate
Oxide skin(coating) and first grid material layer, and at least a pair of of second grid structure for being formed in first grid material layer
The cross-sectional view of matrix after basal body structure；
Fig. 2 shows formation side wall medium layers on the both sides side wall of each second grid structure shown in Fig. 1, and first
The cross-sectional view of the matrix after sacrificial dielectric layer is formed in gate material layers；
Fig. 3 shows the side wall medium layer and oxygen to form covering shown in Fig. 2 positioned at the inside of each pair of second grid structure
The cross-sectional view of matrix after the photoresist layer of compound layer；
Fig. 4 is shown except the side wall medium layer and first grid positioned at the outside of each pair of second grid structure shown in Fig. 3
Material layer, and remove the cross-sectional view of the matrix after photoresist layer；
Fig. 5 shows first grid material layer and oxygen of the etching positioned at the outside of each pair of second grid structure shown in Fig. 4
Compound layer, and etch sacrificial dielectric layer, first grid material layer and oxide skin(coating) positioned at the inside of each pair of second grid structure
To exposing substrate, and using remaining first grid material layer as first grid, using remaining oxide skin(coating) as the first grid oxygen
The cross-sectional view of matrix after compound layer；
Fig. 6 shows the flow diagram of the production method for the nonvolatile memory that the application embodiment is provided；
Fig. 7 shows that in the production method for the nonvolatile memory that the application embodiment is provided, formation includes
Substrate, the oxide skin(coating) being sequentially formed on substrate and first grid material layer, and be formed in first grid material layer
The cross-sectional view of matrix after the basal body structure of at least a pair of of second grid structure；
Fig. 8, which is shown, forms side wall medium layer on the both sides side wall of each second grid structure shown in Fig. 7, and first
The cross-sectional view of the matrix after sacrificial dielectric layer is formed in gate material layers；
Fig. 9 shows the base after etching sacrificial dielectric layer and first grid material layer shown in Fig. 8 to exposing oxide skin(coating)
The cross-sectional view of body；
Figure 10 shows the side wall medium layer and oxygen to form covering positioned at the inside of each pair of second grid structure shown in Fig. 9
The cross-sectional view of matrix after the photoresist layer of compound layer；
Figure 11 shows matrix of the removal after the first grid material layer of each pair of second grid structure shown in Fig. 10
Cross-sectional view；
Figure 12 shows that removal is located at the side wall medium layer in the outside of each pair of second grid structure shown in Figure 11, and removes
The cross-sectional view of matrix after photoresist layer；And
Figure 13 shows that oxide skin(coating) is to exposing substrate shown in etching Figure 12, and using remaining oxide skin(coating) as first
The cross-sectional view of matrix after gate oxide layers.
Specific implementation mode
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
It should be noted that term used herein above is merely to describe specific implementation mode, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Be also intended to include plural form, additionally, it should be understood that, when in the present specification using belong to "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or combination thereof.
For ease of description, herein can with use space relative terms, as " ... on ", " in ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, if the device in attached drawing is squeezed, it is described as " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also other different modes positioning (be rotated by 90 ° or be in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As described in background technology, first grid and the are formed by etching technics in existing production method
In the step of one gate oxide layers, due to being formed with first grid material layer and oxide on the outside of each pair of second grid structure
Layer, and sacrificial dielectric layer, first grid material layer and oxide skin(coating) are formed on the inside of each pair of second grid structure, therefore be difficult
The etching degree of the inner side and outer side of second grid structure is balanced by controlling etch step.
Present inventor studies regarding to the issue above, it is proposed that a kind of making side of nonvolatile memory
Method.As shown in fig. 6, the production method includes the following steps：Basal body structure is formed, basal body structure includes substrate, is sequentially formed in
Oxide skin(coating) on substrate and first grid material layer, and at least a pair of of second grid for being formed in first grid material layer
Structure；Side wall medium layer is formed on the both sides side wall of each second grid structure, and is formed and sacrificed in first grid material layer
Dielectric layer；Etches sacrificial dielectric layer and first grid material layer are to exposing oxide skin(coating)；Removal is located at each pair of second grid structure
Outside side wall medium layer and first grid material layer, and using remaining first grid material layer as first grid；Etching
Oxide skin(coating) is to exposing substrate, and using remaining oxide skin(coating) as the first gate oxide layers.
Above-mentioned production method includes substrate by being formed, the oxide skin(coating) and first grid material being sequentially formed on substrate
Layer, and the basal body structure of at least a pair of of second grid structure that is formed in first grid material layer, then in each second gate
Side wall medium layer is formed on the both sides side wall of pole structure, and forms sacrificial dielectric layer in first grid material layer, and etching
Sacrificial dielectric layer and first grid material layer are to oxide skin(coating) is exposed, to form tool in the inner side and outer side of second grid structure
There is the oxide skin(coating) of same thickness；Next, in removal positioned at the side wall medium layer in the outside of each pair of second grid structure and the
It, can due to the oxide skin(coating) of the inner side and outer side of second grid structure thickness having the same after one gate material layers
To realize the oxide skin(coating) for the inner side and outer side for completely removing second grid structure by controlling etch step, and will not be to second
The substrate of the inner side and outer side of gate structure causes to damage, to realize the quarter for the inner side and outer side for balancing second grid structure
The purpose of degree of corrosion.
The exemplary embodiment party of the production method of nonvolatile memory provided by the present application is described in more detail below
Formula.However, these illustrative embodiments can be implemented by many different forms, and should not be construed to be limited solely to
Embodiments set forth herein.It should be understood that thesing embodiments are provided so that disclosure herein is thorough
And it is complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, it is
For the sake of clear, the thickness of layer and region is expanded, and makes that identical device is presented with like reference characters, thus will be saved
Slightly description of them.
Fig. 7 to Figure 13 is shown in the production method of nonvolatile memory provided by the present application, after each step
The cross-sectional view of obtained matrix.Below in conjunction with Fig. 7 to Figure 13, further illustrate provided herein non-volatile
The production method of property memory.
First, basal body structure is formed, basal body structure includes substrate 10,21 He of oxide skin(coating) being sequentially formed on substrate 10
First grid material layer 31, and at least a pair of of second grid structure 40 for being formed in first grid material layer 31, structure
As shown in Figure 7.Wherein, substrate 10 can be with monocrystalline silicon or silicon-on-insulator etc.；Oxide skin(coating) 21 can be SiO2 etc.；First grid
Material layer 31 can be polysilicon layer；Second grid structure 40 may include gate dielectric layer 41, be formed on gate dielectric layer 41
Second grid 42, and the offset by gap wall 43 that is formed on the both sides side wall of second grid 42 and gate dielectric layer 41, and grid are situated between
Matter layer 41 can be ONO layer, and the material of second grid 42 can be polysilicon, and the material of offset by gap wall 43 can be SiN etc..
The thickness of first grid material layer 31 can be in above-mentioned basal body structureThe thickness of offset by gap wall 43
OrThe method for forming basal body structure is referred to the prior art, and details are not described herein.Meanwhile the application institute
The nonvolatile memory of formation can be flush memory device, and first grid 33 is floating boom, the grid in order to control of second grid 42 at this time.
Completion forms basal body structure, and basal body structure includes substrate 10,21 He of oxide skin(coating) being sequentially formed on substrate 10
First grid material layer 31, and be formed in first grid material layer 31 at least a pair of of second grid structure 40 the step of it
Afterwards, side wall medium layer 51 is formed on the both sides side wall of each second grid structure 40, and is formed in first grid material layer 31
Sacrificial dielectric layer 53, and then form basal body structure as shown in Figure 8.In a preferred embodiment, side wall medium is formed
Layer 51 and the step of sacrificial dielectric layer 53 include：Form the medium material of covering second grid structure 40 and first grid material layer 31
The bed of material；Etch media material layer will be located at the layer of dielectric material on the side wall of second grid structure 40 as side wall medium layer
51, and using positioned at the layer of dielectric material of first grid material layer 31 as sacrificial dielectric layer 53.
In above-mentioned preferred embodiment, layer of dielectric material can be SiN layer etc., and forming the technique of layer of dielectric material can be
Chemical vapor deposition etc., specific process parameter is referred to the prior art.The technique of etch media material layer can be dry method
Etching, more preferably plasma etching, specific process parameter are referred to the prior art.In etched layer of dielectric material
After step, the layer of dielectric material on the upper surface of second grid structure 40 is removed, and is located at second grid structure
Certain media material layer on 40 side wall and in first grid material layer 31 is also removed.At this point it is possible to will be located at
Layer of dielectric material on the side wall of second grid structure 40, and will be positioned at first grid material layer 31 as side wall medium layer 51
Layer of dielectric material is as sacrificial dielectric layer 53.
It completes to form side wall medium layer 51 on the both sides side wall of each second grid structure 40, and in first grid material layer
After the step of forming sacrificial dielectric layer 53 on 31, etches sacrificial dielectric layer 53 and first grid material layer 31 are to exposing oxide
Layer 21, and then form basal body structure as shown in Figure 9.After the step, in the inner side and outer side of second grid structure 40
The oxide skin(coating) 21 with same thickness is formed, consequently facilitating completely removing second grid subsequently through control etch step realization
The oxide skin(coating) 21 of the inner side and outer side of structure 40, to realize the etching journey for the inner side and outer side for balancing second grid structure 40
The purpose of degree.
Specifically, the technique of etches sacrificial dielectric layer 53 and first grid material layer 31 can be dry etching, such as etc.
Plasma etching, etching gas can be HBr etc..In a preferred embodiment, etch media in a previous step
After material layer, using etching technics etches sacrificial dielectric layer 53 in situ and first grid material layer 31 to exposing oxide skin(coating)
21.So-called etching in situ refer to the etch media material layer the step of after, continue to be situated between to sacrificing using the same etching apparatus
Matter layer 53 and first grid material layer 31 perform etching, and so as to avoid the vacuum atmosphere in etching apparatus is broken, and then reduce
Due to the defect of breaking generation of vacuum atmosphere.Meanwhile the inside of second grid structure 40 is enabled to using etching in situ
It is easier to control with the etching degree in outside.
Etches sacrificial dielectric layer 53 and first grid material layer 31 are completed to after the step of exposing oxide skin(coating) 21, removal
Side wall medium layer 51 and first grid material layer 31 positioned at the outside of each pair of second grid structure 40, and by the remaining first grid
Pole material layer 31 is used as first grid 33.In a preferred embodiment, removal side wall medium layer 51 and first grid material
The step of bed of material 31 includes：First, side wall medium layer 51 and oxygen of the covering positioned at the inside of each pair of second grid structure 40 are formed
The photoresist layer 60 of compound layer 21, and then form basal body structure as shown in Figure 10；Then, removal is located at each pair of second grid knot
The first grid material layer 31 in the outside of structure 40, and then form basal body structure as shown in figure 11；Finally, removal is located at each pair of the
The side wall medium layer 51 in the outside of two gate structures 40, and photoresist layer 60 is removed, and then form matrix knot as shown in figure 12
Structure.
In the step of removing side wall medium layer 51 and first grid material layer 31, can first it remove positioned at each pair of second gate
The first grid material layer 31 in the outside of pole structure 40, then removal are located at side wall Jie in the outside of each pair of second grid structure 40
Matter layer 51；The side wall medium layer 51 positioned at the outside of each pair of second grid structure 40 can also be first removed, then, removal is located at every
To the first grid material layer 31 in the outside of second grid structure 40.Wherein, the technique of removal first grid material layer 31 is wet
Method etches or dry etching, and the technique of removal side wall medium layer 51 is wet etching.For example, when first grid material layer 31 is more
When crystal silicon layer, sodium hydroxide solution or tetramethyl ammonium hydroxide solution etching first grid material layer 31 may be used.
Side wall medium layer 51 and first grid material layer 31 of the removal positioned at the outside of each pair of second grid structure 40 are completed,
And after the step of regarding remaining first grid material layer 31 as first grid 33, etching oxidation nitride layer 21 to exposing substrate
10, and it regard remaining oxide skin(coating) 21 as the first gate oxide layers 23, and then form basal body structure as shown in fig. 13 that.Etching
The technique of oxide skin(coating) 21 can be wet etching, and etching solution used by wet etching can be HF solution etc..It is specific
Etching technics be referred to the prior art, details are not described herein.
Meanwhile present invention also provides a kind of nonvolatile memory, the nonvolatile memory is above-mentioned by the application
Production method is made.And the performance for the nonvolatile memory being made by the above-mentioned production method of the application is carried
It is high.
It can be seen from the above description that the application the above embodiments realize following technique effect：The application is logical
It includes substrate to cross formation, the oxide skin(coating) and first grid material layer being sequentially formed on substrate, and is formed in first grid
The basal body structure of at least a pair of of second grid structure in material layer, then forms on the both sides side wall of each second grid structure
Side wall medium layer, and sacrificial dielectric layer and etches sacrificial dielectric layer and first grid material are formed in first grid material layer
The bed of material is to oxide skin(coating) is exposed, to form the oxide skin(coating) with same thickness in the inner side and outer side of second grid structure；
Next, removing after the side wall medium layer in the outside of each pair of second grid structure and first grid material layer, due to
The oxide skin(coating) thickness having the same of the inner side and outer side of second grid structure, therefore can be realized by controlling etch step
The oxide skin(coating) of the inner side and outer side of second grid structure is completely removed, and will not be to the inner side and outer side of second grid structure
Substrate causes to damage, to realize balance second grid structure inner side and outer side etching degree purpose.
The foregoing is merely the preferred embodiments of the application, are not intended to limit this application, for the skill of this field
For art personnel, the application can have various modifications and variations.Within the spirit and principles of this application, any made by repair
Change, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (10)
1. a kind of production method of nonvolatile memory, which is characterized in that the production method includes the following steps：
Basal body structure is formed, described matrix structure includes substrate, the oxide skin(coating) and the first grid being sequentially formed on the substrate
Pole material layer, and at least a pair of of second grid structure for being formed in the first grid material layer；
Side wall medium layer, and the shape in the first grid material layer are formed on the both sides side wall of each second grid structure
At sacrificial dielectric layer；
The sacrificial dielectric layer and the first grid material layer are etched to exposing the oxide skin(coating)；
The side wall medium layer and the first grid material layer of the removal positioned at the outside of each pair of second grid structure, and
Using the remaining first grid material layer as first grid；
The oxide skin(coating) is etched to exposing the substrate, and using the remaining oxide skin(coating) as the first gate oxide layers.
2. manufacturing method according to claim 1, which is characterized in that form the side wall medium layer and the sacrificial dielectric
Layer the step of include：
Form the layer of dielectric material for covering the second grid structure and the first grid material layer；
The layer of dielectric material is etched, the layer of dielectric material on the side wall of the second grid structure will be located at as institute
Side wall medium layer is stated, and using the layer of dielectric material in the first grid material layer as sacrificial dielectric layer.
3. production method according to claim 2, which is characterized in that etch the technique of the layer of dielectric material and carved for dry method
Erosion.
4. production method according to claim 3, which is characterized in that after etching the layer of dielectric material, using original position
Etching technics etches the sacrificial dielectric layer and the first grid material layer to exposing the oxide skin(coating).
5. manufacturing method according to claim 1, which is characterized in that remove the side wall medium layer and the first grid
The step of material layer includes：
Form light of the covering positioned at the side wall medium layer and the oxide skin(coating) of the inside of each pair of second grid structure
Photoresist layer；
The side wall medium layer and the first grid material layer of the removal positioned at the outside of each pair of second grid structure；
Remove the photoresist layer.
6. production method according to claim 5, which is characterized in that remove the side wall medium layer and the first grid
In the step of material layer, first removal is located at the first grid material layer in the outside of each pair of second grid structure, then
The side wall medium layer of the removal positioned at the outside of each pair of second grid structure.
7. production method according to claim 6, which is characterized in that the technique for removing the first grid material layer is wet
Method etches or dry etching.
8. production method according to claim 6, which is characterized in that remove the technique of the side wall medium layer and carved for wet method
Erosion.
9. production method according to any one of claim 1 to 8, which is characterized in that the second grid structure includes
Gate dielectric layer, the second grid being formed on gate dielectric layer, and it is formed in the two of the second grid and the gate dielectric layer
Offset by gap wall on the side wall of side.
10. manufacturing method according to claim 9, which is characterized in that the nonvolatile memory is flush memory device, institute
It is floating boom, second grid grid in order to control to state first grid.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944511A (en) * | 2009-07-09 | 2011-01-12 | 中芯国际集成电路制造(上海)有限公司 | Method for making storage unit |
| CN102104044A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8445953B2 (en) * | 2009-07-08 | 2013-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for flash memory cells |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944511A (en) * | 2009-07-09 | 2011-01-12 | 中芯国际集成电路制造(上海)有限公司 | Method for making storage unit |
| CN102104044A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory and manufacturing method thereof |
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