CN107230678A - The manufacture method of flash memory - Google Patents
The manufacture method of flash memory Download PDFInfo
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- CN107230678A CN107230678A CN201710677510.6A CN201710677510A CN107230678A CN 107230678 A CN107230678 A CN 107230678A CN 201710677510 A CN201710677510 A CN 201710677510A CN 107230678 A CN107230678 A CN 107230678A
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000007667 floating Methods 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 13
- 239000007788 liquid Substances 0.000 claims description 12
- 239000002253 acid Substances 0.000 claims description 10
- 238000005260 corrosion Methods 0.000 claims description 9
- 230000007797 corrosion Effects 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 238000010790 dilution Methods 0.000 claims description 4
- 239000012895 dilution Substances 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- 230000005641 tunneling Effects 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000006210 lotion Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a kind of manufacture method of flash memory, it is included on substrate and sequentially forms floating gate oxide layers, floating gate layer, control grid layer and dielectric layer, the dielectric layer is etched to expose control grid layer, again the first side wall is formed on the opening sidewalls that etching is produced, mask is used as using the first side wall, the control grid layer of etching opening bottom, the thickness of first side wall is thinned, first side wall is set to retreat the control grid layer tip exposed due to produced by etching, oxidation processes are carried out to control grid layer tip, its passivation is set to become mellow and full, avoid when wiping data, high electric field is formed between wordline grid and control gate, control gate point discharge and the problem of breakdown device, improve the reliability and stability of device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of manufacture method of flash memory.
Background technology
Flash memory (Flash) is a kind of nonvolatile memory, that is, powering off data will not also lose, its have integrated level it is high,
Access speed is fast, good reliability, easily erasing and the advantages of rewrite, thus is set in mobile communication such as mobile phone, notebook, PCs
It is widely used in standby.
The manufacture method of existing flash memory, be typically sequentially form on a semiconductor substrate floating gate oxide layers and floating gate layer,
Separation layer, control grid layer and dielectric layer, then local medium layer is removed using dry etching, an opening is formed to expose control gate
Layer, in order to ensure after the etch without residual polycrystalline silicon, it usually needs keep enough etch periods, is formed to control grid layer
Overetch, this will cause control grid layer to have the profile of bending, the control grid layer tip formed between wordline grid and control gate.
When wiping data, it usually needs the higher positive voltage on wordline grid, apply relatively low negative voltage on the control gate, finally exist
High electric field is formed between wordline grid and control gate, the potential risk with breakdown device.
The content of the invention
It is an object of the invention to provide a kind of manufacture method of flash memory, to solve in the prior art due to control grid layer
Carry out over etching and produce control grid layer tip, when wiping data, high electric field is formed between wordline grid and control gate, is easily hit
The problem of wearing device.
In order to achieve the above object, the invention provides a kind of manufacture method of flash memory, including：
There is provided and be sequentially formed with floating gate oxide layers, floating gate layer, control grid layer and dielectric layer on substrate, the substrate；
One opening of the dielectric layer formation is etched, to expose the control grid layer；
The first side wall is formed on the side wall of the opening；
The control grid layer in the opening is etched, control grid layer tip, shape can be formed due to over etching in this step
Into control grid layer tip；
First side wall is laterally thinned to expose the control grid layer tip；
Oxidation processes are carried out to control grid layer tip；
Optionally, the step that first side wall is laterally thinned to expose the control grid layer tip includes：
First side wall is thinned using the method for acid liquid corrosion；
Cleaned using the first standard cleaning liquid；
Optionally, the hydrofluoric acid containing dilution in the acid solution；
Optionally, the first standard cleaning liquid includes hydrogen peroxide, ammoniacal liquor and deionized water；
Optionally, the time of acid liquid corrosion is used for 100s-5min；
Optionally, it is 700 degree of -1000 degree the temperature of oxidation processes to be carried out to control grid layer tip；
Optionally, it is 5s-120s to the time that control grid layer tip carries out oxidation processes；
Optionally, the first side wall step is formed on the side wall of the opening includes：
One silica layer is formed on the dielectric layer and on the inwall of the opening；
Etch to remove the silicon oxide layer on the dielectric layer with the opening bottom wall, to form first side wall；
Optionally, the thickness of the silicon oxide layer is 1000 angstroms -1500 angstroms；
Optionally, control grid layer tip is carried out after oxidation processes, the manufacture method of the floating boom also includes：
The second side wall is formed on the side wall of control grid layer in the opening；
Using the second side wall floating gate layer described in mask etching；
Form tunneling oxide layer and word line polysilicon layer；
Optionally, a separation layer is formed between the floating gate layer and the control grid layer；
Optionally, the material of the dielectric layer includes the one or more in silica, silicon nitride and silicon oxynitride；
Optionally, the dielectric layer is etched using dry etch process.
In a kind of manufacture method for flash memory that the present invention is provided, it is included on substrate and sequentially forms floating gate oxide layers, floats
Gate layer, control grid layer and dielectric layer, etch the dielectric layer to expose control grid layer, then the opening sidewalls produced in etching
It is upper formation the first side wall, using the first side wall as mask, the control grid layer of etching opening bottom wall, in order to prevent control gate etching with
There is control gate residual afterwards, be usually that control gate is carried out to cause control grid layer point after overetch, control grid layer overetch
The generation at end, is laterally thinned the thickness of first side wall, retreats first side wall and exposes control grid layer tip, to described
Control grid layer tip carries out oxidation processes, its passivation is become mellow and full, it is to avoid in erasing data, wordline grid and control gate it
Between form high electric field, control grid layer point discharge and the problem of breakdown device.
Brief description of the drawings
The flow chart of the manufacture method for the flash memory that Fig. 1 provides for embodiment；
Fig. 2-Fig. 7 is the diagrammatic cross-section of the semiconductor structure of the manufacture method formation using the flash memory；
Wherein, 1- substrates, 2- floating gate oxide layers, 3- floating gate layers, 4- control grid layers, 41- control grid layers tip, 5- media
Layer, 6- openings, the side walls of 61- first, the side walls of 62- second, 7- separation layers.
Embodiment
The embodiment of the present invention is described in more detail below in conjunction with schematic diagram.According to description below and
Claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing uses very simplified form and equal
Using non-accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Refering to Fig. 1, the flow chart of the manufacture method of its flash memory provided for embodiment.As shown in figure 1, the system of the flash memory
The method of making includes：
S1：There is provided and be sequentially formed with floating gate oxide layers, floating gate layer, control grid layer and dielectric layer on substrate, the substrate；
S2：Etch the dielectric layer to expose control grid layer, form one and be open；
S3：The first side wall is formed on the side wall of the opening；
S4：The control grid layer in the opening is etched, control grid layer tip is formed；
S5：First side wall is laterally thinned to expose the control grid layer tip；
S6：Oxidation processes are carried out to control grid layer tip.
Wherein, when etching the control grid layer in the opening, generally to need to carry out over etching to control grid layer, cause control
Gate layer processed has the profile of bending, forms control grid layer tip, and the first side wall on the opening sidewalls is laterally thinned with exposure
Go out control grid layer tip, then control grid layer tip is subjected to oxidation processes, its passivation is become mellow and full, it is to avoid wiping data
When, high electric field, control grid layer point discharge are formed between wordline grid and control gate and the problem of breakdown device.
Specifically, refer to Fig. 2 to Fig. 7, it is cuing open for the semiconductor structure of the manufacture method formation using the flash memory
Face schematic diagram.Next, will be further described with reference to Fig. 2 to Fig. 7 to the manufacture method of the flash memory.
First, Fig. 2 is refer to there is provided substrate 1, and floating gate oxide layers 2, floating gate layer 3, control are sequentially formed with the substrate 1
Gate layer 4 processed and dielectric layer 5.The material of the substrate 1 is preferably on silicon or germanium, SiGe, GaAs or insulator
Silicon etc..Substrate in the present embodiment is silicon substrate, and forms active area using ion implantation technology.Sequentially form described
Floating gate oxide layers 2, floating gate layer 3, control grid layer 4 and dielectric layer 5, the material of the floating gate oxide layers 2 is preferably silica, is used
Isolate in by the substrate 1 and the floating gate layer 3, the floating gate layer 3 and the control grid layer 4 are used to be formed in subsequent technique
Floating boom and control gate.The material of the floating gate layer 3 and the control grid layer 4 can be polysilicon；The material of the dielectric layer 5 can
Think the one or more combination in silica, silicon nitride, silicon oxynitride, low-K dielectric, super low-K dielectric.
Need herein illustratively, in embodiments herein, between the floating gate layer 3 and the control grid layer 4 also
Including separation layer.Specifically, referring to Fig. 3, being used between the floating gate layer 3 and the control grid layer 4 including a separation layer 7
Isolate floating boom and control gate, the separation layer 7 can be the composite construction layer of oxidenitride oxide (ONO).
Please continue to refer to Fig. 2, use dry etching to etch the dielectric layer 5 (can etch one to expose control grid layer 4
Part control grid layer 4), form an opening 6.
Then, the first side wall 61 is formed on the side wall of the opening 6, it is preferred that using the method for low pressure gas phase deposition
Certain thickness silicon oxide layer is deposited on the inwall and the dielectric layer 5 of the opening 6, it is preferred that can be carried out after deposition fast
Fast annealing, to strengthen the step coverage and compactness of side wall, finally etches the oxidation on 6 bottom walls of the opening and dielectric layer 5
Silicon layer, forms the first side wall 61.Preferably, the thickness of the silicon oxide layer is between 1000 angstroms -1500 angstroms, such as described oxidation
The thickness of silicon layer is 1300 angstroms, 1350 angstroms and 1400 angstroms, and the thickness of silicon oxide layer described in the present embodiment is 1400 angstroms.
, can be using the control grid layer in the method etching opening 6 of anisotropic etching please continue to refer to Figure 4 and 5
4, because the over etching to control grid layer 4 (is usually to control gate to prevent there be control gate residual after control gate etching
Overetch is carried out), control grid layer 4 can cause the generation at control grid layer tip 41 after etching.
With continued reference to Fig. 5, first side wall 61 is thinned to expose control grid layer tip 41.It is preferred that, using humidifying
The method for learning corrosion corrodes the first side wall 61, reduces its thickness.It is preferred that, using the hydrofluoric acid (HF) of dilution to described first
Side wall 61 carries out acid liquid corrosion, and the time of corrosion is 100s-5min, e.g. 100s, 2min, 3min, 4min and 5min, preferably
, with the hydrofluoric acid (water of dilution in the present embodiment：Hydrofluoric acid=100:1) to first side wall 61 carry out acid liquid corrosion when
Between be 2min.Certainly, it should be appreciated by those skilled in the art that the acid solution has high selection to first side wall 61
Than the effect corroded first side wall 61 and do not impacted to other layers can be reached, not only hydrofluoric acid.
In order to reduce after the influence of impurity, the first side wall 61 described in acid liquid corrosion, it is preferred that the first standard can be used clear
Washing lotion is cleaned, and the first standard cleaning liquid is the combination of hydrogen peroxide, ammoniacal liquor and deionized water, wherein, ammoniacal liquor：Dioxygen
Water：Deionized water volume ratio is 1:2:40.
By being thinned after first side wall 61, the control grid layer tip 41 is exposed, then to the control grid layer
Tip 41 carries out oxidation processes, is passivated it, shape becomes mellow and full, specific as shown in Figure 6.It is preferred that, device is put into quickly
Aoxidized in Equipment for Heating Processing, the time for aoxidizing the control grid layer tip 41 is 5s-120s, e.g. 20s, 50s, 70s
And 100s, the time that the control grid layer tip 41 is aoxidized in the present embodiment is 100s；Aoxidize the control grid layer tip 41
Temperature is 700 degree of -1000 degree, and e.g. 800 degree, 850 degree, 900 degree and 1000 degree aoxidize the control grid layer in the present embodiment
The temperature at tip 41 is 850 degree.Control grid layer tip 41 after oxidation becomes mellow and full, it is to avoid when wiping data, wordline grid
High electric field, control gate point discharge are formed between control gate and the problem of breakdown device.
Further, referring to Fig. 7, it is described opening 6 in control grid layer side wall on form the second side wall 62, it is described
The material of second side wall 62 is identical with first side wall 61 with forming method, and simply thickness is different.Fetch down, with described second
Side wall 62 is floating gate layer 3 described in mask etching, re-forms tunneling oxide layer and word line polysilicon layer.
To sum up, in the manufacture method of flash memory provided in an embodiment of the present invention, it is included on substrate and sequentially forms floating boom oxygen
Change layer, floating gate layer, control grid layer and dielectric layer, etch the dielectric layer to expose control grid layer, then in etching generation
The first side wall is formed on opening sidewalls, using the first side wall as mask, the control grid layer of etching opening bottom wall is laterally thinned described
The thickness of first side wall, retreats first side wall and exposes control grid layer tip, control grid layer tip is aoxidized
Processing, makes its passivation become mellow and full, it is to avoid in erasing data, high electric field, floating gate layer are formed between wordline grid and control gate
Point discharge and the problem of breakdown device.
The preferred embodiments of the present invention are above are only, any restriction effect is not played to the present invention.Belonging to any
Those skilled in the art, in the range of technical scheme is not departed from, to the invention discloses technical scheme and
Technology contents make the variation such as any type of equivalent substitution or modification, belong to the content without departing from technical scheme, still
Belong within protection scope of the present invention.
Claims (13)
1. a kind of manufacture method of flash memory, it is characterised in that the manufacture method of the flash memory includes：
There is provided and be sequentially formed with floating gate oxide layers, floating gate layer, control grid layer and dielectric layer on substrate, the substrate；
One opening of the dielectric layer formation is etched, to expose the control grid layer；
The first side wall is formed on the side wall of the opening；
The control grid layer in the opening is etched, control grid layer tip is formed；
First side wall is laterally thinned to expose the control grid layer tip；
Oxidation processes are carried out to control grid layer tip.
2. the manufacture method of flash memory as claimed in claim 1, it is characterised in that first side wall is laterally thinned to expose
The step at the control grid layer tip includes：
First side wall is thinned using the method for acid liquid corrosion；
Cleaned using the first standard cleaning liquid.
3. the manufacture method of flash memory as claimed in claim 2, it is characterised in that the hydrofluoric acid containing dilution in the acid solution.
4. the manufacture method of flash memory as claimed in claim 2, it is characterised in that the first standard cleaning liquid includes dioxygen
Water, ammoniacal liquor and deionized water.
5. the manufacture method of flash memory as claimed in claim 2, it is characterised in that use the time of acid liquid corrosion for 100s-
5min。
6. the manufacture method of flash memory as claimed in claim 1, it is characterised in that carried out to control grid layer tip at oxidation
The temperature of reason is 700 degree of -1000 degree.
7. the manufacture method of flash memory as claimed in claim 6, it is characterised in that carried out to control grid layer tip at oxidation
The time of reason is 5s-120s.
8. the manufacture method of flash memory as claimed in claim 1, it is characterised in that form the first side on the side wall of the opening
Wall step includes：
One silica layer is formed on the dielectric layer and on the inwall of the opening；
Etch to remove on the dielectric layer and the silicon oxide layer of the opening bottom wall is to form first side wall.
9. the manufacture method of flash memory as claimed in claim 8, it is characterised in that the thickness of the silicon oxide layer is 1000 angstroms-
1500 angstroms.
10. the manufacture method of flash memory as claimed in claim 1, it is characterised in that aoxidized to control grid layer tip
After processing, the manufacture method of the flash memory also includes：
The second side wall is formed on the side wall of control grid layer in the opening；
Using the second side wall floating gate layer described in mask etching；
Form tunneling oxide layer and word line polysilicon layer.
11. the manufacture method of flash memory as claimed in claim 1, it is characterised in that the floating gate layer and the control grid layer it
Between be formed with a separation layer.
12. the manufacture method of flash memory as claimed in claim 1, it is characterised in that the material of the dielectric layer include silica,
One or more in silicon nitride and silicon oxynitride.
13. the manufacture method of flash memory as claimed in claim 1, it is characterised in that given an account of using dry etch process etching
Matter layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710677510.6A CN107230678B (en) | 2017-08-09 | 2017-08-09 | Method for manufacturing flash memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710677510.6A CN107230678B (en) | 2017-08-09 | 2017-08-09 | Method for manufacturing flash memory |
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| CN107230678B CN107230678B (en) | 2020-04-10 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110429035A (en) * | 2019-09-06 | 2019-11-08 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of flash memory and flash memory |
| CN111613618A (en) * | 2020-05-26 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN112164655A (en) * | 2020-09-29 | 2021-01-01 | 上海华虹宏力半导体制造有限公司 | Preparation method of flash memory device |
| CN112908859A (en) * | 2021-03-24 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory |
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| Publication number | Publication date |
|---|---|
| CN107230678B (en) | 2020-04-10 |
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