CN102263064A - Method for forming discrete grid storage device - Google Patents
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- CN102263064A CN102263064A CN201010193811XA CN201010193811A CN102263064A CN 102263064 A CN102263064 A CN 102263064A CN 201010193811X A CN201010193811X A CN 201010193811XA CN 201010193811 A CN201010193811 A CN 201010193811A CN 102263064 A CN102263064 A CN 102263064A
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Abstract
The invention provides a method for forming a discrete grid storage device, comprising the following steps: providing a semiconductor substrate, and forming a grid medium layer, a first polysilicon layer, an interlaminar insulating layer and a second polysilicon layer on the semiconductor substrate in sequence; etching the second polysilicon layer and the interlaminar insulating layer until the first polysilicon layer is exposed, thus forming a control grid; forming side walls on the control grid and the side wall of the etched interlaminar insulating layer; and etching the first polysilicon layer by using an isotropous plasma etching technology by taking the control grid and the side walls as masks, so that the outer side of the etched first polysilicon layer is provided with a top end. Compared with the prior art, the method provided by the invention is simple in process and low in cost; and because the accuracy of the plasma etching technology is easy to control, the method is more suitable for manufacturing devices with small characteristic dimensions.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of formation method of discrete grid memory device.
Background technology
In present semiconductor industry, integrated circuit mainly can be divided into the three major types type: analog integrated circuit, digital integrated circuit and DA combination integrated circuit.
An important kind as digital integrated circuit, memory device, especially flash memory (flash memory, be called for short flash memory) development particularly rapid, main because flash memory have under situation about not powering up can long preservation information and have integrated level height, access speed fast, be easy to wipe and advantage such as rewriting.
The standard physical structure of flash memory is called memory cell (bit).The structure of memory cell is different with conventional MOS transistor.Separate by gate insulator between the grid (gate) of conventional MOS transistor and conducting channel, be generally oxide layer (oxide); And flash memory more than between control gate (CG:control gate is equivalent to the grid of conventional MOS transistor) and conducting channel layer of material, be referred to as floating boom (FG:floating gate).Because the existence of floating boom makes flash memory can finish three kinds of basic manipulation modes: i.e. reading and writing, wipe.Even if under the situation that does not have power supply to supply with, the existence of floating boom can keep storing the integrality of data.
Usually in order to improve the integrated level of memory, can make on semi-conductive substrate a plurality of memory cells floating boom and above control gate, thereby constitute discrete grid memory device.Fig. 1 has provided the structural representation of existing discrete grid memory device, there is shown two memory cell, and each memory cell comprises the memory transistor 110 that is formed on the silicon substrate and adjacent with it erase gate 120 (EG:erasing gate).The shared erase gate 120 of the memory transistor of these two memory cell, described memory transistor comprises floating boom 101, control gate 105,105 of described floating boom 101 and control gates have interlayer insulating film (unmarked); Simultaneously be formed with side wall 125, have tunneling insulation layer 140 between described erase gate 120 and the floating boom 101 at control gate 105 and interlayer insulating film both sides.Be formed with source electrode 135 in the silicon substrate of described erase gate 120 bottoms, and in the opposite side silicon substrate of floating boom 101, be formed with drain electrode (unmarked) with respect to erase gate 120, all isolated between described floating boom 101, erase gate 120 and the silicon substrate by oxide layer.
Because the physical characteristic and the structure of described floating boom 101, it can store charge.Corresponding relation in the floating boom 101 between the binary data (0 or 1) of the state of electric charge and store charge state representative can have different definition.Generally speaking, when floating boom 101 trapped electronss, this bank bit is defined as by " 1 " and becomes " 0 ", and this process also can be described as programming mode for writing; Relative, after electronics discharged from floating boom 101, this bank bit was defined as by " 0 " and becomes " 1 ", and this process is called wipes.When programming, with source electrode 135 ground connection, the voltage of control gate is during greater than drain voltage, oxide layer between floating boom 101 and its bottom silicon substrate (being the conducting channel between source-drain electrode) can narrow down by band, therefore the electronics in conducting channel can be accelerated, can transit to the floating boom from conducting channel, thereby finish programming.During erasure information, use Fowler-Nordheim (writing a Chinese character in simplified form F-N) tunneling effect usually, this moment control gate 105 ground connection, erase gate 120 adds positive voltage, electronics to erase gate 120, is finished wiping electric charge in the floating boom 101 by floating boom 101 tunnellings.Because the F-N effect is very responsive to the electric field in the tunneling insulation layer 140, electric field is big more, and tunnelling current is big more, and is fast more to the erasing speed of electric charge, therefore in order to improve the erasing speed of device, needs to improve the electric field strength in the tunneling insulation layer 140.
Existing a kind of electric field strength method that improves in the tunneling insulation layer, by when forming floating boom, the structure that tapers off to a point at the interface that makes floating boom and tunneling insulation layer is to improve the electric field strength in the tunneling insulation layer.Described formation has the method for discrete grid memory device structures of cutting-edge structure shown in Fig. 2 a to Fig. 2 d.
As Fig. 2 a, adopt the low-pressure chemical vapor phase deposition method to form one deck polysilicon as floating gate polysilicon layer 20 on silicon substrate 10 surfaces; On floating gate polysilicon layer 20, form silicon nitride layer 30 and patterning photoresist layer (not shown).With the photoresist layer is mask, silicon nitride layer 30 is etched to exposes floating gate polysilicon layer 20.
As Fig. 2 b, partial thermal oxidation is carried out on floating gate polysilicon layer 20 surfaces that expose, oxidized floating gate polysilicon layer 20 will be removed, so that form the depression tip in remaining floating gate polysilicon layer 20 sides, therefore most advanced and sophisticated size depends on the scope of partial thermal oxidation;
As Fig. 2 c, the oxidized part in floating gate polysilicon layer 20 surfaces that adopts the wet etching removal to expose;
As Fig. 2 d, behind the removal photoresist layer, be the barrier layer with silicon nitride layer 30, to floating gate polysilicon layer 20 further dry etchings until silicon substrate 10, form floating boom 20a, the side of described floating boom 20a has the tip, follow-uply will further form tunneling insulation layer and erase gate in floating boom 20a side.
The method that above-mentioned formation has most advanced and sophisticated floating boom has adopted the partial thermal oxidation technology of wet etching again, be subjected in the accuracy limitations of partial thermal oxidation and wet-etching technology, only the flash memory than large-feature-size is suitable for, for the flash memory structure of characteristic size below 130nm, craft precision can't reach corresponding requirements.
Therefore,, need a kind of technological process of exploitation simple, with low cost, can form the manufacture method of the discrete grid memory device at floating boom tip for flush memory device than small-feature-size.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of discrete grid memory device, and technological process is simple, and is with low cost, and is applicable to the manufacturing than the small-feature-size device.
For addressing the above problem, the invention provides a kind of formation method of discrete grid memory device, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, forms gate dielectric layer, first polysilicon layer, interlayer insulating film and second polysilicon layer successively; Described second polysilicon layer of etching and interlayer insulating film form control gate until exposing first polysilicon layer; On the interlayer insulating film sidewall after described control gate and the etching, form side wall; With control gate and side wall is mask, adopts isotropic plasma etching industrial etching first polysilicon layer, makes first polysilicon layer outside after the etching have the tip.
Optionally, the etching gas of described isotropism plasma etching industrial comprises Cl
2, O
2And HBr.The technological parameter of described plasma etching industrial comprises: feed HBr/Cl
2Mist, the mixed volume ratio is 8.25～12; Feed the HBr/O2 mist, the mixed volume ratio is 85～140; Keeping the air pressure in the etch chamber is 10mTorr～15mTorr.
Optionally, adopt first polysilicon layer of described isotropic plasma etching industrial etched portions thickness earlier, adopt anisotropic plasma etching industrial to continue the not part of Be Controlled grid covering of etching first polysilicon layer again, until exposing gate dielectric layer.As alternative dispensing means, directly adopt isotropic plasma etching industrial etching first polysilicon layer, until exposing gate dielectric layer.
Optionally, the first polysilicon layer thickness range of the isotropic plasma etching industrial etching removal of described employing is
Optionally, after the control gate surface forms mask, also comprise step: first polysilicon layer that over etching exposes.The etching gas that described over etching adopts comprises CF
4The technological parameter of described over etching comprises: radio-frequency power is more than or equal to 600w, and bias voltage feeds CF smaller or equal to 120V
4Gas flow keeps the interior air pressure of etch chamber smaller or equal to 6mTorr smaller or equal to 50sccm.The thickness range that described over etching is removed first polysilicon layer is
After described etching first polysilicon layer exposes gate dielectric layer, also comprise: define the source region; Ion is carried out in described source region to be injected; Above the outside of side wall, source region, form tunneling insulation layer and erase gate successively.It is phosphorus or arsenic that described source region ion injects type, and implantation dosage is 2 * 10
15/ cm
2To 4 * 10
15/ cm
2The formation method of described tunneling insulation layer is a low-pressure chemical vapor phase deposition technology.The thickness of described tunneling insulation layer is
The present invention adopts to have isotropic plasma etching industrial when forming floating boom, in vertical etching first polysilicon layer, also produces certain lateral etching, makes that first polysilicon layer (also the being floating boom) side after being etched forms the tip of caving in.Compared with prior art, the present invention does not increase extra technology, only need improve etch step based on common process, so flow process is simply with low cost, and because the plasma etching industrial precision is easy to control, is more suitable for the manufacturing of small-feature-size device.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 is the structural representation of the discrete grid memory device of prior art;
Fig. 2 a to Fig. 2 d is a kind of manufacture method schematic diagram of existing discrete grid floating boom;
Fig. 3 is the basic procedure schematic diagram of the formation method of discrete grid memory device of the present invention;
Fig. 4 to Figure 12 is the cross-sectional view of the discrete grid memory device formation method of the embodiment of the invention;
Figure 13 is the partial schematic diagram at the floating boom tip of embodiment of the invention formation.
Embodiment
In theory, discrete grid memory device utilizes tunnel thermionic emission mechanism when programming, and makes program rate very fast, and the reaction time is generally in μ s magnitude; And when erasure information, utilize the F-N tunneling effect, make that to wipe speed slower, in the ms magnitude.According to F-N tunneling effect current formula,
i
FN＝A×S
TUN×E
2 TUN×exp(B/E
TUN)
Wherein, E
TUNBe the electric field strength in the tunneling insulation layer, S
TUNBe the region area that produces electron tunneling between floating boom and the erase gate, A and B are the F-N parameters.Described tunnelling current i
FNWith the field intensity E on the tunneling insulation layer
TUNClosely related, for improving this electric field strength, can reduce the thickness of tunneling insulation layer, but do the loss that causes electric charge on the floating boom easily like this, thereby cause losing of information; And erasing voltage generally is difficult to improve, because improve the increase that erasing voltage can cause device instability and power consumption.
Continuation is with reference to figure 1, floating boom 101 is similar to rectangle with tunneling insulation layer 140 contact areas, concrete as dotted line circle part among Fig. 1, when carrying out erase operation, erase gate 120 applies the voltage of forward in floating boom 101, forms the electric field that is pointed to floating boom 101 by erase gate 120, because the contact-making surface of floating boom 101 and tunneling insulation layer 140 is comparatively flat, to cause the electric field strength on the tunneling insulation layer 140 lower, corresponding tunnelling current is less than normal, and charge erasure speed is slow in the floating boom 101.In practice, for instance, when erasing voltage was 11.5V, the erasing time will be lower than 10ms, added to 13V and in fact work as erasing voltage, and the erasing time still reaches 5s, differs greatly with desired value.For improving the ability of wiping of discrete grid memory device, need taper off to a point in floating boom 101 and tunneling insulation layer 140 contact portions, utilize the point discharge effect to improve this place's field intensity.
In the prior art, the size at floating boom tip depends on the partial thermal oxidation scope to floating gate polysilicon layer, but is subjected in the accuracy limitations of partial thermal oxidation and wet-etching technology, and it is very little that above-mentioned tip size is difficult to do.Therefore for the flash memory of small-feature-size, floating boom thickness own is just thinner, and the method at above-mentioned formation floating boom tip is also inapplicable.On the other hand, adopt the partial thermal oxidation technology of wet etching again, need priority through peroxidating and wet etching machine bench, process cycle is longer, and it is more to relate to technological parameter.Do not have on the most advanced and sophisticated flash memory system fabrication technique basis in routine, need to increase extra processing procedure, therefore greatly improved the complex process degree.
And method provided by the invention is not only applicable to discrete grid memory device, also be applicable to general memory device with floating gate structure, be specially adapted to characteristic size at 130nm and following memory device, as EPROM (Erasable Programmable Read Only Memory EPROM), EEPROM (signal of telecommunication Erasable Programmable Read Only Memory EPROM) etc.Adopt simple and reliable technology at the tip that floating boom caves near the side formation of tunnel oxide, Fig. 3 has provided the basic procedure schematic diagram of the formation method of discrete grid memory device of the present invention, and key step comprises:
Step S101, provide Semiconductor substrate, on described Semiconductor substrate, form gate dielectric layer, first polysilicon layer, interlayer insulating film and second polysilicon layer successively;
Step S102, described second polysilicon layer of etching and interlayer insulating film form control gate, and form side wall on the sidewalls of control gate until first polysilicon layer;
Step S103, isotropic plasma etching industrial etching first polysilicon layer of employing be the part of Be Controlled grid covering not, above-mentioned isotropic plasma etching industrial, not only at vertical etching first polysilicon layer vertically, simultaneously also first polysilicon layer is played certain corrasion, make that the first polysilicon layer side after the etching tapers off to a point in side direction.
At etching first polysilicon layer after exposing gate dielectric layer, just formed floating boom, subsequent step also should comprise in addition: ion injects the step that forms the source region and form tunnel insulation layer and erase gate above the above-mentioned sidewall outside, source region, finally finishes the manufacturing of discrete grid memory device.
Method provided by the invention is applicable to and forms the polysilicon tip, is particularly useful for the formation at the floating boom tip of discrete grid memory device.But method of the present invention should be limited in the formation technology of floating boom of discrete grid memory device, if relate to the problem that forms the polysilicon tip in other technologies, method of the present invention also can be suitable for accordingly.
Below in conjunction with specific embodiment and accompanying drawing thereof, principle of the present invention and advantage are described further.Fig. 4 to Figure 12 is the cross-sectional view of the embodiment of the invention, and a detailed formation method of discrete grid memory device is provided.
At first as shown in Figure 4, provide Semiconductor substrate 300, form gate dielectric layer 310 on the surface of Semiconductor substrate 300.
In the present embodiment, silicon or SiGe that described Semiconductor substrate 300 can be monocrystalline, polycrystalline or non crystalline structure; It also can be silicon-on-insulator (SOI); The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.Have certain isolation structure (not shown) on the described Semiconductor substrate 300, can isolate (LOCOS) etc. from (STI), local field oxidation for shallow trench isolation.
Described Semiconductor substrate 300 can be the P type, can realize by injecting the boron ion; At the tunnelling charge carrier of discrete grid memory device in such cases is electronics.Described Semiconductor substrate 300 can also be the N type, can realize by injecting phosphonium ion; This moment, described tunnelling charge carrier was the hole.The memory device of present embodiment adopts electronics as charge carrier.
In the present embodiment, described gate dielectric layer 310 can be selected silica for use at this for silica, silicon nitride, silicon oxynitride or other high k materials.Its formation method can be the boiler tube thermal oxidation, ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition technologies such as (PECVD), and present embodiment adopts the boiler tube thermal oxidation technology.
As shown in Figure 5, on gate dielectric layer 310, form first polysilicon layer 320, be used to form floating boom.The formation method of first polysilicon 320 can be chemical vapor deposition (CVD), low-pressure chemical vapor phase deposition (LPCVD) technology, and present embodiment adopts low-pressure chemical vapor phase deposition technology.Described first polysilicon layer 320 has first thickness, and its scope is
Be preferably
First polysilicon layer 320 is mixed, and the tunnelling charge carrier is an electronics in the present embodiment, therefore carries out the N type and mixes, and dopant ion can be pentads such as phosphorus, antimony, arsenic.The doping method of described first polysilicon layer 320 is that ion injects, and implantation dosage is 6 * 10
14/ cm
2To 5 * 10
15/ cm
2
As shown in Figure 6, form interlayer insulating film 330, second polysilicon layer 340 and the dielectric layer successively on the surface of first polysilicon layer 320.
In the present embodiment, described interlayer insulating film 330 can be the ONO three-decker, i.e. silica-silicon-nitride and silicon oxide, and as the insulating barrier between first polysilicon layer 320 and second polysilicon layer 340, this structure has the advantage of little, the low defective of electric leakage.The formation method of silica can be ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition technologies such as (PECVD), the vapor deposition of present embodiment using plasma enhanced chemical.The formation method of silicon nitride can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD) technology.Present embodiment adopts low-pressure chemical vapor phase deposition.
Described second polysilicon layer 340 is used as the formation control gate in subsequent technique.The formation method of described second polysilicon layer 340 can be identical with first polysilicon layer 320, and present embodiment adopts low-pressure chemical vapor phase deposition technology.The thickness of described second polysilicon layer 340 is
Be preferably
Because the tunnelling charge carrier is an electronics in the present embodiment, described second polysilicon layer 340 is carried out the N type mix, dopant ion can be pentads such as phosphorus, antimony, arsenic.
In the present embodiment, described dielectric layer comprises the double-decker that oxide layer 350 and silicon nitride layer 360 constitute, and is used for the top surface at follow-up plasma etching industrial protection control gate.The thickness of described oxide layer 350 is 300～
Be preferably
The thickness of described silicon nitride layer 360 is 850～
Be preferably
As shown in Figure 7, etching dielectric layer, second polysilicon layer, interlayer insulating film 330 form control gate 340a until exposing first polysilicon layer 320 successively; On the sidewall of described control gate 340a and interlayer insulating film 330, form side wall 370.The concrete technology that forms control gate 340a is as follows: form photoresist layer on described dielectric layer, the patterning photoresist layer defines the control gate figure afterwards, and this technology is conventionally known to one of skill in the art; Then, be mask with the photoresist, dielectric layer, second polysilicon layer and interlayer insulating film 330 are etched to expose first polysilicon layer 320 successively, described lithographic method can be a dry etching.
Described side wall 370 is used at follow-up isotropic plasma etching industrial; the sidewall of protection control gate can be a kind of or its combination in silicon oxide layer, the silicon nitride layer, in the present embodiment; described side wall 370 is a silicon oxide layer, can form by chemical vapour deposition (CVD) CVD.
According to aforementioned content as can be known, usually after forming control gate, enter next step technology before because first polysilicon layer, 320 surfaces of exposing to the open air, very easily oxidized formation oxide-film.Therefore in order to remove above-mentioned oxide-film,, as shown in Figure 8, first polysilicon layer 320 that exposes to the open air between the adjacent control gate is carried out over etching, lightening holes thickness as possibility.For in vertical direction, first polysilicon layer 320 is obtained bigger selective etching ratio, the etching gas that described over etching adopts can be CF
4Concrete technological parameter can for: radio-frequency power more than or equal to 600w, bias voltage feeds CF smaller or equal to 120V
4Gas flow keeps the interior air pressure of etch chamber smaller or equal to 6mTorr smaller or equal to 50sccm.The thickness range of described over etching attenuate first polysilicon layer 320 can for
In the present embodiment, the thickness of over etching attenuate is preferably
Therefore the thickness at first polysilicon layer 320 is
The time, through behind the over etching, also remaining pact
Thickness.
As shown in Figure 9, be mask with control gate and side wall, first polysilicon layer 320 that exposes to the open air is carried out isotropic plasma etching, form floating boom.
In the present embodiment, described isotropism plasma etching need vertically and laterally carry out etching to described first polysilicon layer 320 simultaneously.In order to reach the purpose of above-mentioned etching, the etching gas of described plasma etching can comprise Cl
2, O
2And HBr.Concrete technological parameter can for: feed HBr/Cl
2Mist, the mixed volume ratio is 8.25～12; Feed the HBr/O2 mist, the mixed volume ratio is 85～140; Keeping the air pressure in the etch chamber is 10mTorr～15mTorr.
As optional embodiment, the isotropic plasma etching industrial of above-mentioned employing, can one step etching first polysilicon layer 320 to exposing gate dielectric layer 310, and form floating boom.But because the thickness of first polysilicon layer 320 is thicker, etching speed is slower on the one hand for such scheme, and the floating boom lateral dimension loss that forms on the other hand too much will be unfavorable for the carrying out of subsequent technique.
As another optional embodiment, can adopt first polysilicon layer 320 of isotropic plasma etching method etched portions thickness earlier, make that first polysilicon layer, 320 sides after the etching taper off to a point; Then, more as shown in figure 10, adopt conventional anisotropic etch process, etching is removed first polysilicon layer 320 of residual thickness to exposing gate dielectric layer 310, forms floating boom 320a.The control gate 340a of described floating boom 320a and top thereof constitutes the grid structure of the memory transistor of discrete grid memory device.Adjacent described grid structure has at interval, be used for follow-up formation erase gate, and Semiconductor substrate 300 parts at described interval can be defined as the source region.
In the embodiment shown in fig. 10, the thickness range of described isotropic plasma etching industrial etching first polysilicon layer is about
Preferably, the thickness of etching attenuate is
So also remaining pact of first polysilicon layer 320 of this part
Thickness, simultaneously form the tip of caving in side direction.It is to be noted, isotropic plasma etching of the present invention only is a relative concept, in fact, vertically the etching speed with side direction still can have certain difference, but with on a certain direction, have etching technics (for example anisotropic etching) isotropism of selective etching ratio greatly usually.
As shown in figure 11, on the zone beyond the source region of definition, form patterned photoresist 380, utilize photoresist 380 ion to be carried out in the source region of definition and inject, inject ion and can be phosphorus or arsenic as mask.In the present embodiment, adopt arsenic ion, implantation dosage is 2 * 10
15/ cm
2To 4 * 10
15/ cm
2Ion injects the back and forms N+ doping source region 385 in this zone; Remove photoresist layer 380 at last.
As shown in figure 12, above the outside of described side wall 370 and source region 385, form tunneling insulation layer 390; Between the grid structure of the memory transistor of discrete grid memory device, form erase gate 400.In the present embodiment, described tunneling insulation layer 390 also adopts silica.Therefore in fact tunneling insulation layer 390 can be considered as one with side wall 370, between described floating boom and the erase gate 400 interval tunneling insulation layer 390 of silica material.
Figure 13 is the partial schematic diagram at the floating boom tip of embodiment of the invention formation, as seen from Figure 13, the formation method of present embodiment, formed the tip of caving in (the dotted line circle illustrates among the figure) at floating boom 340a near tunneling insulation layer 390 1 sides, than traditional rectangle floating boom, present embodiment can strengthen floating boom 320a at tip place and put on electric field strength on the tunneling insulation layer 390, make discrete grid memory device when work, improve electronics and pass through the speed of tunneling insulation layer 390, and then improve the data erase rates of memory to erase gate 400 migrations from floating boom 320a.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (14)
1. the formation method of a discrete grid memory device is characterized in that, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, forms gate dielectric layer, first polysilicon layer, interlayer insulating film and second polysilicon layer successively;
Described second polysilicon layer of etching and interlayer insulating film form control gate until exposing first polysilicon layer;
On the interlayer insulating film sidewall after described control gate and the etching, form side wall;
With control gate and side wall is mask, adopts isotropic plasma etching industrial etching first polysilicon layer, makes first polysilicon layer outside after the etching have the tip.
2. the formation method of discrete grid memory device as claimed in claim 1 is characterized in that the etching gas of described isotropism plasma etching industrial comprises Cl
2, O
2And HBr.
3. the formation method of discrete grid memory device as claimed in claim 2 is characterized in that, the technological parameter of described plasma etching industrial comprises: feed HBr/Cl
2Mist, the mixed volume ratio is 8.25～12; Feed the HBr/O2 mist, the mixed volume ratio is 85～140; Keeping the air pressure in the etch chamber is 10mTorr～15mTorr.
4. the formation method of discrete grid memory device as claimed in claim 1, it is characterized in that, adopt first polysilicon layer of described isotropic plasma etching industrial etched portions thickness earlier, adopt anisotropic plasma etching industrial to continue the not part of Be Controlled grid covering of etching first polysilicon layer again, until exposing gate dielectric layer.
5. the formation method of discrete grid memory device as claimed in claim 1 is characterized in that, isotropic plasma etching industrial etching first polysilicon layer of described employing is until exposing gate dielectric layer.
6. the formation method of discrete grid memory device as claimed in claim 4 is characterized in that, the first polysilicon layer thickness range that the isotropic plasma etching industrial etching of described employing is removed is
7. the formation method of discrete grid memory device as claimed in claim 1 is characterized in that, after the control gate surface forms mask, also comprises step: first polysilicon layer that over etching exposes.
8. the formation method of discrete grid memory device as claimed in claim 7 is characterized in that, the etching gas that described over etching adopts comprises CF
4
9. the formation method of discrete grid memory device as claimed in claim 8 is characterized in that, the technological parameter of described over etching comprises: radio-frequency power is more than or equal to 600w, and bias voltage feeds CF smaller or equal to 120V
4Gas flow keeps the interior air pressure of etch chamber smaller or equal to 6mTorr smaller or equal to 50sccm.
10. the formation method of discrete grid memory device as claimed in claim 9 is characterized in that, the thickness range that described over etching is removed first polysilicon layer is
11. the formation method as claim 4 or 5 described discrete grid memory devices is characterized in that, after etching first polysilicon layer exposes gate dielectric layer, also comprises:
Define the source region;
Ion is carried out in described source region to be injected;
Above the outside of side wall, source region, form tunneling insulation layer and erase gate successively.
12. the formation method of discrete grid memory device as claimed in claim 11 is characterized in that, it is phosphorus or arsenic that described source region ion injects type, and implantation dosage is 2 * 10
15/ cm
2To 4 * 10
15/ cm
2
13. the formation method of discrete grid memory device according to claim 11 is characterized in that, the formation method of described tunneling insulation layer is a low-pressure chemical vapor phase deposition technology.
14. the formation method of discrete grid memory device according to claim 11 is characterized in that the thickness of described tunneling insulation layer is
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| CN106298675A (en) * | 2015-05-26 | 2017-01-04 | 旺宏电子股份有限公司 | Semiconductor element and manufacture method thereof |
| CN107230678A (en) * | 2017-08-09 | 2017-10-03 | 上海华虹宏力半导体制造有限公司 | The manufacture method of flash memory |
| CN108511448A (en) * | 2018-03-23 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor structure |
| CN110429035A (en) * | 2019-09-06 | 2019-11-08 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of flash memory and flash memory |
| CN112713149A (en) * | 2019-10-25 | 2021-04-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method |
| CN113871486A (en) * | 2021-09-27 | 2021-12-31 | 北京大学 | Multi-floating-gate laminated type synaptic transistor and preparation method thereof |
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| CN113871486A (en) * | 2021-09-27 | 2021-12-31 | 北京大学 | Multi-floating-gate laminated type synaptic transistor and preparation method thereof |
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