CN108511448A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN108511448A CN108511448A CN201810247065.4A CN201810247065A CN108511448A CN 108511448 A CN108511448 A CN 108511448A CN 201810247065 A CN201810247065 A CN 201810247065A CN 108511448 A CN108511448 A CN 108511448A
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- layer
- etching
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- semiconductor structure
- forming method
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 107
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 171
- 238000010586 diagram Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000005001 laminate film Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of forming methods of semiconductor structure, the etching of mask layer on first grid layer is divided into and is carried out twice, after first time etching etching, there are residues when the mask layer, when then carrying out second of etching, the etching selection ratio of the mask layer and the first grid layer is increased, so that the loss of first grid layer caused by being etched due to mask layer is become smaller, so that remaining first grid layer thickness increases, when subsequently being etched to the oxide layer of first grid layer surface, since the thickness of first grid thickens, it can prevent from being just etched through first grid when etching the oxide layer of first grid layer surface, so as to avoid the damage of first grid layer bottom ONO layer film.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of forming method of semiconductor structure.
Background technology
In semiconductor processing industry, ONO (oxide layer-nitride layer-oxide layer) is stacked in nonvolatile flash memory (NOR
FLASH) as the interlayer electricity between floating boom (Floating Gate, FG) and control gate (Control Gate, CG) in memory
Medium.ONO films damage caused by the online scanning electron microscope of EF90 finds the etching by control grid layer polysilicon, basic former
Because being that control grid layer etching uses chlorine as gas breakdown, and easily etches complete natural oxide and heavily doped sundries control gate
Polymer.
Due to hardware limitation, it is impossible that breakdown time when control grid layer etches, which is reduced, further, because of ONO
Film damages, and etching shallow trenches isolating oxide layer and will make shallow trench followed by the etching of offset etching and floating gate oxide layers
Separation loss is more, and then the silicon in bottom active area at floating gate layer etching will be damaged.
Invention content
The purpose of the present invention is to provide a kind of forming methods of semiconductor structure, to solve in the prior art because of control gate
The problem of etching of layer polysilicon causes ONO films to damage.
In order to achieve the above object, the present invention provides a kind of forming method of semiconductor structure, include the following steps：
Front-end architecture is provided, the front-end architecture includes the first grid layer and mask layer stacked gradually；
First time etching is carried out to the mask layer；And
The first grid layer is etched to expose out for the second time to the mask layer, second of etching is to described
Mask layer high selectivity is in the selectivity to the first grid layer.
Optionally, when second of etching, the etching selection ratio ranging from 4 of the mask layer and the first grid layer
~6.
Optionally, when the first time etching, the etching selection ratio of the mask layer and the first grid layer is 1~2.
Optionally, the etching mode progress first time etching is stopped using arrival time and etched for described second.
Optionally, the altitude range of the first time etching is 2520~3080 angstroms, using gas CF4Or CHF3Etching.
Optionally, the height of second of etching is more than or equal to 650 angstroms, using gas CH3F etching agents.
Optionally, the mask layer is silicon nitride layer.
Optionally, the front-end architecture further includes substrate, and the oxide layer being located on the substrate is located in the oxide layer
Second grid layer and the dielectric layer on the second grid layer, the first grid layer be located on the dielectric layer.
Optionally, after the completion of etching for described second, the first grid layer surface generates oxide layer, using etching work
Skill removes the oxide layer.
Optionally, grid, the second grid layer are floating boom to the first grid layer in order to control, and the dielectric layer is ONO layer.
Optionally, the control grid layer is polysilicon layer.
Optionally, the thickness range of the mask layer is 3000~3630 angstroms, and the thickness range of the first grid layer is
540~660 angstroms, the thickness range of the ONO layer is 130~160 angstroms.
In conclusion in the forming method of semiconductor structure provided by the invention, front-end architecture, the front end knot are provided
Structure includes the first grid layer and mask layer stacked gradually；First time etching is carried out to the mask layer；And to the mask
Layer is etched to expose out the first grid layer for the second time, and second of etching is to the mask layer high selectivity in right
The selectivity of the first grid layer.The etching of mask layer on first grid layer is divided into the present invention and being carried out twice, first
There are residues after secondary etching etching, when the mask layer, when then carrying out second and etching, to the mask layer and described first
The etching selection ratio of grid layer increases so that and first grid layer loss caused by being etched due to mask layer is become smaller, and remaining first
Gate layer thickness increases.
Further, because the thickness of first grid is too thin, when the oxide layer to first grid layer surface etches, just hold
Easily first grid is etched through.The present invention is exactly by the way that the thickness of first grid is thickened, to prevent in etching first grid
Just first grid is etched through when the oxide layer of layer surface, so as to avoid first grid layer bottom ONO layer film
Damage.
Description of the drawings
Fig. 1 is the device architecture schematic diagram after control gate etching in existing method；
Fig. 2 is device architecture schematic diagram when floating boom etches in existing method；
Fig. 3 is the flow diagram of the forming method of semiconductor structure provided in an embodiment of the present invention；
Fig. 4 is the device architecture schematic diagram of formation before the mask layer etching provided in an embodiment of the present invention；
Fig. 5 is the device architecture schematic diagram formed when mask layer etches in existing method；
Fig. 6 is that mask layer etches the device architecture schematic diagram formed after the completion in existing method；
Fig. 7 is the device architecture schematic diagram after mask layer etches in step sl in method provided in an embodiment of the present invention；
Fig. 8 is the device architecture schematic diagram after mask layer etches in step s3 in method provided in an embodiment of the present invention；
Wherein, 11- active areas, 12- floating booms, 13-ONO layers, 14- control gates, 15- shallow trench isolations, 21- substrates, 22- oxygen
Change layer, 23- floating booms, 24- dielectric layers, 25- first grid layers, 26- mask layers.
Specific implementation mode
The specific implementation mode of the present invention is described in more detail below in conjunction with schematic diagram.According to following description and
Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Refering to fig. 1 and Fig. 2, as described in the background art, ONO layer 13 is formed between floating boom 12 and control gate 14,
When etching control gate 14 due to, as etching gas, easily etching complete natural oxide and again using chlorine in existing scheme
Dopant control gate polymer, so as to cause the damage of 13 film of ONO layer, then can later offset etching and floating boom oxidation
So that the oxide layer of the shallow trench isolation 17 in active area 11 is etched when layer etching and shallow trench isolation 15 made to lose more,
So that 11 subregion of active area is exposed, when floating boom 12 etches, the region that active area 11 exposes can also be etched,
This will cause the silicon of active area 11 to be damaged, the final performance for influencing semiconductor devices.
Therefore, when manufacturing semiconductor devices, to solve the above-mentioned problems, the present invention provides a kind of semiconductor structures
Forming method.
It is the flow diagram of the forming method of semiconductor structure provided in an embodiment of the present invention, such as Fig. 1 refering to Fig. 3
Shown, the forming method of the semiconductor structure includes the following steps:
Step S1：Front-end architecture is provided, the front-end architecture includes the first grid layer and mask layer stacked gradually；
Step S2：First time etching is carried out to the mask layer；And
Step S3：The first grid layer, second of quarter are etched to expose out for the second time to the mask layer
Erosion is to the mask layer high selectivity in the selectivity to the first grid layer.
Refering to Fig. 4, before carrying out above-mentioned etching, a front-end architecture is provided, the front-end architecture includes a substrate 21, is located at
Oxide layer 22 on the substrate 21, the second grid 23 being located in the oxide layer 22 are located on the second grid layer 23
Dielectric layer 26, be located at the dielectric layer 26 on first grid layer 25, be located at the first grid layer 25 on mask layer 26.
Specifically, in one embodiment, the thickness range of the oxide layer 22 is 80~100 angstroms, can be 80 angstroms, 90
Angstrom, 100 angstroms；The thickness range of the second grid layer 23 is 270~330 angstroms, can be 280 angstroms, 300 angstroms, 330 angstroms；It is described
The thickness range of dielectric layer is 130~160 angstroms, can be 130 angstroms, 144 angstroms, 150 angstroms；The thickness model of the first grid layer 25
It is 540~660 angstroms to enclose, and can be 550 angstroms, 600 angstroms, 650 angstroms；The thickness range of the mask layer 26 is 3000~3630 angstroms,
It can be 3300 angstroms, 3400 angstroms, 3500 angstroms.
It is disposably complete to the etching of mask layer 26 on the first grid layer 25 in current method refering to Fig. 5 and Fig. 6
At in etching process, the etching selection ratio of the mask layer 26 and the first grid layer 25 is constant, specifically, the mask
The etching selection ratio ranging from 1~2 of layer 26 and the first grid layer 25 is stopped using arrival time described in etching mode progress
Etching, as shown in fig. 6, after the completion of the etching of the mask layer 26, can lose certain thickness first grid layer 26, pass through
The online scanning electron microscope thickness measurement online of EF90 platforms, after the completion of the etching of the mask layer 26, the first grid of loss
The thickness of pole layer 25 is close to 295 angstroms.
Refering to Fig. 7 and Fig. 8, in method provided by the present invention, to the etching of dielectric layer 26 on the control grid layer 25
It is divided into and carries out twice, etch for the first time, select lower etching selection ratio, the mask layer 26 is performed etching but will not be described
Mask layer 26 all etches away, and there are residues, carries out second later and etches, selects higher etching selection ratio, covered to described
Film layer 26 performs etching, and exposes the first grid layer.Specifically, stopping etching mode using arrival time carries out described the
Primary etching and second of etching, that is, limit etch period, reach required effect, further, select lower etching
Select the etching selection than referring to the mask layer 26 and the first grid layer 25 relatively low, specifically, 26 He of the mask layer
The etching selection ratio ranging from 1~2 of the first grid layer 25；Higher etching selection ratio is selected to refer to the mask layer 26 and institute
The etching selection for stating first grid layer 25 is higher, specifically, the etching of the mask layer 26 and the first grid layer 25 is selected
It selects than ranging from 4~6.Further, the second grid layer is floating boom, and the dielectric layer is ONO layer, the first grid
Grid, the control grid layer 25 are preferably polysilicon layer to layer in order to control, and the mask layer 26 is preferably silicon nitride layer, then for the first time
In etching, the etching selection ratio ranging from 1~2 of the silicon nitride and the polysilicon, in second etches, state silicon nitride and
The etching selection ratio of the polysilicon ranging from 4~6, it is preferred that the altitude range of the first time etching is 2520~3080
Angstrom, and the first time etching height be less than the mask layer thickness, and for the first time etch after, the mask layer there are about
15% residue.Using gas CF4Or CHF3Etching, etch period ranging from 49.5~60.5s, preferred time are 55s, institute
The height for stating second of etching is more than or equal to 650 angstroms, using gas CH3F is etched, etch period ranging from 54~66s, preferably
Time is 60s, and the required height (converting according to etch rate) etched is reached particular by etch period is limited.
Further, by improving etching selection ratio so that the loss of first grid layer caused by being etched due to mask layer
Reduce, specifically, by the online scanning electron microscope thickness measurement online of EF90 platforms, using on existing scheme etching control gate
After mask layer, the residual thickness of the control gate is about 337 angstroms, using mask on method provided by the present invention etching control gate
After layer, the residual thickness of the control gate is about 446 angstroms, compared with existing scheme, using method provided by the present invention, is being covered
After film layer etching, the residual thickness of the control gate increases, specifically, the residual thickness gain of the control gate is close to 110
Angstrom.Further, it also shows the residual thickness gain of the control gate in PCM tests there are about 100 angstroms.
Further, it is completed in second of etching etching, after exposing the first grid layer, in natural conditions
Under, the first grid layer surface can generate an oxide layer, when carrying out the etching of first grid layer, need first to its surface
Oxide layer performs etching, since the thickness of first grid layer is too thin, and when etching the oxide layer, the oxide layer with it is described
The etching selection of first grid layer is relatively low, specifically, using chlorine when etching the oxide layer, etches the first grid layer
When use chlorine or hydrogen bromide, it is described be based on above-mentioned 2 reasons, be easy in etching oxidation layer first grid etching wear
Thoroughly, and then the ONO laminate films of damage first grid layer bottom, the present invention pass through remaining first grid after mask layer is etched
Thickness increase, then when subsequently being etched to the oxide layer of first grid layer surface, come prevent this step at the beginning when just
First grid is etched through, to avoid the damage to first grid layer bottom ONO laminate films to a certain extent.
In conclusion in the forming method of semiconductor structure provided by the invention, front-end architecture, the front end knot are provided
Structure includes the first grid layer and mask layer stacked gradually；First time etching is carried out to the mask layer；And to the mask
Layer is etched to expose out the first grid layer for the second time, and second of etching is to the mask layer high selectivity in right
The selectivity of the first grid layer.The etching of mask layer on first grid layer is divided into the present invention and being carried out twice, first
There are residues after secondary etching etching, when the mask layer, when then carrying out second and etching, to the mask layer and described first
The etching selection ratio of grid layer increases so that and first grid layer loss caused by being etched due to mask layer is become smaller, and remaining first
Gate layer thickness increases.
Further, because the thickness of first grid is too thin, when the native oxide to first grid layer surface etches,
It is easy for first grid to etch away, the present invention is exactly by thickening the thickness of first grid, to prevent in the etching first grid
Just first grid is etched through when the oxide layer of pole layer surface, avoids the damage of first grid layer bottom ONO layer film
It is bad.And then avoid because ONO films damage, caused by shallow trench isolation loss it is more, cause active region region to expose,
When floating boom etches, the impaired problem of bottom active area, improves device performance.
The preferred embodiment of the present invention is above are only, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical scheme of the present invention, to the invention discloses technical solution and
Technology contents make the variations such as any type of equivalent replacement or modification, belong to the content without departing from technical scheme of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (12)
1. a kind of forming method of semiconductor structure, which is characterized in that including,
Front-end architecture is provided, the front-end architecture includes the first grid layer and mask layer stacked gradually；
First time etching is carried out to the mask layer；And
The first grid layer is etched to expose out for the second time to the mask layer, second of etching is to the mask
Layer-selective is higher than the selectivity to the first grid layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that described when second of etching
The etching selection ratio ranging from 4~6 of mask layer and the first grid layer.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that described when the first time etching
The etching selection ratio of mask layer and the first grid layer is 1~2.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that stop etching side using arrival time
Formula carries out the first time etching and described second etches.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the height model of the first time etching
It is 2520~3080 angstroms to enclose, including using gas CF4Or CHF3Etching.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the height of second of etching is big
In equal to 650 angstroms, including using gas CH3F is etched.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the mask layer is silicon nitride layer.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the front-end architecture further includes lining
Bottom, the oxide layer being located on the substrate are located at the second grid layer in the oxide layer and on the second grid layer
Dielectric layer, the first grid layer is located on the dielectric layer.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that completed in second of etching
Afterwards, the first grid layer surface generates oxide layer, and the oxide layer is removed using etching technics.
10. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the first grid layer is in order to control
Grid, the second grid layer are floating boom, and the dielectric layer is ONO layer.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the control grid layer is polysilicon
Layer.
12. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the thickness range of the mask layer
It it is 3000~3630 angstroms, the thickness range of the first grid layer is 540~660 angstroms, and the thickness range of the ONO layer is 130
~160 angstroms.
Priority Applications (1)
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| CN201810247065.4A CN108511448A (en) | 2018-03-23 | 2018-03-23 | The forming method of semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810247065.4A CN108511448A (en) | 2018-03-23 | 2018-03-23 | The forming method of semiconductor structure |
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| CN201810247065.4A Pending CN108511448A (en) | 2018-03-23 | 2018-03-23 | The forming method of semiconductor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113035699A (en) * | 2021-03-03 | 2021-06-25 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device |
| CN113964032A (en) * | 2020-07-20 | 2022-01-21 | 和舰芯片制造(苏州)股份有限公司 | Method of manufacturing nonvolatile memory array, computer device, and storage medium |
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| CN107204338A (en) * | 2017-05-23 | 2017-09-26 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory cell |
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| CN1449578A (en) * | 2000-06-30 | 2003-10-15 | 兰姆研究有限公司 | Method for etching dual damascene structures in organosilicate glass |
| US6627484B1 (en) * | 2000-11-13 | 2003-09-30 | Advanced Micro Devices, Inc. | Method of forming a buried interconnect on a semiconductor on insulator wafer and a device including a buried interconnect |
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Application publication date: 20180907 |