CN112908859B - Method for manufacturing flash memory - Google Patents
Method for manufacturing flash memory Download PDFInfo
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- CN112908859B CN112908859B CN202110313042.0A CN202110313042A CN112908859B CN 112908859 B CN112908859 B CN 112908859B CN 202110313042 A CN202110313042 A CN 202110313042A CN 112908859 B CN112908859 B CN 112908859B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 220
- 238000005530 etching Methods 0.000 claims abstract description 60
- 230000008569 process Effects 0.000 claims abstract description 26
- 239000003989 dielectric material Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 23
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- RAHZWNYVWXNFOC-UHFFFAOYSA-N Sulphur dioxide Chemical compound O=S=O RAHZWNYVWXNFOC-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a flash memory, which can increase the opening size of a second opening in a side wall material layer by thinning the thickness of the side wall material layer, so that a process window for subsequently etching the side wall material layer can be increased, and a part of control gate material layer can be exposed after the side wall material layer is etched to form the side wall layer, thereby avoiding the side wall layer from blocking the subsequent etching of the control gate material layer, breaking the control gate material layer when the control gate material layer is subsequently etched, and forming the control gate layer by using the broken control gate material layer, and further solving the problem of control gate short circuit in the flash memory caused by the blocking of the control gate material layer by the side wall layer.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for manufacturing a flash memory.
Background
In the current semiconductor industry, memory accounts for a significant proportion of integrated circuit products, and flash memory in memory has evolved particularly rapidly. The method is mainly characterized in that the method can keep stored information for a long time under the condition of no power-up, has the advantages of high integration level, high access speed, easy erasure and the like, and is widely applied to the fields of microcomputers, automatic control and the like.
Referring to fig. 1, which is a schematic cross-sectional view of a structure of a flash memory in the prior art, the manufacturing process of the flash memory is as follows: first, a semiconductor substrate 1 is provided, and a floating gate material layer 2, a control gate material layer 3, and a mask layer 4 are sequentially formed on the semiconductor substrate 1. Then, the mask layer 4 is etched to form an opening in the mask layer 4. Next, a layer of sidewall material is deposited along the sidewalls and bottom wall of the opening. Next, a first etching is performed to etch the sidewall material layer in the opening to form the sidewall layer 5. Next, a second etching is performed to etch the control gate material layer 3 in the opening to form a control gate layer. However, in the above steps, due to the limitation of the size of the flash memory device, when the opening in the mask layer 4 is smaller, and the sidewall material layers are deposited along the sidewalls and the bottom wall of the opening, the distance between the sidewall material layers on the opposite sidewalls of the opening is smaller, so that the etching window in the subsequent first etching is smaller, and therefore, after the first etching is performed to form the sidewall layer, the sidewall layer still covers the control gate material layer 3 (part of the thickness of the sidewall material layer remains on the surface of the control gate material layer 3), that is, the opening cannot expose the control gate material layer 3, and during the subsequent etching of the control gate material layer 3, the sidewall layer on the surface of the control gate material layer 3 can block the etching, thereby causing that the control gate material layer 3 cannot be broken, as shown in a dashed line frame 6 in fig. 1, the control gate material layer 3 cannot be broken, and thus causing a problem of a short circuit in the subsequently formed flash memory.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory, which aims to solve the problem of control gate short circuit.
In order to solve the above technical problems, the present invention provides a method for manufacturing a flash memory, including:
providing a semiconductor substrate, wherein a control gate material layer and a mask layer are sequentially formed on the semiconductor substrate;
forming a first opening in the mask layer, wherein the first opening exposes the control gate material layer;
Filling a side wall material layer in the first opening, wherein the side wall material layer covers the side wall and the bottom wall of the first opening, and the side wall material layer filling the first opening is provided with a recess to define a second opening;
thinning the thickness of the side wall material layer to increase the opening size of the second opening;
Etching the side wall material layer to further thin the thickness of the side wall material layer, removing the side wall material layer at the bottom of the first opening to form a side wall layer, and exposing part of the control gate material layer; and
And etching the exposed control gate material layer by taking the side wall layer as a mask to divide the control gate material layer and forming a control gate layer by using the divided control gate material layer.
Optionally, in the method for manufacturing a flash memory, the material of the sidewall layer includes silicon oxide.
Optionally, in the method for manufacturing a flash memory, the method for thinning the thickness of the sidewall material layer includes:
and removing part of the side wall material layer by using a dry etching process so as to thin the thickness of the side wall material layer.
Optionally, in the method for manufacturing a flash memory, when the thickness of the sidewall material layer is thinned, the etching gas is at least one of fluorine, argon, oxygen, sulfur dioxide, hydrogen bromide and carbon fluoride.
Optionally, in the method for manufacturing a flash memory, after filling the sidewall material layer in the first opening, before thinning the thickness of the sidewall material layer, the method further includes:
Measuring the thickness of the side wall material layer;
And comparing the thickness of the side wall material layer with the target thickness.
Optionally, the method for etching the sidewall material layer to form the sidewall layer includes: comparing the thickness of the side wall material layer with the target thickness;
Presetting etching time required for etching the side wall material layer according to a comparison result of the thickness of the side wall material layer compared with the target thickness and the thinned thickness of the side wall material layer;
And carrying out a wet etching process on the side wall material layer according to the preset etching time required by the side wall material layer until the side wall material layer at the bottom of the first opening is removed, and reducing the thickness of the side wall material layer on the side wall of the first opening to the target thickness to form the side wall layer and expose part of the control gate material layer, wherein the etching solution adopted in the wet etching process is diluted hydrofluoric acid solution.
Optionally, in the method for manufacturing a flash memory, before forming the control gate material layer, the method for manufacturing a flash memory further includes:
forming a floating gate structure layer, wherein the floating gate structure layer covers the surface of the semiconductor substrate;
Forming a shallow trench isolation structure which penetrates through the floating gate structure layer and extends into the semiconductor substrate; and
And forming a dielectric material layer, wherein the dielectric material layer covers the floating gate structure layer and the shallow trench isolation structure, and the control gate material layer covers the dielectric material layer.
Optionally, in the method for manufacturing a flash memory, the material of the dielectric material layer includes silicon oxide and/or silicon nitride.
Optionally, in the method for manufacturing a flash memory, the control gate layer has a third opening, and the third opening is communicated with the second opening and exposes a part of the dielectric material layer;
And after etching the exposed control gate material layer, etching the exposed dielectric material layer to form a dielectric layer, and etching the exposed dielectric material layer to form a dielectric layer.
Optionally, in the method for manufacturing a flash memory, the mask layer is made of silicon nitride and/or silicon oxynitride.
In the manufacturing method of the flash memory, the opening size of the second opening in the side wall material layer can be increased by thinning the thickness of the side wall material layer, so that a process window for subsequently etching the side wall material layer can be increased, and a part of the control gate material layer can be exposed after the side wall material layer is etched to form the side wall layer, thereby avoiding the situation that the side wall layer blocks the subsequently etched control gate material layer, breaking the control gate material layer when the control gate material layer is subsequently etched, and forming the control gate layer by using the broken control gate material layer, so that the problem of control gate short circuit in the flash memory caused by the blocking of the etched control gate material layer by the side wall layer can be solved.
Drawings
FIG. 1 is a schematic diagram of a prior art flash memory;
FIG. 2 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the invention;
Fig. 3 to 8 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the invention;
FIG. 9 is a diagram illustrating a relationship between a pattern density and a thickness of a sidewall material layer in a method for manufacturing a flash memory according to an embodiment of the present invention;
Fig. 10 to 11 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the invention;
Wherein reference numerals are as follows:
1-a semiconductor substrate; 2-floating gate structure; 3-a control gate material layer; 4-a mask layer; 5-a side wall layer;
10-a semiconductor substrate; ;
20-floating gate structure;
30-a layer of dielectric material; 30 a-a dielectric layer;
31-a first layer of oxide material; 31 a-a first oxide layer;
a layer of 32-nitrided material; 32 a-a nitride layer;
33-a layer of a second oxide material; 33 a-a second oxide layer;
40-a control gate material layer;
50-masking layer; 50 a-a first opening;
60-a side wall material layer; 60 a-a side wall layer;
70-a second opening;
80-third opening.
Detailed Description
The method for manufacturing the flash memory according to the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 2, a flow chart of a method for manufacturing a flash memory according to an embodiment of the invention is shown. As shown in fig. 2, the method for manufacturing the flash memory includes:
Step S1: providing a semiconductor substrate, wherein a control gate material layer and a mask layer are sequentially formed on the semiconductor substrate;
Step S2: forming a first opening in the mask layer, wherein the first opening exposes the control gate material layer;
Step S3: filling a side wall material layer in the first opening, wherein the side wall material layer covers the side wall and the bottom wall of the first opening, and the side wall material layer filling the first opening is provided with a recess to define a second opening;
step S4: thinning the thickness of the side wall material layer to increase the opening size of the second opening;
step S5: etching the side wall material layer to further thin the thickness of the side wall material layer, removing the side wall material layer at the bottom of the first opening to form a side wall layer, and exposing part of the control gate material layer; and
Step S6: and etching the exposed control gate material layer by taking the side wall layer as a mask to divide the control gate material layer and forming a control gate layer by using the divided control gate material layer.
Next, the above steps will be described in more detail with reference to fig. 3 to 11. Fig. 3 to 8 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the invention;
FIG. 9 is a schematic diagram showing a linear relationship between a pattern density and a thickness of a sidewall material layer in a method for manufacturing a flash memory according to an embodiment of the present invention; fig. 10 to 11 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the invention.
First, step S1 is performed, and referring to fig. 1, a semiconductor substrate 10 is provided. Specifically, the semiconductor substrate 10 may be silicon or silicon germanium of a single crystal, polycrystalline or amorphous structure, or may be silicon-on-insulator SOI. In this embodiment, the semiconductor substrate 10 may be a silicon substrate, and the active region and the well structure in the active region are formed by a doping process, such as an ion implantation process.
Next, a floating gate structure layer 20 is formed on the semiconductor substrate 10, the floating gate structure layer 20 including a floating gate oxide layer (GOX) and a floating gate layer (not shown) covering the floating gate oxide layer. The floating gate oxide layer, which is used to isolate the semiconductor substrate 10 from the floating gate layer, includes, but is not limited to, silicon dioxide, preferably silicon dioxide, to facilitate interfacial adhesion between the layers. Further, the floating Gate Oxide (GOX) may be formed by Low Pressure Chemical Vapor Deposition (LPCVD), thermal oxidation, molecular beam epitaxy, etc., and the thickness thereof may be, for example, 90-100 angstroms according to specific process requirements.
In this embodiment, the material of the floating gate layer may be undoped polysilicon, doped polysilicon doped with phosphorus, metal nanocrystals, silicon germanium nanocrystals or other suitable conductive materials, and the floating gate layer may be formed by a deposition process, for example, a chemical vapor deposition process, which is used to form a Floating Gate (FG) that can trap or lose electrons, so that the finally formed flash memory has the functions of storing and erasing.
Next, referring to fig. 4, a shallow trench isolation structure (not shown) is formed, which penetrates through the floating gate structure layer 20 and extends into the semiconductor substrate 10 to define an active region of the semiconductor substrate 10 for forming a memory cell.
Next, a dielectric material layer 30, a control gate material layer 40 and a mask layer 50 are sequentially formed, wherein the dielectric material layer 30 covers the shallow trench isolation structure and the floating gate structure layer 20, and the control gate material layer 40 covers the dielectric material layer 30. The material of the dielectric material layer 30 includes silicon oxide and/or silicon nitride, and in this embodiment, the dielectric material layer 30 may include a first oxide material layer 31, a nitride material layer 32, and a second oxide material layer 33 that are sequentially stacked. The dielectric material layer 30 is used to isolate the floating gate structure layer 20 from the control gate material layer 40.
The material of the control gate material layer 40 may be undoped polysilicon, doped polysilicon doped with phosphorus, metal nanocrystalline, silicon germanium nanocrystalline, or other suitable conductive material, and the control gate material layer 40 may be formed by a deposition process, for example, a chemical vapor deposition process. The control gate material layer 40 is used for forming a control gate later, wherein the thickness of the control gate material layer 40 may be 500-600 angstroms, for example.
The mask layer 50 covers the control gate material layer 40, and the mask layer 50 may be made of silicon nitride and/or silicon oxynitride. The thickness of the mask layer can be 2000-3300 angstroms.
Next, step S2 is performed, referring to fig. 5, a first opening 50a is formed in the mask layer 50, and the first opening 50a exposes the control gate material layer 40. The specific method comprises the following steps: first, a patterned photoresist layer (not shown) is formed on the mask layer 50, wherein the patterned photoresist layer has a photoresist opening therein, and the photoresist opening exposes a portion of the mask layer 50. Next, the mask layer 50 is etched using a dry etching process to form a first opening 50a in the mask layer 50. The patterned photoresist layer is then removed.
Then, the first opening 50a may be cleaned before the deposition of the sidewall material layer, so as to prevent the etching byproducts remaining in the first opening 50a from affecting the deposition effect of the subsequent sidewall material layer.
Next, step S3 is performed, referring to fig. 6, a sidewall material layer 60 is filled in the first opening, the sidewall material layer 60 covers the sidewall and the bottom wall (or the exposed control gate material layer) of the first opening 50a, and the sidewall material layer 60 filling the first opening has a recess to define a second opening 70. The material of the sidewall material layer 60 includes silicon oxide, and in other embodiments of the present invention, the material of the sidewall material layer 60 may include silicon nitride and silicon oxynitride. The thickness of the sidewall material layer 60 may be 1100-1300 a, for example.
Further, the sidewall material layer 60 may be formed by a low pressure vapor deposition (LPCVD) process of tetraethyl orthosilicate (TEOS), and after the sidewall material layer 60 is deposited, the deposited thickness of the sidewall material layer 60 may be measured to ensure that the critical dimension error of the sidewall material layer 60 filled in the first opening 50a meets the requirement. Optionally, after forming the sidewall material layer 60, the device may be continuously annealed rapidly to improve the compactness of the sidewall material layer 60. For example, the process temperature for depositing the sidewall material layer 60 may be 300 to 1000 ℃, the annealing temperature may be 500 to 1200 ℃, and the annealing time may be 20 to 110 seconds.
Next, the thickness of the sidewall material layer 60 is measured, and the thickness of the sidewall material layer 60 may be measured by an Optical Critical Dimension (OCD) measuring method, which uses an OCD measuring and analyzing system, or may be measured by a film thickness measuring machine. And comparing the thickness of the side wall material layer 60 with the target thickness, wherein the comparison result is used for the etching time required for the subsequent preset etching of the side wall material layer.
Next, step S4 is performed, referring to fig. 7, to thin the thickness of the sidewall material layer 60, so as to increase the opening size of the second opening 70. Specifically, a dry etching process may be used to remove a portion of the sidewall material layer 60, that is, remove a portion of the sidewall material layer 60 located on the sidewall of the second opening 70, and remove a portion of the sidewall material layer 60 located at the bottom of the second opening 70, so as to thin the thickness of the sidewall material layer 60, thereby increasing the width and depth dimensions of the second opening 50 a. The thickness of the sidewall material layer 60 may be reduced by, for example, 20 to 100 angstroms, for example, 20 to 50 angstroms or 100 angstroms, so as to increase the process window for subsequent etching of the sidewall material layer 60.
In this embodiment, when the thickness of the sidewall material layer 60 is thinned, the etching gas may be at least one of fluorine, argon, oxygen, sulfur dioxide, hydrogen bromide and carbon fluoride.
Next, step S5 is performed, referring to fig. 8, etching the sidewall material layer 60 to further thin the thickness of the sidewall material layer 60, and removing the sidewall material layer 60 at the bottom of the first opening 50a to form a sidewall layer 60a, and exposing a portion of the control gate material layer 40. Specifically, the method for etching the sidewall material layer 60 to form the sidewall layer 60a includes: firstly, the etching time required for etching the sidewall material layer 60 is preset according to the comparison result of the compared thickness of the sidewall material layer and the target thickness, and the thinned thickness of the sidewall material layer 60, wherein the target thickness can be, for example, 900-1100 angstroms. Then, a wet etching process is performed on the sidewall material layer 60 according to a preset etching time required for the sidewall material layer 60 until the sidewall material layer 60 at the bottom of the second opening 70 is removed (i.e., a portion of the sidewall material layer covering the bottom wall of the first opening is removed), and the thickness of the sidewall material layer 60 on the sidewall of the first opening is reduced to the target thickness, so as to form the sidewall layer 60a and expose a portion of the control gate material layer 40. In this manner, the opening size of the second opening 70 may be further increased, and a portion of the control gate material layer 40 may be exposed, i.e., the sidewall material layer 60 on the sidewall of the second opening may be left to form the sidewall layer 60a. Since the opening size of the second opening 50a is increased in step S4, when the wet etching process is performed on the sidewall material layer 60, the etching solution can sufficiently infiltrate into the sidewall material layer 60, so that the sidewall material layer 60 can be prevented from remaining at the bottom of the second opening 70, that is, the formed sidewall layer 60a can be prevented from exposing a portion of the control gate material layer 40, so that the subsequent sidewall layer 60a is prevented from blocking the etching control gate material layer 40.
The etching solution adopted in the wet etching process is diluted hydrofluoric acid solution (DHF), the etching time of the wet etching process is, for example, 30 s-150 s, and the ratio of water in the diluted hydrofluoric acid solution to hydrofluoric acid can be, for example, 20:1-100:1.
Further, the pattern density (PATTERN DENSITY) of each memory cell in the flash memory is different, and when the sidewall material layer 60 is formed, the thickness of the sidewall material layer formed by the different pattern densities is different, so that the size of the corresponding second opening is also different, as shown in fig. 9, and the pattern density and the thickness of the sidewall material layer have a linear relationship. Based on this, in this embodiment, the etching time required for etching the sidewall material layer 60 is preset by comparing the thickness of the sidewall material layer 60 with the target thickness, and according to the comparison result of the compared thickness of the sidewall material layer 60 with the target thickness, and the thinned thickness of the sidewall material layer 60. Therefore, proper etching process conditions (such as etching time of an etching process) can be selected according to the thicknesses of the side wall material layers corresponding to different pattern densities (PATTERN DENSITY), and etching amounts (such as etching 50 angstroms or 100 angstroms) of the side wall material layers corresponding to different pattern densities are selected according to the thicknesses of the side wall material layers, so that the thicknesses of the finally formed side wall layers are reduced to target thicknesses, and further the dimension (FGSP CD) of the side wall layer of the platform can be stable and uniform.
Next, referring to fig. 10, the exposed control gate material layer 40 is etched using the sidewall layer 60a as a mask to divide the control gate material layer 40, and the control gate layer 40a is formed using the divided control gate material layer 40. Specifically, the control gate layer 40a has a third opening 80 therein, and the third opening 80 communicates with the second opening 70 and exposes a portion of the dielectric material layer 30. Further, the exposed control gate material layer 40 may be etched using a plasma dry etching process to form a third opening 80, and the control gate material layer 40 may be divided using the third opening 80, thereby forming the control gate layer 40a. In this step, since a portion of the control gate material layer 40 is exposed by the sidewall layer 60a, a portion of the control gate material layer 40 may be exposed in the second opening 70, and thus the control gate material layer 40 exposed by etching may be divided and the divided control gate material layer 40 may be used to form the control gate layer 40a, so that the problem of control gate short circuit in the flash memory caused by the barrier etching of the control gate material layer 40 by the sidewall layer 60a may be solved.
Further, referring to fig. 11, after etching the control gate material layer 40, the dielectric material layer 30 is also etched to form a dielectric layer 30a. Specifically, the method for etching the dielectric material layer 30 includes: etching the second oxide material layer 33 by using a plasma dry etching process to form a second oxide layer 33a; and etching the nitride material layer 32 to form a nitride layer 32a; and etching the first oxide material layer 31 to form a first oxide layer 31a.
After step S6, word lines may be formed in the second opening 70 and the third opening 80, thereby completing the fabrication of the entire flash memory.
In summary, in the method for manufacturing the flash memory provided by the embodiment of the invention, the thickness of the side wall material layer is thinned, so that the opening size of the second opening in the side wall material layer can be increased, the process window for subsequently etching the side wall material layer can be increased, and a part of the control gate material layer can be exposed after the side wall material layer is etched to form the side wall layer, thereby avoiding the situation that the side wall layer blocks the subsequently etched control gate material layer, and further, when the subsequently etched control gate material layer, the control gate material layer can be broken, and the broken control gate material layer is utilized to form the control gate layer, so that the problem of control gate short circuit in the flash memory caused by the blocking of the etched control gate material layer by the side wall layer can be solved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (8)
1. A method of manufacturing a flash memory, comprising:
providing a semiconductor substrate, wherein a control gate material layer and a mask layer are sequentially formed on the semiconductor substrate;
forming a first opening in the mask layer, wherein the first opening exposes the control gate material layer;
Filling a side wall material layer in the first opening, wherein the side wall material layer covers the side wall and the bottom wall of the first opening, and the side wall material layer filling the first opening is provided with a recess to define a second opening;
Measuring the thickness of the side wall material layer;
comparing the thickness of the side wall material layer with the target thickness;
thinning the thickness of the side wall material layer to increase the opening size of the second opening;
Presetting etching time required for etching the side wall material layer according to a comparison result of the thickness of the side wall material layer compared with the target thickness and the thinned thickness of the side wall material layer;
Performing wet etching on the side wall material layer until the side wall material layer at the bottom of the first opening is removed according to the preset etching time required by the side wall material layer, so as to further thin the thickness of the side wall material layer, and removing the side wall material layer at the bottom of the first opening, so that the thickness of the side wall material layer at the side wall of the first opening is reduced to the target thickness, so as to form the side wall layer, and exposing part of the control gate material layer, wherein the etching solution adopted by the wet etching process is diluted hydrofluoric acid solution; and
And etching the exposed control gate material layer by taking the side wall layer as a mask to divide the control gate material layer and forming a control gate layer by using the divided control gate material layer.
2. The method of claim 1, wherein the sidewall layer comprises silicon oxide.
3. The method of claim 1, wherein the method of thinning the thickness of the sidewall material layer comprises:
and removing part of the side wall material layer by using a dry etching process so as to thin the thickness of the side wall material layer.
4. The method of claim 3, wherein the etching gas used in thinning the thickness of the sidewall material layer is at least one of fluorine, argon, oxygen, sulfur dioxide, hydrogen bromide, and carbon fluoride.
5. The method of manufacturing a flash memory device according to claim 1, wherein before forming the control gate material layer, the method of manufacturing a flash memory device further comprises:
forming a floating gate structure layer, wherein the floating gate structure layer covers the surface of the semiconductor substrate;
Forming a shallow trench isolation structure which penetrates through the floating gate structure layer and extends into the semiconductor substrate; and
And forming a dielectric material layer, wherein the dielectric material layer covers the floating gate structure layer and the shallow trench isolation structure, and the control gate material layer covers the dielectric material layer.
6. The method of claim 5, wherein the dielectric material layer comprises silicon oxide and/or silicon nitride.
7. The method of manufacturing a flash memory device of claim 6, wherein the control gate layer has a third opening therein, the third opening being in communication with the second opening and exposing a portion of the dielectric material layer;
And etching the exposed dielectric material layer after etching the exposed control gate material layer to form a dielectric layer.
8. The method of claim 1, wherein the mask layer is made of silicon nitride and/or silicon oxynitride.
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