CN103943462A - Method for eliminating load effect generated by thin film deposition - Google Patents

Method for eliminating load effect generated by thin film deposition Download PDF

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Publication number
CN103943462A
CN103943462A CN201410174773.1A CN201410174773A CN103943462A CN 103943462 A CN103943462 A CN 103943462A CN 201410174773 A CN201410174773 A CN 201410174773A CN 103943462 A CN103943462 A CN 103943462A
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gate
step
method according
thin film
process
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CN201410174773.1A
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崇二敏
黄君
毛志彪
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上海华力微电子有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The invention provides a method for eliminating a load effect generated by thin films deposited after a short-channel effect is lowered. Firstly, ion injection is carried out by adopting a method for increasing the width of grid side walls, so that the short-channel effect is lowered; then the width of the grid side walls is reduced, and the thin film deposition process is then carried out. The method for reducing the width of the grid side walls comprises the steps of protecting grids and the tops of the grid side walls by utilizing an anti-reflecting layer, defining the width which the grid side walls need to be reduced by utilizing the patterned anti-reflecting layer, and then adopting a dry etching process to etch and thin the grid side walls. Obviously, due to the fact that the width of the grid side walls is reduced, the filling space among the grids is increased, thin film filling capacity among the grids is further improved, and the load effect generated after the thin film deposition is carried out after the existing method of lowering the sort-channel effect is adopted is avoided.

Description

针对薄膜沉积产生负载效应的消除方法 Generating elimination method for the loading effect of the thin film deposition

技术领域 FIELD

[0001] 本发明涉及半导体技术领域,特别涉及一种在降低短沟道效应后所沉积的薄膜产生负载效应的消除方法。 [0001] The present invention relates to semiconductor technology, and more particularly to a method of generating eliminate the loading effect of the reduction in the short channel effect film deposited.

背景技术 Background technique

[0002] 随着工艺尺寸不断缩小,特别是65nm及其以下,由于栅极自身及其侧墙的宽度进一步减小,源漏区的离子注入更加接近沟道(channel),导致器件的短沟道效应非常明显。 [0002] As process dimensions shrink, especially 65nm and below, since the width of the gate and the spacer itself is further reduced, the ion implantation of the source and drain regions closer to the channel (Channel), resulting in short channel devices channel effect is obvious. 为了降低短沟道效应,现有的主流工艺是在形成栅极和栅极侧墙的半导体衬底上,通过调节源漏区的离子注入的剂量、注入能量、注入角度、或改变注入离子的种类等方式来解决短沟道效应问题。 In order to reduce the short channel effect, the conventional technology is the mainstream in the semiconductor substrate is formed on a sidewall of the gate electrode and the gate, source and drain regions by adjusting the dose of ion implantation, the implantation energy, implantation angle, or changing the implanted ions species and other ways to solve the problem of short-channel effects. 但是,由于离子注入对器件的影响非常大,所以通过离子注入来解决短沟道效应的工艺窗口非常小。 However, due to the ion implantation effect on the device is very large, so to solve the short-channel effect by ion implantation process window is very small.

[0003] 此外,还有一种解决短沟道效应问题的方法,是通过增加栅极侧墙的宽度来增大离子注入与channel之间的距离;请参阅图1_3,图1为形成栅极和栅极侧墙之后的衬底截面结构示意图,图2为增加侧墙宽度之后的衬底截面结构示意图,图3为在图2中的衬底上沉积薄膜之后的截面结构示意图,其中,I表示衬底,2表示栅极,3表示栅极侧墙,4表示所沉积的薄膜。 [0003] In addition, there is a solution to the short channel effect problem is to increase the distance between the ion implantation and by increasing the channel width of the gate sidewall spacer; see FIG. 1_3, FIG. 1 to form the gate electrode and schematic cross-sectional structure of the substrate after the substrate is a schematic cross-sectional structure after the gate spacer, the width of the spacer 2 is increased, FIG. 3 is a schematic cross-sectional structure after depositing a thin film on a substrate in FIG. 2, where, I represents substrate, 2 denotes a gate, 3 denotes a gate sidewall film, 4 denotes deposited.

[0004] 增加栅极侧墙宽度虽然能够增大离子注入和channel之间的距离,然而,由于栅极侧墙变宽,导致栅极与栅极之间的有效空间变小,从而在后续应力接近技术(SMT)或硅化金属阻止区(SAB)制程中导致薄膜填充的工艺窗口减小,进行薄膜沉积后出现负载效应。 [0004] Although increasing the gate width of the spacer can be increased and the distance between the Channel ion implantation, however, since the gate sidewall spacer is widened, resulting in the effective space between the gate and the gate becomes small, so that the subsequent stress after loading effect proximity technology (SMT) or a metal silicide blocking region (SAB) process results in reduced process window filled film, a thin film deposition. 如图3所示,所沉积的薄膜4底部的厚度(虚线a和a'之间的厚度)远大于薄膜4顶部的厚度(虚线b和b'之间的厚度),即出现负载效应;侧墙3之间的距离减小,很容易导致侧墙3之间的薄膜4无法完全沉积在衬底I的表面,从而造成薄膜填充能力下降。 3, (the broken line a and a bottom thickness of the deposited film 4 'between the thickness) is much larger than (the thickness of the broken lines b and b top film 4' between the thickness), i.e. the load effect occurs; side reducing the distance between the walls 3, 4 can easily lead to a thin film between the spacer 3 can not be completely deposited on the surface of the substrate I, resulting in a decline film filling capability.

[0005] 因此,需要改进现有工艺,在沿用第二种方法降低短沟道效应的同时,增大栅极之间的空间和薄膜填充能力,避免后续所沉积的薄膜产生负载效应。 [0005] Accordingly, a need to improve existing processes, while in use the second method to reduce short-channel effects, and increase the space between the gate filling capacity film, the deposited film to avoid subsequent loading effect is generated.

发明内容 SUMMARY

[0006] 为了克服上述问题,本发明目的是在降低短沟道效应后消除在薄膜沉积工艺中出现负载效应的方法,以期在解决短沟道效应问题的同时,增大栅极之间的填充空间,避免后续所沉积的薄膜产生负载效应。 [0006] In order to overcome the above problems, an object of the present invention is a process for loading effect occurs in the thin film deposition process in elimination after reducing short channel effects, while in order to solve the problem of the short channel effect, increases the filling between the gate space, avoiding subsequent deposited film loading effect is generated.

[0007] 本发明提供了一种在降低短沟道效应后所沉积的薄膜产生负载效应的消除方法,其包括以下步骤: [0007] The present invention provides a film comprising reducing short channel effects in the deposited loading effect produced elimination method, comprising the steps of:

[0008] 步骤SOl:在半导体衬底上形成栅极和栅极侧墙; [0008] Step SOl: forming a gate and a gate sidewall spacer on the semiconductor substrate;

[0009] 步骤S02:增加所述栅极侧墙的宽度,并对所述半导体衬底进行源漏区离子注入; [0009] Step S02: increasing the width of the gate sidewall spacers, and said source and drain regions of the semiconductor substrate is ion-implanted;

[0010] 步骤S03:在所述半导体衬底上覆盖一层抗反射层; [0010] Step S03: covered with anti-reflection layer on the semiconductor substrate;

[0011] 步骤S04:在所述抗反射层表面涂覆光刻胶,采用光刻工艺,图案化所述光刻胶,在所述光刻胶中形成所述栅极侧墙要减薄区域的图案;[0012] 步骤S05:以图案化的所述光刻胶为模版,采用干法刻蚀工艺,图案化所述抗反射层,在所述抗反射层中形成所述栅极侧墙要减薄区域的图案; [0011] Step S04: the antireflective layer in the photoresist surface is coated photoresist using a photolithography process, patterning the gate sidewall spacer is formed in the photoresist to be thinned region pattern; [0012] step S05: a gate sidewall spacer to the patterned photoresist as a template, using a dry etching process, patterning the anti-reflection layer, formed in said anti-reflective layer to thinned pattern region;

[0013] 步骤S06:以图案化的所述抗反射层为掩膜,经干法刻蚀工艺,减薄所述栅极侧m ; [0013] Step S06: In the anti-reflective layer is patterned as a mask, by a dry etching process, thinning the gate side m;

[0014] 步骤S07:在所述半导体衬底上沉积薄膜。 [0014] Step S07: depositing a thin film on the semiconductor substrate.

[0015] 优选地,所述步骤S04中,在减薄所述栅极侧墙之后,采用等离子体干法刻蚀工艺去除剩余的所述光刻胶和/或所述抗反射层。 [0015] Preferably, the step S04, after thinning the gate sidewall spacer, a dry etching process using the plasma is removed and / or the anti-reflection layer of the remaining photoresist.

[0016] 进一步地,所述等离子体干法刻蚀工艺中利用纯O2或SO2作为反应气体。 [0016] Further, the plasma dry etching process utilizing pure O2 or SO2 as a reaction gas.

[0017] 进一步地,所述等离子体干法刻蚀工艺所采用的反应压强为5-15mT0rr,上电极功率为500-1500瓦,下电极电压为零,气体流量为150-250sccm,反应时间为40-80秒。 [0017] Further, the reaction pressure of the plasma dry etching process employed is 5-15mT0rr, an upper electrode 500 to 1500 watts of power, a lower electrode voltage is zero, the gas flow rate 150-250sccm, the reaction time is 40-80 seconds.

[0018] 优选地,所述步骤S05中,采用HBr和O2的混合气体作为反应气体。 [0018] Preferably, in the step S05, using a mixed gas of HBr and O2 as the reaction gas. 进一步地,所述步骤S05中,所述HBr与所述O2的流量比例为1:1至15:2。 Further, in the step S05, the flow ratio of the O2 HBr is 1: 1 to 15: 2.

[0019] 优选地,所述步骤S05中,所采用的反应压强为5-10mTorr,所采用的上电极功率为300-500瓦,反应时间为10-80秒。 [0019] Preferably, in the step S05, a reaction pressure employed was 5-10mTorr, the electrodes of the power used for the tiles 300-500, the reaction time is 10 to 80 seconds.

[0020] 优选地,所述步骤S06中,采用氟系气体刻蚀所述栅极侧墙。 [0020] Preferably, in the step S06, the fluorine-based etching gas gate spacers. 进一步地,所述步骤S06中,所述氟系气体为CH2F2和CHF3的混合气体。 Further, in the step S06, the fluorine-based gas is a mixed gas of CHF3 and CH2F2. 更进一步地,所述步骤S06中,所述CH2F2与所述CHF3的流量比例为1:1至4:1。 Still further, in the step S06, the flow ratio of said CHF3 and CH2F2 is 1: 1 to 4: 1.

[0021] 优选地,所述步骤S06中,所采用的反应压强为20-40mTorr,所采用的上电极功率为500-800瓦,所采用的下电极电压为O,反应时间为10-40秒。 Upper electrode of the power [0021] Preferably, in the step S06, a reaction pressure employed was 20-40mTorr, 500-800 watts is used, the lower electrode voltage employed is O, the reaction time of 10-40 seconds .

[0022] 优选地,所述步骤S07中,所述薄膜为应力记忆技术或硅化物阻止区制程中形成的。 [0022] Preferably, in the step S07, the film is a stress memorization technique or a silicide blocking region formed in the process.

[0023] 本发明的在降低短沟道效应后所沉积的薄膜产生负载效应的消除方法,先采用增加栅极侧墙的宽度方法进行离子注入,来降低短沟道效应;然后,减小栅极侧墙的宽度,再进行薄膜沉积工艺。 [0023] After reducing the short channel effect of the deposited film of the present invention is a method to eliminate the loading effect of generating, using the first method of increasing the width of the gate sidewall spacer is ion implantation, to reduce short-channel effects; then, reduce the gate spacer pole width, then the thin film deposition process. 减小栅极侧墙宽度的方法:利用抗反射层保护住栅极和栅极侧墙的顶部,并利用图案化的抗反射层来定义栅极侧墙要减少的宽度,再采用干法刻蚀工艺刻蚀减薄栅极侧墙。 The method of reducing the gate width of the spacer: using a top anti-reflective layer protection live gate and the gate sidewall spacers, and using the patterned antireflective layer to define the width of the gate spacers to be reduced, then using a dry engraved etching process of etching the thinned gate spacers. 很明显,由于栅极侧墙的宽度减少了,栅极之间的填充空间就增加了,从而进一步提升栅极之间的薄膜填充能力,避免采用现有方法进行薄膜沉积时出现的负载效应。 Obviously, since the width of the gate sidewall spacer is reduced, filling the space between the gate electrode increases, thereby further enhancing the filling capacity of the thin film between the gate, to avoid loading effect that occurs when using conventional film deposition method.

附图说明 BRIEF DESCRIPTION

[0024] 图1为形成栅极和栅极侧墙之后的衬底截面结构示意图 Schematic cross-sectional structure of the substrate after [0024] FIG. 1 is a gate electrode and a gate sidewall spacer is formed

[0025] 图2为增加侧墙宽度之后的衬底截面结构示意图 Schematic cross-sectional structure of the substrate after [0025] FIG. 2 is a spacer width increases

[0026] 图3为在图2中的衬底上沉积薄膜之后的截面结构示意图 [0026] FIG. 3 is a schematic view in cross-section in FIG. 2 on the substrate after film deposition

[0027] 图4为本发明的一个较佳实施例的针对所沉积的薄膜产生的负载效应的消除方法的流程示意图 Methods for loading effect flow generated for a thin film deposited [0027] FIG 4 is a preferred embodiment of the present invention, a schematic embodiment

[0028] 图5-11为本发明的上述较佳实施例的针对所沉积的薄膜产生的负载效应的消除方法的各个步骤所对应的截面结构示意图 [0028] The cross-sectional structural diagram of the various steps of the method for eliminating the deposited film loading effect produced by the present invention, FIG. 5-11 preferred embodiments corresponding to the embodiments

具体实施方式 Detailed ways

[0029] 为使本发明的内容更加清楚易懂,以下结合说明书附图,对本发明的内容作进一步说明。 [0029] To make the present invention more clearly understood, the following description in conjunction with the accompanying drawings, the present invention will be further described. 当然本发明并不局限于该具体实施例,本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。 Of course, the present invention is not limited to this specific example embodiments, those skilled in the art generally known alternative also encompassed within the scope of the present invention.

[0030] 以下将结合具体实施例和附图4-11对本发明的在降低短沟道效应之后薄膜沉积过程中出现负载效应的消除方法作进一步详细说明。 [0030] 4-11 further below in conjunction with the accompanying drawings and detailed description of embodiments of the present invention to eliminate the loading effect of the method appears as a thin film deposition process after reducing short channel effects specific embodiments. 其中,图4为本发明的一个较佳实施例的针对所沉积的薄膜产生的负载效应的消除方法的流程示意图,图5-11为本发明的上述较佳实施例的针对所沉积的薄膜产生的负载效应的消除方法的各个步骤所对应的截面结构示意图。 The thin film deposited is generated for the preferred embodiment wherein a schematic flow chart of the loading effect, a preferred embodiment of the present invention. FIG. 4 for the deposited film produced by the method of elimination, the present invention FIG. 5-11 a cross-sectional structural diagram of the various steps of the method to eliminate the loading effect of the corresponding.

[0031] 请参阅图4,本实施例的在降低短沟道效应之后薄膜沉积过程中出现负载效应的消除方法,具体包括以下步骤: [0031] Referring to FIG. 4, the loading effect of the elimination method after reducing short channel effect occurs during film deposition in the present embodiment, includes the following steps:

[0032] 步骤SOl:请参阅图5,在半导体衬底101上形成栅极102和栅极侧墙103 ; [0032] Step SOl: Refer to FIG. 5, the gate electrode 102 and the gate sidewall spacer 103 is formed on the semiconductor substrate 101;

[0033] 这里,可以采用现有的常规工艺来形成栅极102和栅极侧墙103,还可以但不限于包括硅化物的形成等工艺来形成本发明的半导体衬底101。 [0033] Here, to form the gate electrode 102 and the gate spacers 103, but may also be limited to a process comprising forming silicide the semiconductor substrate 101 is formed like the present invention may employ existing conventional processes.

[0034] 本实施例中,半导体衬底101可以但不限于为娃衬底,半导体衬底101的表面具有一层氧化膜,其成分可以为热氧化生成的氧化硅材料,栅极102和栅极侧墙103位于该氧化膜的表面上,本发明对此不再赘述。 Silicon oxide material [0034] In this embodiment, the semiconductor substrate 101 may be, but is not limited to the baby as a substrate, a semiconductor substrate 101 having a surface oxide film, which may be generated as a component of thermal oxidation, the gate electrode 102 and the gate pole located on the sidewall surface of the oxide film 103, the present invention does not repeated. 栅极侧墙103的材料可以为氮化硅、氧化硅等,较佳的,本实施例中,采用氮化硅作为栅极侧墙103的材料。 The gate sidewall spacer 103 material may be silicon nitride, silicon oxide, preferred, embodiment according to the present embodiment, a silicon nitride material is employed as the gate spacers 103.

[0035] 步骤S02:请参阅图6,增加栅极侧墙103的宽度,并对半导体衬底101进行源漏区离子注入; [0035] Step S02: Refer to FIG. 6, the increased width of the gate spacers 103, source and drain regions and for the ion implantation of the semiconductor substrate 101;

[0036] 这里,增加栅极侧墙103宽度,从而形成栅极侧墙103”,增加栅极侧墙103宽度的方法可以采用现有的工艺来完成,本发明对此不再作详细描述;众所周知,在栅极侧墙103宽度增加后,进行源漏区的离子注入,可以增加离子注入区域与沟道的距离,从而降低短沟道效应,这是本领域的技术人员可以知晓的,本发明对此不再赘述。 [0036] Here, the increasing width of the gate spacers 103, spacers 103 are formed so that the gate ", a method of increasing the gate width of the spacer 103 of the conventional process may be accomplished using the present invention does not be described in detail; is well known, an increase in the width of the gate spacers 103, source and drain regions by ion implantation, the ion implantation may be increased with distance from the channel region, thereby reducing the short-channel effect, as one skilled in the art can be known, and the present the invention is not repeated.

[0037] 步骤S03:请参阅图7,在半导体衬底101上覆盖一层抗反射层104 ; [0037] Step S03: Refer to FIG. 7, covered with anti-reflection layer 104 on the semiconductor substrate 101;

[0038] 具体的,可以采用机械法在半导体衬底101上涂覆一层抗反射层104,较佳的,抗反射层104可以为底部抗反射层,比如可以为有机抗反射层,这是由于在后续的工艺中,要在抗反射层上涂覆光刻胶进行光刻工艺,底部抗反射层可以有效减小在光刻胶曝光过程中光刻胶底部对光线的反射,提高曝光质量。 [0038] Specifically, the mechanical methods can be employed on a semiconductor substrate 101 coated with an antireflection layer 104, preferably, the anti-reflection layer 104 may be a bottom anti-reflective layer, for example may be an organic anti-reflective layer, which is Since the subsequent process, a photolithography process to be performed on the antireflection coating a photoresist layer, a bottom anti-reflective layer can effectively reduce the reflection of light at the bottom of the photoresist in the photoresist during exposure, improve the quality of exposure . 这里,抗反射层104包裹住栅极102和栅极侧墙103”,不仅可以保护栅极102和侧墙103”顶部在后续的减薄刻蚀过程中不受到刻蚀损伤,还可以确保半导体衬底101表面的平坦,提高后续光刻和刻蚀工艺的精度。 Here, the antireflection layer 104 wrapped the gate 102 and the gate sidewall spacer 103 ', not only to protect the gate sidewall spacers 102 and 103' at the top without being damaged in the subsequent etching process of etching thinning, you can also ensure a semiconductor planar surface of the substrate 101 to improve the accuracy of the subsequent photolithography and etching process. 较佳的,在本实施例中,在涂覆过程中,确保所覆盖的抗反射层104的顶部趋于平坦。 Preferably, in the present embodiment, during the coating process, to ensure that the top antireflective layer 104 covered by the flattening.

[0039] 步骤S04:请参阅图8,在抗反射层104表面涂覆光刻胶105,采用光刻工艺,图案化光刻胶105,在光刻胶105中形成栅极侧墙103”要减薄区域的图案; [0039] Step S04: Refer to FIG. 8, the antireflection layer 104 in the surface coating of photoresist 105, using a photolithographic process, the patterned photoresist 105, gate sidewall spacers 103 are formed in the resist 105 'to thinning pattern region;

[0040] 这里,可以根据实际工艺要求来选择合适的光刻版,对光刻胶105进行曝光,在光刻胶105中形成曝光后的图案,光刻版中关键尺寸的大小可以尽量增大,从而使得光刻后的光刻胶105的宽度较大,足以遮挡住侧墙103”顶部,这样使得后续的图案化后的抗反射层104能够遮挡住侧墙103”的顶部区域,使其不会受到后续减薄工艺的损伤。 [0040] Here, to select the appropriate photomask according to the actual requirements of the process, the photoresist 105 is exposed, the pattern formed after exposure, the lithographic printing plate in the critical dimension size can be as large as possible in the photoresist 105 , so that the width of the photoresist 105 after photolithography so large enough to block the spacer 103 'at the top, such that the subsequent antireflective layer 104 after patterning spacer 103 can be obscured, "the top region, so that It will not damage the subsequent thinning process.

[0041] 步骤S05:请参阅图9,以图案化的光刻胶105为模版,采用干法刻蚀工艺,图案化抗反射层104,在抗反射层104中形成栅极侧墙103”要减薄区域的图案; [0041] Step S05: Refer to FIG. 9, the patterned photoresist 105 as a template, a dry etching process using the patterned antireflective layer 104, gate sidewall spacers 103 are formed in the anti-reflection layer 104 'to thinning pattern region;

[0042] 这里,可以但不限于采用等离子体干法刻蚀工艺,以上述图案化的光刻胶105为掩膜,刻蚀抗反射层104,从而暴露出栅极侧墙103”要减薄的区域。当然,图案化后的抗反射层104的具体宽度则可以根据实际工艺要求来设定,比如,图案化后的抗反射层也可以覆盖住栅极侧墙103”顶部的一部分,如图7中左边的栅极两边的虚线a与a'之间的宽度;也可以将栅极侧墙顶部全部覆盖住,如图7中右边的栅极两边的虚线b与b'之间的宽度;也可以将栅极侧墙103”恢复到增加宽度之前的栅极侧墙103的宽度等。本实施例中,采用将栅极侧墙103”的宽度恢复到栅极侧墙103的宽度作为覆盖在栅极侧墙103”顶部的图案化后的抗反射层104宽度。 [0042] Here, but not limited to a dry etching process using plasma, the above-described patterned photoresist 105 as a mask, etching the anti-reflective layer 104, thereby exposing the gate spacer 103 'to be thinned regions. of course, the specific width of the anti-reflective layer 104 after the patterning process can be set according to actual requirements, for example, anti-reflective layer after patterning part 103 may be "top gate spacer live coverage, such as both sides of the gate on the left in FIG. 7 and a broken line a 'width between; top gate sidewall spacer may be all covered, b and b on both sides of the gate in the right dashed line in FIG. 7' between the width ; gate spacers 103 may be "restored to the gate width to increase the width of the spacer 103 prior to the present embodiment, the gate spacer 103 employed." width to restore the width of the gate sidewall spacers 103 as in the antireflection layer 104 covers the width of the gate spacers 103 "patterned top.

[0043] 需要说明的是,本发明中,对于刻蚀过程中所采用的工艺参数可以根据实际工艺要求来设定。 [0043] Incidentally, the present invention, the process parameters employed during etching may be set according to the actual requirements of the process. 较佳的,在本实施例中,所采用的压强为5-10mTorr,所采用的上电极功率为300-500瓦,反应时间为10-80秒,与此相配合的下电极电压可以但不限于为100V。 Preferably, in the present embodiment, the pressure used was 5-10mTorr, the electrodes used on the power of 300-500 watts, the reaction time is 10 to 80 seconds, with this electrode voltage can be, but are not cooperating limited to 100V. 在刻蚀过程中,可以采用HBr和O2的混合气体作为刻蚀气体,HBr与O2的流量比例为1:1至15:2,较佳的比例为4:1。 During etching, a mixed gas of HBr and O2 may be used as an etching gas, HBr and O2 flow ratio of 1: 1 to 15: 2, preferably a ratio of 4: 1. 本实施例中,HBr的流量为10-30sccm,O2的流量为4-10sccm。 In this embodiment, the flow rate of HBr 10-30sccm, the flow rate of O2 4-10sccm.

[0044] 步骤S06:请参阅图10,以图案化的抗反射层104为掩膜,经干法刻蚀工艺,减薄栅极侧墙103” ; [0044] Step S06: Refer to FIG. 10, to pattern the antireflective layer 104 as a mask, by a dry etching process, the thinned gate spacer 103 ";

[0045] 具体的,在本实施例中的本步骤中,所说的干法刻蚀工艺可以但不限于为采用现有的SPT工艺进行栅极侧墙103”的减薄,从而得到减薄的栅极侧墙103'。由于本领域的普通技术人员可以知晓现有的栅极侧墙减薄工艺即SPT工艺的具体工艺过程,本发明对此不再赘述。如前所述,正是由于有抗反射膜覆盖在栅极102和栅极侧墙103”顶部,刻蚀气体不能够接触到栅极102和栅极侧墙103”顶部,从而避免了栅极侧墙103”顶部受到刻蚀损伤。 [0045] Specifically, in this step of the present embodiment, the said dry etching process may be thinned without limitation, gate sidewall spacers 103 "SPT employing conventional process to obtain thinned the gate spacer 103 '. Since one of ordinary skill in this art may be aware of a conventional gate sidewall spacer process i.e. particularly the thinning process SPT process, the present invention does not repeated. As described above, it is Since the anti-reflection film 103 covering the "top, the etching gas can not come into contact with the gate electrode 102 and the gate spacer 103 'at the top, thus avoiding the gate spacer 103 in the gate 102 and the gate sidewall spacer" top engraved by erosion. 同时,由于栅极侧墙103”顶部受到保护,可以不考虑栅极侧墙103”顶部的影响,自由控制侧墙水平方向的刻蚀过程,提升了栅极侧墙103”的减薄的效果。 Meanwhile, since the gate spacer 103 "top, are protected, the gate sidewall spacer 103 may not be considered" Influence top, sidewall freely control the etching process in the horizontal direction, to enhance the gate spacer 103 "effect thinned .

[0046] 需要说明的是,本发明中,对于刻蚀过程中所采用的工艺参数可以根据实际工艺要求来设定。 [0046] Incidentally, the present invention, the process parameters employed during etching may be set according to the actual requirements of the process. 在本实施例中,所采用的压强为20-40mTorr,所采用的上电极功率为500-800瓦,反应时间为10-40秒,所采用的下电极电压为O。 In the present embodiment, the pressure used was 20-40mTorr, the electrodes of the power employed was 500-800 watts, the reaction time of 10-40 seconds, electrode voltage employed is O. 在刻蚀过程中,所采用的刻蚀气体可以为氟系气体,本实施例中,采用的氟系气体为CH2F2和CHF3的混合气体。 During etching, the etching gas may be employed fluorine-containing gas, in the present embodiment, fluorine-based gas used was a mixed gas of CHF3 and CH2F2. CH2F2与CHF3的流量比例为1:1至4:1,较佳比例为2:1。 CH2F2 and CHF3 flow ratio of 1: 1 to 4: 1, preferably a ratio of 2: 1. 在本实施例中,CH2F2的流量为60-120sccm, CHF3的流量为30_60sccm。 In the present embodiment, the flow rate of CH2F2 60-120sccm, the flow rate of CHF3 30_60sccm.

[0047] 在本实施例中,在减薄所述栅极侧墙103”之后,还包括:采用等离子体干法刻蚀工艺去除剩余的光刻胶105和/或抗反射层104。这是由于实际工艺要求不同,在形成减薄的栅极侧墙103'之后,可能有光刻胶105和抗反射层104的残留,或只有抗反射层104的残留,因此,需要将其去除,以确保后续薄膜沉积工艺的质量。所采用的反应气体可以但不限于为纯O2或SO2等,本实施例中,采用纯O2作为反应气体,但这不用于限制本发明的范围。需要说明的是,去除光刻胶105和/或抗反射层104的干法刻蚀工艺过程的具体工艺参数可以根据实际工艺要求来设定,本实施例中,较佳的,所采用的反应压强为5-15mT0rr,上电极功率为500-1500瓦,下电极电压为零,气体流量为150-250sccm,反应时间为40-80秒。当然,去除的方法还可以为湿法腐蚀,湿法腐蚀所采用的具体工艺条件可以根 [0047] In the present embodiment, after the thinning of the gate sidewall spacer 103 ", further comprising: a plasma dry etch process to remove the remaining photoresist 105 and / or the antireflective layer 104. It is due to the different requirements of the actual process, after the formation of the thinned gate spacer 103 ', there may be residual anti-reflective layer 104 or antireflection layer 104 only remaining photoresist 105 and, therefore, needs to be removed to ensure the quality of the subsequent film deposition process. the reaction gases may be employed but are not limited to pure O2 or the like SO2, in the present embodiment, pure O2 as the reaction gas, but this is not intended to limit the scope of the invention. Incidentally , removal and / or the specific process parameters of the process of dry etching the antireflective layer 104. the photoresist 105 may be set according to the actual requirements of the process, in this embodiment, the preferred reaction pressure used is 5- 15mT0rr, the upper electrode 500 to 1500 watts of power, a lower electrode voltage is zero, the gas flow rate 150-250sccm, the reaction time is 40 to 80 seconds. of course, the method may also be removed by wet etching, wet etching employed root specific process conditions may 实际工艺要求来设定,本发明在此不作限制。 The actual setting process requirements, the present invention is not limited herein.

[0048] 步骤S07:请参阅图11,在半导体衬底101上沉积薄膜106。 [0048] Step S07: Refer to FIG. 11, a thin film 106 is deposited on the semiconductor substrate 101.

[0049] 具体的,在形成减薄的栅极侧墙103'之后,进行SMT或SAB制程,在SMT或SAB制程中沉积薄膜106,如图11中所示,薄膜106顶部的厚度与薄膜106底部的厚度近似相同,巧妙地消除了现有的在降低短沟道效应之后在薄膜沉积过程中出现的负载效应。 [0049] Specifically, in the 'thinned after forming the gate spacer 103, or SAB for SMT process, depositing a thin film or SAB 106 in SMT processes, as the thickness of the film, the top film 106 in FIG. 11 106 the thickness of the bottom is approximately the same, skillfully eliminated prior load effect occurs in the thin film deposition process after reducing short channel effects.

[0050] 综上所述,本发明的在降低短沟道效应后在薄膜沉积工艺中出现负载效应的消除方法,先采用增加栅极侧墙的宽度方法进行离子注入,来降低短沟道效应;然后,减小栅极侧墙的宽度,再进行薄膜沉积工艺。 [0050] In summary, the method of the present invention to eliminate the loading effect of reducing the short channel effect occurs in the thin film deposition process, the method of increasing the width of the first gate spacer using an ion implantation to reduce short channel effects ; then, the reduced width of the gate sidewall spacer, and then a thin film deposition process. 减小栅极侧墙宽度的方法:利用抗反射层保护住栅极和栅极侧墙的顶部,并利用图案化的抗反射层来定义栅极侧墙要减少的宽度,再采用干法刻蚀工艺刻蚀减薄栅极侧墙。 The method of reducing the gate width of the spacer: using a top anti-reflective layer protection live gate and the gate sidewall spacers, and using the patterned antireflective layer to define the width of the gate spacers to be reduced, then using a dry engraved etching process of etching the thinned gate spacers. 很明显,由于栅极侧墙的宽度减少了,栅极之间的填充空间就增加了,从而进一步提升栅极之间的薄膜填充能力,避免采用现有方法进行薄膜沉积时出现的负载效应。 Obviously, since the width of the gate sidewall spacer is reduced, filling the space between the gate electrode increases, thereby further enhancing the filling capacity of the thin film between the gate, to avoid loading effect that occurs when using conventional film deposition method.

[0051] 虽然本发明已以较佳实施例揭示如上,然所述实施例仅为了便于说明而举例而已,并非用以限定本发明,本领域的技术人员在不脱离本发明精神和范围的前提下可作若干的更动与润饰,本发明所主张的保护范围应以权利要求书所述为准。 [0051] While the present invention has been disclosed in the preferred embodiment as described above, then the described embodiments for illustrative purposes only and example only, not intended to limit the present invention, those skilled in the art without departing from the spirit and scope of the present invention may be made at a number of alterations and modifications, the scope of the present invention as claimed in the claims should prevail.

Claims (12)

1.一种在降低短沟道效应后所沉积的薄膜产生负载效应的消除方法,其特征在于,包括以下步骤: 步骤SOl:在半导体衬底上形成栅极和栅极侧墙; 步骤S02:增加所述栅极侧墙的宽度,并对所述半导体衬底进行源漏区离子注入; 步骤S03:在所述半导体衬底上覆盖一层抗反射层; 步骤S04:在所述抗反射层表面涂覆光刻胶,采用光刻工艺,图案化所述光刻胶,在所述光刻胶中形成所述栅极侧墙要减薄区域的图案; 步骤S05:以图案化的所述光刻胶为模版,采用干法刻蚀工艺,图案化所述抗反射层,在所述抗反射层中形成所述栅极侧墙要减薄区域的图案; 步骤S06:以图案化的所述抗反射层为掩膜,经干法刻蚀工艺,减薄所述栅极侧墙; 步骤S07:在所述半导体衬底上沉积薄膜。 1. A method of producing a thin film to reduce the short channel effect of the deposited loading effect of the cancellation method, characterized by comprising the following steps: Step SOl: forming a gate and a gate sidewall spacer on the semiconductor substrate; Step S02 is: increasing the width of the gate sidewall spacers, and said source and drain regions of the semiconductor substrate is ion-implanted; step S03: covered with anti-reflection layer on the semiconductor substrate; step S04: the antireflective layer the photoresist coated surface, using a photolithography process, patterning the photoresist, the gate sidewall spacer is formed to be thinned in the photoresist pattern area; step S05: to pattern the the photoresist as a template, using a dry etching process, patterning the antireflective layer, the gate sidewall spacer is formed to be thinned pattern area in the anti-reflective layer; step S06: the patterned said anti-reflective layer as a mask by dry etching process, thinning the gate sidewall spacer; step S07: depositing a thin film on the semiconductor substrate.
2.根据权利要求1所述的方法,其特征在于,所述步骤S04中,在减薄所述栅极侧墙之后,采用等离子体干法刻蚀工艺去除剩余的所述光刻胶和/或所述抗反射层。 2. The method according to claim 1, wherein said step S04, after thinning the gate sidewall spacer, plasma dry etch process to remove the remaining photoresist and the / or the anti-reflective layer.
3.根据权利要求2所述的方法,其特征在于,所述等离子体干法刻蚀工艺中利用纯O2或SO2作为反应气体。 3. The method according to claim 2, wherein said plasma dry etching process utilizing pure O2 or SO2 as a reaction gas.
4.根据权利要求2所述的方法,其特征在于,所述等离子体干法刻蚀工艺所采用的反应压强为5-15mTorr,上电极功率为500-1500瓦,下电极电压为零,气体流量为150-250sccm,反应时间为40-80秒。 4. The method according to claim 2, wherein the reaction pressure plasma dry etching process employed is 5-15mTorr, an upper electrode 500 to 1500 watts of power, a lower electrode voltage is zero, the gas flow 150-250sccm, the reaction time is 40 to 80 seconds.
5.根据权利要求1所述的方法,其特征在于,所述步骤S05中,采用HBr和O2的混合气体作为反应气体。 5. The method according to claim 1, wherein, in said step S05, a mixed gas of HBr and O2 as the reaction gas.
6.根据权利要求5所述的方法,其特征在于,所述步骤S05中,所述HBr与所述O2的流量比例为1:1至15:2。 6. The method according to claim 5, wherein, in said step S05, the flow ratio of the O2 HBr is 1: 1 to 15: 2.
7.根据权利要求1所述的方法,其特征在于,所述步骤S05中,所采用的反应压强为5-10mTorr,所采用的上电极功率为300-500瓦,反应时间为10-80秒。 7. The method according to claim 1, characterized in that the reaction pressure in the step S05, is employed 5-10mTorr, the electrodes of the power employed was 300-500 watts, the reaction time is 10 to 80 seconds .
8.根据权利要求1所述的方法,其特征在于,所述步骤S06中,采用氟系气体刻蚀所述栅极侧墙。 8. The method according to claim 1, wherein, in said step S06, the fluorine-based etching gas gate spacers.
9.根据权利要求8所述的方法,其特征在于,所述步骤S06中,所述氟系气体为CH2F2和CHF3的混合气体。 9. The method according to claim 8, wherein, in said step S06, the fluorine-based gas is a mixed gas of CHF3 and CH2F2.
10.根据权利要求9所述的方法,其特征在于,所述步骤S06中,所述CH2F2与所述CHF3的流量比例为1:1至4:1。 10. The method according to claim 9, wherein, in said step S06, the flow ratio of said CHF3 and CH2F2 is 1: 1 to 4: 1.
11.根据权利要求1所述的栅极侧墙减薄工艺,其特征在于,所述步骤S06中,所采用的反应压强为20-40mTorr,所采用的上电极功率为500-800瓦,所采用的下电极电压为0,反应时间为10-40秒。 11. The gate spacer thinning process according to claim 1, characterized in that the reaction pressure in the step S06, is employed 20-40mTorr, the electrodes of the power employed was 500-800 watts, the the electrode voltage used is 0, the reaction time of 10-40 seconds.
12.根据权利要求1所述的方法,其特征在于,所述步骤S07中,所述薄膜为应力记忆技术或硅化物阻止区制程中形成的。 12. The method according to claim 1, wherein, in said step S07, the thin film is formed to stress memorization technique or a silicide blocking region in the process.
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