CN112908859A - Method for manufacturing flash memory - Google Patents
Method for manufacturing flash memory Download PDFInfo
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- CN112908859A CN112908859A CN202110313042.0A CN202110313042A CN112908859A CN 112908859 A CN112908859 A CN 112908859A CN 202110313042 A CN202110313042 A CN 202110313042A CN 112908859 A CN112908859 A CN 112908859A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The invention provides a manufacturing method of a flash memory, which can increase the opening size of a second opening in a side wall material layer by reducing the thickness of the side wall material layer, thus increasing the process window of subsequent etching of the side wall material layer, exposing part of a control gate material layer after etching the side wall material layer to form the side wall layer, thereby avoiding the situation that the side wall layer blocks the subsequent etching control gate material layer, breaking the control gate material layer when the control gate material layer is subsequently etched, forming the control gate layer by utilizing the broken control gate material layer, and further solving the problem of control gate short circuit in the flash memory caused by the side wall layer blocking the etching control gate material layer.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a flash memory.
Background
In the current semiconductor industry, memory accounts for a significant proportion of the integrated circuit products, and flash memory in memory is particularly rapidly developing. It features that the stored information can be maintained for a long time without power-on, and has the advantages of high integration level, fast access speed and easy erasing, so it is widely used in microcomputer and automatic control.
Referring to fig. 1, which is a schematic cross-sectional view of a flash memory in the prior art, a manufacturing process of the flash memory is as follows: first, a semiconductor substrate 1 is provided, and a floating gate material layer 2, a control gate material layer 3, and a mask layer 4 are sequentially formed on the semiconductor substrate 1. Then, the mask layer 4 is etched to form an opening in the mask layer 4. And then, depositing a side wall material layer along the side wall and the bottom wall of the opening. And then, performing first etching to etch the side wall material layer in the opening to form a side wall layer 5. And then, performing second etching to etch the control gate material layer 3 in the opening to form a control gate layer. However, in the above steps, due to the size limitation of the flash memory device, the size of the opening in the mask layer 4 is small, and when the sidewall material layer is deposited along the sidewall and the bottom wall of the opening, the distance between the side wall material layers on the opposite side walls of the opening is smaller, so that an etching window is smaller when the first etching is performed subsequently, therefore, after the first etching is performed to form the sidewall layer, the sidewall layer still covers the control gate material layer 3 (the sidewall material layer with partial thickness remains on the surface of the control gate material layer 3), i.e. the control gate material layer 3 cannot be exposed in said opening, when the control gate material layer 3 is subsequently etched, the sidewall layer on the surface of the control gate material layer 3 will block the etching, thereby causing the control gate material layer 3 not to be cut, as shown by the dashed line 6 in fig. 1, the control gate material layer 3 cannot be broken, so that the problem of short circuit of the control gate in the flash memory formed later is caused.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory, which aims to solve the problem of control gate short circuit.
To solve the above technical problem, the present invention provides a method for manufacturing a flash memory, comprising:
providing a semiconductor substrate, wherein a control gate material layer and a mask layer are sequentially formed on the semiconductor substrate;
forming a first opening in the mask layer, wherein the control gate material layer is exposed out of the first opening;
filling a side wall material layer in the first opening, wherein the side wall material layer covers the side wall and the bottom wall of the first opening, and the side wall material layer filling the first opening is provided with a recess to define a second opening;
thinning the thickness of the side wall material layer to increase the opening size of the second opening;
etching the side wall material layer to further reduce the thickness of the side wall material layer, removing the side wall material layer positioned at the bottom of the first opening to form a side wall layer, and exposing part of the control gate material layer; and the number of the first and second groups,
and etching the exposed control gate material layer by taking the side wall layer as a mask so as to break the control gate material layer, and forming the control gate layer by utilizing the broken control gate material layer.
Optionally, in the method for manufacturing a flash memory, the material of the sidewall layer includes silicon oxide.
Optionally, in the manufacturing method of the flash memory, the method for reducing the thickness of the side wall material layer includes:
and removing part of the side wall material layer with the thickness by using a dry etching process so as to reduce the thickness of the side wall material layer.
Optionally, in the method for manufacturing the flash memory, when the thickness of the side wall material layer is reduced, the adopted etching gas is at least one of fluorine gas, argon gas, oxygen gas, sulfur dioxide, hydrogen bromide and carbon fluoride.
Optionally, in the method for manufacturing a flash memory, after filling a side wall material layer in the first opening and before thinning the thickness of the side wall material layer, the method further includes:
measuring the thickness of the side wall material layer;
and comparing the thickness of the side wall material layer with the target thickness.
Optionally, the method for etching the side wall material layer to form the side wall layer includes: comparing the thickness of the side wall material layer with the target thickness;
presetting etching time required for etching the side wall material layer according to the comparison result of the thickness of the side wall material layer and the target thickness and the thickness of the thinned side wall material layer;
and performing a wet etching process on the side wall material layer according to the preset etching time required by the side wall material layer until the side wall material layer positioned at the bottom of the first opening is removed, and reducing the thickness of the side wall material layer positioned on the side wall of the first opening to the target thickness to form the side wall layer and expose part of the control gate material layer, wherein the etching solution adopted by the wet etching process is a diluted hydrofluoric acid solution.
Optionally, in the method for manufacturing a flash memory, before forming the control gate material layer, the method for manufacturing a flash memory further includes:
forming a floating gate structure layer, wherein the floating gate structure layer covers the surface of the semiconductor substrate;
forming a shallow trench isolation structure, wherein the shallow trench isolation structure penetrates through the floating gate structure layer and extends into the semiconductor substrate; and the number of the first and second groups,
and forming a dielectric material layer, wherein the dielectric material layer covers the floating gate structure layer and the shallow trench isolation structure, and the control gate material layer covers the dielectric material layer.
Optionally, in the method for manufacturing a flash memory, a material of the dielectric material layer includes silicon oxide and/or silicon nitride.
Optionally, in the manufacturing method of the flash memory, a third opening is formed in the control gate layer, and the third opening is communicated with the second opening and exposes a part of the dielectric material layer;
and etching the exposed dielectric material layer to form a dielectric layer after etching the exposed control gate material layer, and etching the exposed dielectric material layer to form the dielectric layer.
Optionally, in the method for manufacturing a flash memory, the mask layer is made of silicon nitride and/or silicon oxynitride.
In the manufacturing method of the flash memory provided by the invention, the opening size of the second opening in the side wall material layer can be increased by reducing the thickness of the side wall material layer, so that a process window for subsequently etching the side wall material layer can be increased, and a part of the control gate material layer can be exposed after the side wall material layer is etched to form the side wall layer, thereby avoiding the situation that the side wall layer blocks the subsequent etching control gate material layer, so that the control gate material layer can be broken when the control gate material layer is subsequently etched, the control gate material layer is formed by utilizing the broken control gate material layer, and further solving the problem of control gate short circuit in the flash memory caused by the side wall layer blocking the etching control gate material layer.
Drawings
FIG. 1 is a schematic diagram of a prior art flash memory;
FIG. 2 is a flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the present invention;
fig. 3 to 8 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the invention;
fig. 9 is a schematic diagram illustrating a relationship between a pattern density and a thickness of a spacer material layer in a method for manufacturing a flash memory according to an embodiment of the present invention;
fig. 10 to 11 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the invention;
wherein the reference numerals are as follows:
1-a semiconductor substrate; 2-a floating gate structure; 3-a control gate material layer; 4-a mask layer; 5-side wall layer;
10-a semiconductor substrate; (ii) a
20-a floating gate structure;
30-a layer of dielectric material; 30 a-a dielectric layer;
31-a first oxide layer; 31 a-a first oxide layer;
a 32-nitride material layer; 32 a-a nitride layer;
33-a second layer of oxide material; 33 a-a second oxide layer;
40-a control gate material layer;
50-a mask layer; 50 a-a first opening;
60-side wall material layer; 60 a-side wall layer;
70-a second opening;
80-third opening.
Detailed Description
The following describes the method for manufacturing a flash memory according to the present invention in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the invention. As shown in fig. 2, the method for manufacturing the flash memory includes:
step S1: providing a semiconductor substrate, wherein a control gate material layer and a mask layer are sequentially formed on the semiconductor substrate;
step S2: forming a first opening in the mask layer, wherein the control gate material layer is exposed by the first opening;
step S3: filling a side wall material layer in the first opening, wherein the side wall material layer covers the side wall and the bottom wall of the first opening, and the side wall material layer filling the first opening is provided with a recess to define a second opening;
step S4: thinning the thickness of the side wall material layer to increase the opening size of the second opening;
step S5: etching the side wall material layer to further reduce the thickness of the side wall material layer, removing the side wall material layer positioned at the bottom of the first opening to form a side wall layer, and exposing part of the control gate material layer; and the number of the first and second groups,
step S6: and etching the exposed control gate material layer by taking the side wall layer as a mask so as to break the control gate material layer, and forming the control gate layer by utilizing the broken control gate material layer.
Next, the above steps will be described in more detail with reference to fig. 3 to 11. Fig. 3 to 8 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating a linear relationship between a pattern density and a thickness of a spacer material layer in a method for manufacturing a flash memory according to an embodiment of the present invention; fig. 10 to 11 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the invention.
First, step S1 is performed, referring to fig. 1, providing a semiconductor substrate 10. Specifically, the semiconductor substrate 10 may be silicon or silicon germanium with a single crystal, polycrystalline or amorphous structure, or may be a silicon-on-insulator SOI. In this embodiment, the semiconductor substrate 10 may be a silicon substrate, and an active region and a well structure located in the active region are formed through a doping process, such as an ion implantation process.
Next, a floating gate structure layer 20 is formed on the semiconductor substrate 10, wherein the floating gate structure layer 20 includes a floating gate oxide layer (GOX) and a floating gate layer (not shown) covering the floating gate oxide layer. The floating gate oxide layer is made of a material including, but not limited to, silicon dioxide, preferably silicon dioxide, which is beneficial to enhancing the interface adhesion between layers, and is used for separating the semiconductor substrate 10 from the floating gate layer. Further, the floating gate oxide layer (GOX) may be formed by Low Pressure Chemical Vapor Deposition (LPCVD), thermal oxidation, or molecular beam epitaxy, and the thickness thereof may be determined according to specific process requirements, and may be, for example, 90 angstroms to 100 angstroms.
In this embodiment, the floating gate layer may be made of undoped polysilicon, doped polysilicon doped with phosphorus, metal nanocrystals, silicon germanium nanocrystals, or other suitable conductive materials, and the floating gate layer may be formed by a deposition process, such as a chemical vapor deposition (cvd) process, and is used to form a Floating Gate (FG) that can trap or lose electrons, so that the finally formed flash memory has the functions of storage and erasure.
Next, referring to fig. 4, a shallow trench isolation structure (not shown) is formed, which penetrates through the floating gate structure layer 20 and extends into the semiconductor substrate 10 to define an active region for forming a memory cell in the semiconductor substrate 10.
Next, a dielectric material layer 30, a control gate material layer 40 and a mask layer 50 are sequentially formed, wherein the dielectric material layer 30 covers the shallow trench isolation structure and the floating gate structure layer 20, and the control gate material layer 40 covers the dielectric material layer 30. The material of the dielectric material layer 30 includes silicon oxide and/or silicon nitride, and in this embodiment, the dielectric material layer 30 may include a first oxide material layer 31, a nitride material layer 32, and a second oxide material layer 33, which are sequentially stacked. The dielectric material layer 30 is used for separating the floating gate structure layer 20 from the control gate material layer 40.
The control gate material layer 40 may be undoped polysilicon, doped polysilicon doped with phosphorus, etc., metal nanocrystals, silicon germanium nanocrystals, or other suitable conductive materials, and the control gate material layer 40 may be formed by a deposition process, such as a chemical vapor deposition process. The control gate material layer 40 is used for forming a control gate in the following, wherein the thickness of the control gate material layer 40 may be, for example, 500 angstroms to 600 angstroms.
The mask layer 50 covers the control gate material layer 40, and the material of the mask layer 50 may be silicon nitride and/or silicon oxynitride. Wherein, the thickness of the mask layer can be 2000-3300 angstroms.
Next, step S2 is performed, and referring to fig. 5, a first opening 50a is formed in the mask layer 50, wherein the first opening 50a exposes the control gate material layer 40. The specific method comprises the following steps: first, a patterned photoresist layer (not shown) is formed on the mask layer 50, wherein the patterned photoresist layer has a photoresist opening therein, and the photoresist opening exposes a portion of the mask layer 50. Next, the mask layer 50 is etched by a dry etching process to form a first opening 50a in the mask layer 50. And then, removing the patterned photoresist layer.
Then, the first opening 50a may be cleaned before depositing a sidewall material layer, so as to prevent the etching by-product remaining in the first opening 50a from affecting the deposition effect of the subsequent sidewall material layer.
Next, step S3 is executed, referring to fig. 6, a sidewall material layer 60 is filled in the first opening, the sidewall material layer 60 covers the sidewalls and the bottom wall (or the exposed control gate material layer) of the first opening 50a, and the sidewall material layer 60 filling the first opening has a recess to define a second opening 70. The material of the sidewall material layer 60 includes silicon oxide, and in other embodiments of the present invention, the material of the sidewall material layer 60 may include silicon nitride and silicon oxynitride. The thickness of the sidewall material layer 60 may be 1100 angstroms to 1300 angstroms, for example.
Further, the side wall material layer 60 may be formed by a low-pressure vapor deposition (LPCVD) process of tetraethyl orthosilicate (TEOS), and after the deposition of the side wall material layer 60, the deposition thickness of the side wall material layer 60 may be measured to ensure that the critical dimension error of the side wall material layer 60 filled in the first opening 50a meets the requirement. Optionally, after the side wall material layer 60 is formed, rapid annealing may be continuously performed on the device to improve the compactness of the side wall material layer 60. For example, the process temperature for depositing the sidewall material layer 60 may be 300 ℃ to 1000 ℃, the annealing temperature may be 500 ℃ to 1200 ℃, and the annealing time may be 20s to 110 s.
And then, measuring the thickness of the side wall material layer 60, wherein the thickness of the side wall material layer 60 can be measured by an Optical Critical Dimension (OCD) measurement method, and the method adopts an OCD measurement and analysis system to measure, or can be measured by a film thickness measuring machine. And comparing the thickness of the side wall material layer 60 with the target thickness, wherein the comparison result is used for presetting the etching time required when the side wall material layer is etched in the follow-up process.
Next, step S4 is executed, referring to fig. 7, to thin the thickness of the sidewall material layer 60, so as to increase the opening size of the second opening 70. Specifically, the sidewall material layer 60 with a partial thickness may be removed by using a dry etching process, that is, the sidewall material layer 60 with a partial thickness on the sidewall of the second opening 70 and the sidewall material layer 60 with a partial thickness at the bottom of the second opening 70 are removed, so as to reduce the thickness of the sidewall material layer 60, and further increase the width and depth of the second opening 50 a. The thickness of the sidewall material layer 60 may be reduced by, for example, 20 angstroms to 100 angstroms, for example, 20 angstroms, 50 angstroms or 100 angstroms, so as to increase a process window for subsequently etching the sidewall material layer 60.
In this embodiment, when the thickness of the sidewall material layer 60 is reduced, the adopted etching gas may be at least one of fluorine gas, argon gas, oxygen gas, sulfur dioxide, hydrogen bromide and carbon fluoride.
Next, step S5 is executed, referring to fig. 8, the sidewall material layer 60 is etched to further reduce the thickness of the sidewall material layer 60, and the sidewall material layer 60 located at the bottom of the first opening 50a is removed to form a sidewall layer 60a, and a portion of the control gate material layer 40 is exposed. Specifically, the method for etching the side wall material layer 60 to form the side wall layer 60a includes: firstly, according to the comparison result of the thickness of the side wall material layer and the target thickness, and the thickness of the thinned side wall material layer 60, presetting the etching time required for etching the side wall material layer 60, wherein the target thickness can be 900 angstroms to 1100 angstroms, for example. Then, according to the preset etching time required by the sidewall material layer 60, a wet etching process is performed on the sidewall material layer 60 until the sidewall material layer 60 located at the bottom of the second opening 70 is removed (i.e., the portion of the sidewall material layer covering the bottom wall of the first opening is removed), and the thickness of the sidewall material layer 60 located on the sidewall of the first opening is reduced to the target thickness, so as to form the sidewall layer 60a and expose a portion of the control gate material layer 40. In this way, the opening size of the second opening 70 may be further increased, and a portion of the control gate material layer 40 is exposed, that is, the sidewall spacer material layer 60 on the sidewall of the second opening is remained to form the sidewall spacer layer 60 a. Since the opening size of the second opening 50a is increased in step S4, when the wet etching process is performed on the sidewall material layer 60, the etching solution can fully penetrate into the sidewall material layer 60, so that the sidewall material layer 60 can be prevented from remaining at the bottom of the second opening 70, that is, the formed sidewall layer 60a can be exposed out of the control gate material layer 40, and the subsequent sidewall layer 60a is prevented from blocking the etching of the control gate material layer 40.
The etching solution adopted by the wet etching process is a diluted hydrofluoric acid solution (DHF), the etching time of the wet etching process is 30-150 s, for example, and the proportion of water and hydrofluoric acid in the diluted hydrofluoric acid solution can be 20: 1-100: 1.
Further, the pattern density (pattern density) of each memory cell in the flash memory is different, and when the sidewall material layer 60 is formed, the thickness of the sidewall material layer formed by the different pattern densities is different, so that the size of the corresponding second opening is also different, as shown in fig. 9, the pattern density and the thickness of the sidewall material layer form a linear relationship. Based on this, in this embodiment, the etching time required for etching the sidewall material layer 60 is preset by comparing the thickness of the sidewall material layer 60 with the target thickness, and according to the comparison result of the thickness of the sidewall material layer 60 with the target thickness, and the thickness of the thinned sidewall material layer 60. Therefore, according to the thickness of the side wall material layer corresponding to different pattern densities (pattern density), a proper etching process condition (such as etching time of an etching process) can be selected, and the etching amount (such as 50 angstroms or 100 angstroms) of different side wall material layers is selected according to the thickness of the side wall material layer corresponding to different pattern densities, so that the thickness of the finally formed side wall layer is reduced to a target thickness, and the size (FGSP CD) of the side wall layer of the platform can be stabilized and unified.
Next, referring to fig. 10, the exposed control gate material layer 40 is etched by using the sidewall layer 60a as a mask to divide the control gate material layer 40, and the divided control gate material layer 40 is used to form a control gate layer 40 a. Specifically, the control gate layer 40a has a third opening 80 therein, and the third opening 80 is communicated with the second opening 70 and exposes a portion of the dielectric material layer 30. Further, the exposed control gate material layer 40 may be etched by using a plasma dry etching process to form a third opening 80, and the control gate material layer 40 is cut by using the third opening 80, so as to form the control gate layer 40 a. In this step, since the sidewall layer 60a exposes a portion of the control gate material layer 40, so that a portion of the control gate material layer 40 can be exposed in the second opening 70, the control gate material layer 40 exposed by etching can be divided, and the divided control gate material layer 40 can be used to form the control gate layer 40a, thereby solving the problem of short circuit of the control gate in the flash memory caused by the sidewall layer 60a blocking the etching of the control gate material layer 40.
Further, referring to fig. 11, after etching the control gate material layer 40, the dielectric material layer 30 is also etched to form a dielectric layer 30 a. Specifically, the method for etching the dielectric material layer 30 includes: etching the second oxide material layer 33 by using a plasma dry etching process to form a second oxide layer 33 a; and etching the nitride material layer 32 to form a nitride layer 32 a; and etching the first oxide layer 31 to form a first oxide layer 31 a.
After step S6, word lines may be formed in the second opening 70 and the third opening 80, thereby completing the manufacture of the entire flash memory.
In summary, in the method for manufacturing a flash memory provided in the embodiment of the present invention, the size of the opening of the second opening in the sidewall material layer can be increased by reducing the thickness of the sidewall material layer, so that the process window for subsequently etching the sidewall material layer can be increased, and a part of the control gate material layer can be exposed after etching the sidewall material layer to form the sidewall layer, thereby preventing the sidewall layer from blocking the subsequent etching of the control gate material layer, so that the control gate material layer can be broken when the control gate material layer is subsequently etched, and the control gate layer is formed by using the broken control gate material layer, thereby solving the problem of control gate short circuit in the flash memory caused by the sidewall layer blocking the etching of the control gate material layer.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of manufacturing a flash memory, comprising:
providing a semiconductor substrate, wherein a control gate material layer and a mask layer are sequentially formed on the semiconductor substrate;
forming a first opening in the mask layer, wherein the control gate material layer is exposed out of the first opening;
filling a side wall material layer in the first opening, wherein the side wall material layer covers the side wall and the bottom wall of the first opening, and the side wall material layer filling the first opening is provided with a recess to define a second opening;
thinning the thickness of the side wall material layer to increase the opening size of the second opening;
etching the side wall material layer to further reduce the thickness of the side wall material layer, removing the side wall material layer positioned at the bottom of the first opening to form a side wall layer, and exposing part of the control gate material layer; and the number of the first and second groups,
and etching the exposed control gate material layer by taking the side wall layer as a mask so as to break the control gate material layer, and forming the control gate layer by utilizing the broken control gate material layer.
2. The method of claim 1, wherein the sidewall layer comprises silicon oxide.
3. The method for manufacturing the flash memory according to claim 1, wherein the method for thinning the thickness of the side wall material layer comprises:
and removing part of the side wall material layer with the thickness by using a dry etching process so as to reduce the thickness of the side wall material layer.
4. The method according to claim 3, wherein the etching gas used in the step of reducing the thickness of the spacer material layer is at least one of fluorine, argon, oxygen, sulfur dioxide, hydrogen bromide and carbon fluoride.
5. The method of claim 1, wherein after filling the first opening with a sidewall material layer and before thinning the thickness of the sidewall material layer, the method further comprises:
measuring the thickness of the side wall material layer;
and comparing the thickness of the side wall material layer with the target thickness.
6. The method of claim 5, wherein the step of etching the spacer material layer to form the spacer layer comprises:
presetting etching time required for etching the side wall material layer according to the comparison result of the thickness of the side wall material layer and the target thickness and the thickness of the thinned side wall material layer;
and performing a wet etching process on the side wall material layer according to the preset etching time required by the side wall material layer until the side wall material layer positioned at the bottom of the first opening is removed, and reducing the thickness of the side wall material layer positioned on the side wall of the first opening to the target thickness to form the side wall layer and expose part of the control gate material layer, wherein the etching solution adopted by the wet etching process is a diluted hydrofluoric acid solution.
7. The method of manufacturing a flash memory of claim 1, wherein before forming the control gate material layer, the method of manufacturing a flash memory further comprises:
forming a floating gate structure layer, wherein the floating gate structure layer covers the surface of the semiconductor substrate;
forming a shallow trench isolation structure, wherein the shallow trench isolation structure penetrates through the floating gate structure layer and extends into the semiconductor substrate; and the number of the first and second groups,
and forming a dielectric material layer, wherein the dielectric material layer covers the floating gate structure layer and the shallow trench isolation structure, and the control gate material layer covers the dielectric material layer.
8. The method of claim 7, wherein the material of the dielectric material layer comprises silicon oxide and/or silicon nitride.
9. The method of claim 8, wherein the control gate layer has a third opening therein, the third opening communicating with the second opening and exposing a portion of the dielectric material layer;
and etching the exposed dielectric material layer to form a dielectric layer after etching the exposed control gate material layer.
10. The method of claim 1, wherein the mask layer is made of silicon nitride and/or silicon oxynitride.
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