CN110310926A - Solve the method that sram cell device metal silicide defect is formed - Google Patents
Solve the method that sram cell device metal silicide defect is formed Download PDFInfo
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- CN110310926A CN110310926A CN201910551934.7A CN201910551934A CN110310926A CN 110310926 A CN110310926 A CN 110310926A CN 201910551934 A CN201910551934 A CN 201910551934A CN 110310926 A CN110310926 A CN 110310926A
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- 238000000034 method Methods 0.000 title claims abstract description 79
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 51
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 49
- 239000002184 metal Substances 0.000 title claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 48
- 230000007547 defect Effects 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 60
- 239000010703 silicon Substances 0.000 claims abstract description 60
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 46
- 150000004767 nitrides Chemical class 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 238000001459 lithography Methods 0.000 claims abstract description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 15
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- 230000007812 deficiency Effects 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000000452 restraining effect Effects 0.000 description 2
- -1 LDD ion Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000003607 modifier Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000306 recurrent effect Effects 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of methods that solution sram cell device metal silicide defect is formed, comprising: forms MOSFET structure；Form grid curb wall；Carry out source-drain electrode ion implanting；Using SMT process deposits buffer oxide layer and high stress silicon nitride layer and anneal；Remove high stress silicon nitride layer and buffer oxide layer；Remove side wall nitride silicon layer；Deposit SAB oxide layer；Grow SAB silicon nitride layer；SAB lithography and etching technique is carried out, forms new side wall nitride silicon layer, and new side wall nitride silicon layer is thinner than the side wall nitride silicon layer originally formed；Form metal silicide.The present invention first removes the side wall nitride silicon layer in grid curb wall, subsequent SAB layers of self-aligned silicide blocking of formation and etching technics is recycled to re-form the side wall nitride silicon layer of grid curb wall, interval between grid and grid increases, the process window when formation of subsequent metal silicide is considerably increased, solves the problems, such as to be difficult to form good metal silicide in device source drain region because of process window deficiency.
Description
Technical field
The present invention relates to microelectronics and semiconductor integrated circuit manufacturing fields, particularly belong to a kind of solution sram cell device
The method that metal silicide defect is formed.
Background technique
Static RAM (Static Random Access Memory, abbreviation SRAM) is as one in memory
Member has many advantages, such as that high speed, low-power consumption are mutually compatible with standard technology, is widely used in PC, personal communication, consumption electronic product
Fields such as (smart card, digital camera, multimedia players).One Static RAM generally includes multiple static randoms and deposits
Storage unit (abbreviation sram cell), multiple sram cell is arranged according to array.
Continuous miniature with semiconductor technology device critical dimensions, the complexity of CMOS manufacturing process is also increasingly
Height, correspondingly, process window are also more and more narrow.For logic process, the design rule in sram cell region is compared to patrolling
The design rule in volume region is stringenter, and restraining factors are also more, such as between the size of grid and active area, grid and grid
Distance and the distance between active area and active area etc., all can be by the restriction of design rule and technological ability.
SRAM is the cellular construction of high compaction, such as the sram cell device for the 6T that a memory space is 64Mbit
Part, the transistor contained in unit are as high as 304,008,000, and quantity is quite surprising.If guaranteeing sram cell
It works normally, just must assure that all transistor zero failures, this is all one non-to the stability of technique and the performance of device
Often big challenge.
Fig. 1 is the partial process view for manufacturing the prior art technology of sram cell, and Fig. 3 A to Fig. 3 G is shown in FIG. 1 existing
The schematic cross-section for the device that each step is formed in technique.In conjunction with shown in Fig. 1 and Fig. 3 A to Fig. 3 G, the system of sram cell device
It makes technique and specifically includes step as described below:
Step 1, a silicon substrate 101 is provided, the silicon substrate 101 divides for PMOS area and NMOS area, serves as a contrast in the silicon
It is formed on bottom 101 by shallow trench isolation, trap ion implanting, gate oxide growth, polysilicon deposition and etching, LDD ion implanting etc.
MOSFET (metal oxide semiconductor field effect tube) device architecture；
Specifically, gate oxide is covered on PMOS area and NMOS area, a polysilicon is deposited on gate oxide
Then layer (i.e. grid layer) techniques such as is exposed to gate oxide and polysilicon layer, etches, being respectively formed on PMOS area
Grid 102 and NMOS area on grid 102, as shown in Figure 3A；
Step 2, grid curb wall is formed；
In this step, as shown in Figure 3A, the deposited oxide layer first on grid, the then deposited silicon nitride in oxide layer
Layer, then using plasma etching technics etch perpendicular to the orientation in surface of silicon direction to silicon nitride layer again, shape
At side wall nitride silicon layer 103, removal is finally performed etching to oxide layer using hydrofluoric acid, forms the grid around the grid 102
Pole side wall；Wherein, side wall nitride silicon layer 103 forms the side wall around the grid 102 as oxide layer described in subsequent etching
The hard exposure mask of Shi Suoxu；
Step 3, source-drain electrode ion implanting (S/D IMP) is carried out；
In this step, ion implantation technology is carried out to PMOS area and NMOS area, as shown in Figure 3B, thus in PMOS
On region and corresponding source electrode and drain electrode (being not shown in Fig. 3 B) is respectively formed in NMOS area；
Step 4, slow using SMT (Stress Memorization Technology, stress memory technique) process deposits
Rush oxide layer and high stress silicon nitride layer；
In this step, as shown in Figure 3 C, (i.e. in the grid of formation, source electrode and leakage in PMOS area and NMOS area
On extremely) form buffer oxide layer 104 and high stress silicon nitride layer 105；
Step 5, as shown in Figure 3 C, high annealing is carried out, activation source and drain injects ion；
Step 6, as shown in Figure 3D, high stress silicon nitride layer 105 is removed first with phosphoric acid, recycles hydrofluoric acid removal buffering
Oxide layer 104；
Step 7, as shown in FIGURE 3 E, SAB (Salicide Block, self-aligned silicide stop) oxide layer 106 is deposited；
Step 8, as shown in FIGURE 3 E, SAB silicon nitride layer 107 is grown in SAB oxide layer 106 using CVD technique；
Step 9, SAB silicon nitride layer 107 and SAB oxide layer 106 are removed, as illustrated in Figure 3 F；
Step 10, metal silicide technology is carried out, forms self aligned metal silicide 108, as shown in Figure 3 G.
Due to the fluctuation of processing line (Process Flow), the size of grid (Poly gate) there will necessarily be certain
Error, this means that can be relatively small at the interval (spacing) in some regions between grid, causes metal silication in this way
The formation process window of object reduces.In addition, the interval too small between grid will also result in SAB silicon nitride in SAB etching technics
Layer etches away with being unable to fully, and forms silicon nitride residue, and then lead to the formation (Poor of source-drain area metal silicide defect
Formation), cause component failure.Since the interval too small between grid causes subsequent metal silicide to form defect, such as scheme
Shown in 2, there is defect in the dotted line frame of the left side for metal silicide, is that metal silicide is normal in the solid box of the right.
Summary of the invention
It is formed the technical problem to be solved in the present invention is to provide a kind of solution sram cell device metal silicide defect
Method, can solve the interval too small in the sram cell device of the prior art between some regions grid leads to metal silicide
The problem of formation process window is small and source-drain area metal silicide forms defect.
In order to solve the above technical problems, the side provided by the invention for solving sram cell device metal silicide defect and being formed
Method includes the following steps: suitable for the CMOS technology that technology node is 20nm~40nm
Step S1 forms MOSFET structure；
Step S2 forms grid curb wall, and the grid curb wall includes side wall nitride silicon layer and side wall oxide layer, and the side
Wall silicon nitride layer is located on the outside of the side wall oxide layer；
Step S3 carries out source-drain electrode ion implanting；
Step S4 using stress memory technique process deposits buffer oxide layer and high stress silicon nitride layer, and anneals；
Step S5 removes high stress silicon nitride layer and buffer oxide layer；
Step S6 removes side wall nitride silicon layer；
Step S7 deposits SAB oxide layer；
Step S8 grows SAB silicon nitride layer；
Step S9 carries out SAB lithography and etching technique, forms new side wall nitride silicon layer, and the new side wall nitride
Silicon layer thickness is less than the side wall nitride silicon layer thickness in step S2；
Step S10 forms metal silicide.
Further, in step s 6, side wall nitride silicon layer is removed using phosphoric acid.
Further, in step s 8, SAB silicon nitride layer is grown using boiler tube or atom layer deposition process.
Preferably, the SAB silicon nitride layer with a thickness of 120 angstroms~250 angstroms.
Further, in step s 4, the temperature of annealing is 1010 DEG C~1050 DEG C.
Further, in step s 5, high stress silicon nitride layer is removed using phosphoric acid, removes buffer oxide using hydrofluoric acid
Layer.
Further, in step s 9, the overlay area SAB is defined by lithography and etching using SAB light shield, non-SAB covers
The gate lateral wall of cover area forms grid curb wall.Wherein, the overlay area SAB include SAB resistance, Schottky diode,
The special areas such as LDMOS.
Further, in step s 2, the step of forming grid curb wall is as follows:
Step S21, the deposited oxide layer on the grid of MOSFET structure；
Step S22, the deposited silicon nitride layer in oxide layer；
Step S23, using plasma etching technics carry out the orientation perpendicular to surface of silicon direction to silicon nitride layer
Etching forms side wall nitride silicon layer；
Step S24 performs etching removal to oxide layer using hydrofluoric acid, forms the grid curb wall of all around gate.
Further, in step sl, a silicon substrate is provided, the silicon substrate is divided into PMOS area and NMOS area,
Grid is respectively formed on PMOS area and NMOS area.
Further, after step slo, contact hole is carried out, copper wiring technique forms complete device architecture.
Compared with prior art, it is recurrent can effectively to solve sram cell device in technical process for present invention proposition
Metal silicide forms the problem of defect, specifically, it is beneficial that:
First, the present invention is in MOSFET element structure by forming grid curb wall, carrying out source-drain electrode ion implanting, use
The side wall nitride silicon layer in grid curb wall is removed after SMT technique and high annealing, subsequent recycling SAB technique re-forms newly
Side wall nitride silicon layer, and new side wall nitride silicon layer is thinner than the side wall nitride silicon layer originally formed, by above-mentioned technique
Optimization, the interval in sram cell device between grid and grid increases, when considerably increasing the formation of subsequent metal silicide
Process window, solve since process window deficiency is difficult to form the difficulty of good metal silicide in device source drain region
Topic；
Second, the present invention replaces chemical vapor deposition in the prior art (CVD) using boiler tube or atomic layer deposition processes
SAB silicon nitride layer is formed, higher-quality silicon nitride layer can be obtained.
Detailed description of the invention
Fig. 1 is some processes flow chart of existing sram cell；
Fig. 2 is the effect contrast figure of the metal silicide formed in existing sram cell；
Fig. 3 A to Fig. 3 G is the schematic cross-section of the device of each step in technique shown in Fig. 1；
Fig. 4 A to Fig. 4 H is the schematic cross-section of the device of each step of the present invention；
Fig. 5 is process flow chart of the invention.
Specific embodiment
Sram cell device is a kind of cellular construction of highly dense, and design rule is stringenter, and restraining factors are also very
It is more.Due to the fluctuation of processing line, the size of grid there will necessarily be certain error, therefore in some regions between grid
It is spaced relatively small, the process window for resulting in being formed metal silicide in this way reduces.Meanwhile in SAB etching technics, grid
Between interval too small will also result in SAB silicon nitride layer and etch away with being unable to fully, form silicon nitride residue, and then lead to source and drain
The formation of area's metal silicide defect, causes component failure.
Based on the above issues, the method provided by the invention for solving sram cell device metal silicide defect and being formed, such as
Shown in Fig. 5, specifically comprise the following steps:
Step S1 forms MOSFET structure；
Step S2 forms grid curb wall, and the grid curb wall includes side wall nitride silicon layer and side wall oxide layer, and the side
Wall silicon nitride layer is located on the outside of the side wall oxide layer；
Step S3 carries out source-drain electrode ion implanting；
Step S4 using stress memory technique process deposits buffer oxide layer and high stress silicon nitride layer, and anneals；
Step S5 removes high stress silicon nitride layer and buffer oxide layer；
Step S6 removes side wall nitride silicon layer；
Step S7 deposits SAB oxide layer；
Step S8 grows SAB silicon nitride layer；
Step S9 carries out SAB lithography and etching technique, forms new side wall nitride silicon layer, and the new side wall nitride
Silicon layer thickness is less than the side wall nitride silicon layer thickness in step S2；
Step S10 forms metal silicide.
Below by way of particular specific embodiment and embodiments of the present invention are described with reference to the drawings, those skilled in the art
Further advantage and effect of the invention can be understood easily by content disclosed in the present specification.The present invention also can be by other
Different specific embodiments is implemented or is applied, and details in this specification can also be based on different perspectives and applications,
Without departing substantially from carrying out various modifier changes under spirit of the invention.
Fig. 5 is the method flow diagram for solving sram cell device metal silicide defect in the present invention and being formed.Fig. 4 A extremely schemes
4H is the schematic cross-section for the device that each step of the method for the present invention is formed.In conjunction with shown in Fig. 5, Fig. 4 A to Fig. 4 H, the present invention is provided
Solve sram cell device metal silicide defect formed method, suitable for technology node be 20nm~40nm CMOS work
In skill, specifically comprise the following steps:
Step S1 forms MOSFET structure.
As shown in Figure 4 A, in this step, a silicon substrate 101 is provided, the silicon substrate 101 divides for PMOS area and NMOS
Region passes through shallow trench isolation, trap ion implanting, gate oxide growth, polysilicon deposition and etching, LDD on the silicon substrate 101
Ion implanting etc. forms MOSFET (metal oxide semiconductor field effect tube) device architecture.
Specifically, gate oxide is covered on PMOS area and NMOS area, a polysilicon is deposited on gate oxide
Then layer (i.e. grid layer) techniques such as is exposed to gate oxide and polysilicon layer, etches, being respectively formed on PMOS area
Grid 102 and NMOS area on grid 102, as shown in Figure 4 A.
The material of the gate oxide is silica or the medium material with high dielectric constant for adulterating the elements such as nitrogen
Thermal oxidation method or chemical vapor deposition (CVD) method can be used in material, the forming method of the gate oxide.
Step S2 forms grid curb wall, and the grid curb wall includes side wall nitride silicon layer 103 and side wall oxide layer, and institute
Side wall nitride silicon layer 103 is stated to be located on the outside of the side wall oxide layer.
As shown in Figure 4 A, in this step, first in device surface deposited oxide layer, the then cvd nitride in oxide layer
Silicon layer, then using plasma etching technics etch perpendicular to the orientation in surface of silicon direction to silicon nitride layer again,
Side wall nitride silicon layer 103 is formed, removal is finally performed etching to oxide layer using hydrofluoric acid, is formed around the grid 102
Grid curb wall；Wherein, side wall nitride silicon layer 103 is formed as oxide layer described in subsequent etching around the side of the grid 102
Required hard exposure mask when wall.
Step S3 carries out source-drain electrode ion implanting as shown in Figure 4 B；Specifically, PMOS area and NMOS area are carried out
Ion implantation technology, in PMOS area and be respectively formed corresponding source electrode and drain electrode in NMOS area.
Step S4 is answered using stress memory technique (SMT) process deposits buffer oxide layer (Buffer Oxide) 104 and height
Power silicon nitride layer (High Tensile SiN) 105, and anneal, activation source-drain electrode injects ion, as shown in Figure 4 C, annealing
Temperature can be 1010 DEG C~1050 DEG C, but not limited to this.
Step S5 removes high stress silicon nitride layer 105 and buffer oxide layer 104 as shown in Figure 4 D.
In this step, high stress silicon nitride layer 105 is removed using phosphoric acid, then buffer oxide is removed using hydrofluoric acid clean
Layer 104.
Step S6, as shown in Figure 4 E, the side wall nitride silicon layer 103 removed in grid curb wall are specifically removed using phosphoric acid
The side wall nitride silicon layer 103.
Step S7 deposits SAB oxide layer 106, regrowth SAB silicon nitride layer 107.
In this step, SAB oxide layer is first formed using chemical breath (CVD) technique in the device surface that step S6 is formed
106, then use boiler tube (Furnace) or atomic layer deposition (ALD) technology generations in the prior art in SAB oxide layer 106
Chemical vapor deposition (CVD) forms the SAB silicon nitride layer 107 of high quality, and as illustrated in figure 4f, which compares step
The silicon nitride layer deposited in S2 is thin, for being subsequently formed new side wall nitride silicon layer 109.
Preferably, the SAB silicon nitride layer 107 with a thickness of 120 angstroms~250 angstroms, but not limited to this.
Step S8 carries out SAB lithography and etching technique, forms new side wall nitride silicon layer 109, and the new side wall nitrogen
The thickness of SiClx layer 109 is less than the thickness of the side wall nitride silicon layer 103 in step S2.
As shown in Figure 4 G, it is not necessarily to more large correction chart, using SAB mask layer, SAB covering is defined by lithography and etching technique
The special areas such as region, including SAB resistance, Schottky diode, LDMOS, the gate lateral wall of the non-overlay area SAB form described
New side wall nitride silicon layer 109.
Step S9 carries out metal silicide technology, forms self aligned metal silicide as shown at figure 4h.
Step S10 carries out contact hole, copper wiring technique forms complete device architecture.
In the prior art, the high stress silicon nitride layer 105 and buffer oxide layer 104 generally formed in removal SMT technique
Afterwards, self-aligned silicide is directly formed by CVD mode and stops SAB (Salicide Block) layer, then carried out SAB layers corresponding
Etching technics eventually forms metal silicide.
And in the present invention, after high stress silicon nitride layer 105 and buffer oxide layer 104 that removal SMT technique is formed, first
The side wall nitride silicon layer 103 in grid curb wall is removed, subsequent self-aligned silicide is recycled to stop SAB (Salicide
Block) formation of layer and etching technics re-form the side wall nitride silicon layer of grid curb wall, the side wall formed in this way
Side wall nitride silicon layer (the side wall nitride silicon layer in the grid curb wall the originally formed) thickness of silicon nitride layer than in the prior art
It is thinner, therefore the interval in sram cell device between grid and grid increases, and considerably increases subsequent metal silicide and is formed
When process window, solve and be difficult to form good metal silicide in device source drain region due to process window deficiency
Problem.
The present invention has been described in detail through specific embodiments, which is only of the invention preferable
Embodiment, the invention is not limited to above embodiment.Without departing from the principles of the present invention, those skilled in the art
The equivalent replacement and improvement that member makes, are regarded as in the technology scope that the present invention is protected.
Claims (13)
1. a kind of method for solving sram cell device metal silicide defect and being formed, which comprises the steps of:
Step S1 forms MOSFET structure；
Step S2 forms grid curb wall, and the grid curb wall includes side wall nitride silicon layer and side wall oxide layer, and the side wall nitrogen
SiClx layer is located on the outside of the side wall oxide layer；
Step S3 carries out source-drain electrode ion implanting；
Step S4 using stress memory technique process deposits buffer oxide layer and high stress silicon nitride layer, and anneals；
Step S5 removes high stress silicon nitride layer and buffer oxide layer；
Step S6 removes side wall nitride silicon layer；
Step S7 deposits SAB oxide layer；
Step S8 grows SAB silicon nitride layer；
Step S9 carries out SAB lithography and etching technique, forms new side wall nitride silicon layer, and the new side wall nitride silicon layer
Thickness is less than the side wall nitride silicon layer thickness in step S2；
Step S10 forms metal silicide.
2. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, which is characterized in that
In step s 6, side wall nitride silicon layer is removed using phosphoric acid.
3. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, which is characterized in that
In step s 8, SAB silicon nitride layer is grown using boiler tube or atom layer deposition process.
4. the method according to claim 3 for solving sram cell device metal silicide defect and being formed, which is characterized in that
The SAB silicon nitride layer with a thickness of 120 angstroms~250 angstroms.
5. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, which is characterized in that
In the step s 7, SAB oxide layer is grown using chemical vapor deposition process.
6. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, which is characterized in that
In step s 4, the temperature of annealing is 1010 DEG C~1050 DEG C.
7. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, which is characterized in that
In step s 5, high stress silicon nitride layer is removed using phosphoric acid, removes buffer oxide layer using hydrofluoric acid.
8. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, which is characterized in that
In step s 9, the overlay area SAB, the gate lateral wall shape of the non-overlay area SAB are defined by lithography and etching using SAB light shield
At grid curb wall.
9. the method according to claim 8 for solving sram cell device metal silicide defect and being formed, which is characterized in that
The overlay area SAB includes SAB resistance, Schottky diode, LDMOS.
10. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, feature exist
In in the CMOS technology that the method is 20nm~40nm for technology node.
11. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, feature exist
In, in step s 2, formed grid curb wall the step of it is as follows:
Step S21, the deposited oxide layer on the grid of MOSFET structure；
Step S22, the deposited silicon nitride layer in oxide layer；
Step S23, using plasma etching technics etch perpendicular to the orientation in surface of silicon direction to silicon nitride layer,
Form side wall nitride silicon layer；
Step S24 performs etching removal to oxide layer using hydrofluoric acid, forms the grid curb wall of all around gate.
12. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, feature exist
In in step sl, providing a silicon substrate, the silicon substrate is divided into PMOS area and NMOS area, in PMOS area and NMOS
Grid is respectively formed on region.
13. the method according to claim 1 for solving sram cell device metal silicide defect and being formed, feature exist
In after step slo, progress contact hole, copper wiring technique form complete device architecture.
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