CN113506720A - Method for improving flatness of wafer back surface - Google Patents
Method for improving flatness of wafer back surface Download PDFInfo
- Publication number
- CN113506720A CN113506720A CN202110685158.7A CN202110685158A CN113506720A CN 113506720 A CN113506720 A CN 113506720A CN 202110685158 A CN202110685158 A CN 202110685158A CN 113506720 A CN113506720 A CN 113506720A
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- wafer
- silicon nitride
- film layer
- nitride film
- wet etching
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 74
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 74
- 238000001039 wet etching Methods 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000002253 acid Substances 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 57
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 239000007788 liquid Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 abstract description 29
- 230000007547 defect Effects 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 13
- 238000001259 photo etching Methods 0.000 abstract description 6
- 238000001459 lithography Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 238000005406 washing Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
- H01L21/0209—Cleaning of wafer backside
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
Abstract
The invention discloses a method for improving the flatness of the back surface of a wafer, which comprises the following steps: growing a stress memory silicon nitride film layer on the front surface of the wafer with the second side wall; etching and removing the stress memory silicon nitride film layer and the silicon nitride film layer by a first method; and then removing the residual silicon nitride film layer on the back surface of the wafer through second wet etching. According to the invention, a cleaning process aiming at the back of the wafer is added after the acid tank cleaning process, so that the silicon nitride film layer on the back of the wafer which is not completely removed in the acid tank process can be completely removed, and after the silicon nitride film layer is removed, the etching effect of the cleaning solution on the Poly cannot be influenced due to the residual silicon nitride film layer in the cleaning step before the wafer enters the photoetching machine in the back-stage process, so that the thickness of the Poly is uniform, the flatness of the back of the wafer is improved, the Defocus defect is reduced or eliminated, and the yield is improved.
Description
Technical Field
The invention relates to the field of wafer manufacturing, in particular to a method for improving the flatness of the back surface of a wafer.
Background
The second sidewall (Space 2) of the wafer generally comprises a silicon nitride film layer and a silicon oxide film layer, which are mainly formed on the surface of the wafer on which the first sidewall (Space 1) is formed through deposition and etching processes, and fig. 1 shows a schematic cross-sectional structure diagram of the wafer with the Space 2. The silicon nitride film layer is generally prepared by a furnace process, so that the silicon nitride film layer is deposited on both the front surface and the back surface of the wafer.
Meanwhile, in order to improve the speed of the semiconductor device, a Stress Memory (SMT) silicon nitride film layer is deposited on the front surface of the wafer, the SMT silicon nitride film layer has tensile stress, then the stress is kept in a channel of the substrate through a rapid annealing process, and finally the SMT silicon nitride film layer is washed away through an acid tank process. In the process of washing off the SMT silicon nitride film layer by the acid tank process, because the front surface and the back surface of the wafer are simultaneously soaked in the cleaning solution, the cleaning solution can also clean the silicon nitride film layer on the back surface of the wafer together to expose the polysilicon gate film (Poly), but because the cleaning process is limited, the silicon nitride film layer on the back surface of the wafer cannot be completely removed, the silicon nitride film layer remains, particularly the residues on the edge position of the wafer are more obvious, and the remaining silicon nitride film layer can be kept to the later stage process; in the mill of preceding, back end of the line sharing lithography machine, back end wafer is before getting into the lithography machine, must wash the wafer back in order to reduce metal ion concentration to the safety range in, and in the cleaning process, the washing liquid also can the product etching effect to Poly, when having the remaining of silicon nitride thin layer on Poly, the washing liquid worsens to Poly's etching effect, consequently, the remaining thickness of no remaining Poly of silicon nitride thin layer and the remaining Poly of having the silicon nitride thin layer by the sculpture can produce the difference, leads to the whole roughness inhomogeneous of wafer back, especially silicon nitride thin layer remains serious border position department. After the photoetching process is carried out, the defect of pattern defocusing (Defocus) is easily caused by the abnormal flatness of the back surface of the wafer, so that the overall yield of the wafer is influenced. In order to reduce the influence caused by the abnormal flatness of the back surface of the wafer, in the cleaning step before the wafer enters the lithography machine, an attempt has been made to control the etching amount of the cleaning solution to Poly by diluting the concentration of the cleaning solution to achieve a method for improving the flatness, but the effect is not ideal, and after the cleaning solution is diluted, the effect of removing the metal ions is also poor, and even the concentration of the metal ions cannot be controlled within a standard range, so how to improve the flatness of the back surface of the wafer needs to be further explored.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for improving the back flatness of a wafer, which can realize the improvement of the back flatness of the wafer, further reduce or eliminate the Defocus defect and improve the yield of the wafer.
In order to solve the technical problem, the method for improving the flatness of the back surface of the wafer provided by the invention comprises the following steps:
step A, providing a wafer with a prepared second side wall, wherein a silicon nitride film layer grows on the outer side of a polycrystalline silicon grid electrode film layer on the back of the wafer;
step B, growing a stress memory silicon nitride film layer on the front surface of the wafer provided in the step A;
step C, performing first wet etching on the wafer processed in the step B to remove the stress memory silicon nitride film layer and the silicon nitride film layer;
and D, performing second wet etching on the back of the wafer processed in the step C to remove the residual silicon nitride film layer and etch the polysilicon gate electrode film layer.
Preferably, the second sidewall in step a includes a sidewall silicon nitride layer, and the sidewall silicon nitride layer is grown by a furnace tube process;
the silicon nitride film layer is grown in the process of the furnace tube.
Preferably, the thickness of the sidewall silicon nitride layer is
The thickness of the silicon nitride film layer is
Preferably, the stress memory silicon nitride film is prepared by a chemical vapor deposition process.
Preferably, the thickness of the stress memory silicon nitride film is
Preferably, the first wet etching adopts an acid tank wet etching process.
Preferably, the etching liquid adopted by the acid tank wet etching process is a phosphoric acid solution, and the etching time is 300 s.
Preferably, the second wet etching adopts a wafer back single-wafer wet etching process.
Preferably, the etching liquid adopted by the wafer back single-wafer wet etching process is hydrofluoric acid, and the etching time is 120 s.
Preferably, the thickness of the polysilicon gate thin film layer is
According to the invention, a cleaning process aiming at the back of the wafer is added after the acid tank cleaning process, so that the silicon nitride film layer on the back of the wafer which is not completely removed in the acid tank process can be completely removed, and after the silicon nitride film layer is removed, the etching effect of the cleaning solution on the Poly cannot be influenced due to the residual silicon nitride film layer in the cleaning step before the wafer enters the photoetching machine in the back-stage process, so that the thickness of the Poly is uniform, the flatness of the back of the wafer is improved, the Defocus defect is reduced or eliminated, and the yield is improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a wafer with Space 2;
FIG. 2 is a schematic flow chart illustrating a method for improving the flatness of the backside of a wafer according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a stress memory silicon nitride film grown on the front surface of a wafer with Space 2;
FIG. 4 is a schematic cross-sectional view of a wafer after a first etching;
FIG. 5 is a schematic cross-sectional view of the wafer after the second etching;
FIG. 6a is a scanned view of the backside of a wafer according to an embodiment of the present invention;
FIG. 6b is a scanned view of the backside of a wafer from the prior art;
FIG. 7a is a scanned view of Defect of a backside of a wafer according to an embodiment of the present invention;
fig. 7b is a scanned view of the defects of the back side of a wafer according to the prior art.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, a method for improving the flatness of the backside of a wafer of the present invention is shown, comprising the steps of:
step A, providing a wafer with a prepared second side wall, wherein a silicon nitride film layer grows on the outer side of a polycrystalline silicon grid electrode film layer on the back of the wafer;
step B, growing a stress memory silicon nitride film layer on the front surface of the wafer provided in the step A, wherein the cross-sectional structure schematic diagram of the wafer is shown in FIG. 3;
step C, performing first wet etching on the wafer processed in the step B to remove the stress memory silicon nitride film layer and the silicon nitride film layer, wherein the schematic cross-sectional structure of the wafer is shown in FIG. 4;
and D, performing second wet etching on the back of the wafer processed in the step C to remove the residual silicon nitride film layer and etch the polysilicon gate electrode film layer, wherein the schematic cross-sectional structure of the wafer is shown in FIG. 5.
In the embodiment of the invention, compared with the traditional process, a cleaning process is mainly added, namely the second wet etching in the step D, the newly added cleaning process is only carried out on the back surface of the wafer, the main purpose is to remove the silicon nitride film layer on the back surface of the wafer which is not completely cleaned in the step C, after the silicon nitride film layer is removed, the etching effect of the cleaning solution on the Poly is not influenced due to the residual silicon nitride film layer in the cleaning step before the wafer enters the photoetching machine in the later process, so that the thickness of the Poly is uniform, the flatness of the back surface of the wafer is improved, the Defocus defect is reduced or eliminated, and the yield is improved. Fig. 6a and 6b show scanned views of the back surface of a wafer, wherein fig. 6a shows the wafer obtained by the embodiment of the present invention, and fig. 6b shows the wafer obtained by the prior art, it can be seen that the edge position of the back surface of the wafer obtained by the prior art has a significant defect, as shown by the arrow position in fig. 6b, while the wafer obtained by the method of the embodiment of the present invention has no significant defect on the back surface; fig. 7a and 7b illustrate a comparison of lithography Defocus defects, where fig. 7a is a wafer obtained by the embodiment of the present invention, and fig. 7b is a wafer obtained by the prior art, it can be seen that a significant Defocus defect exists at an edge position of a back surface of the wafer obtained by the prior art, as shown in a front position in fig. 7b, whereas the wafer obtained by the method of the embodiment of the present invention has no significant Defocus defect at the back surface.
Preferably, the second sidewall in step a includes a sidewall silicon nitride layer, and the sidewall silicon nitride layer is grown by a furnace tube process;
the silicon nitride film layer is grown in the process of the furnace tube. Understandably, in the currently common furnace process, silicon nitride thin film layers are formed on both the front and back surfaces of the wafer.
Preferably, the thickness of the sidewall silicon nitride layer is
The thickness of the silicon nitride film layer is
Understandably, the thickness range meets the requirements of the subsequent process.
Preferably, the stress memory silicon nitride film is prepared by a chemical vapor deposition process.
Preferably, the thickness of the stress memory silicon nitride film is
Preferably, the first wet etching adopts an acid tank wet etching process.
Preferably, the etching liquid adopted by the acid tank wet etching process is a phosphoric acid solution, and the etching time is 300 s.
Preferably, the second wet etching adopts a wafer back single-wafer wet etching process.
Preferably, the etching liquid adopted by the wafer back single-wafer wet etching process is hydrofluoric acid, and the etching time is 120 s.
In the embodiment of the invention, the second wet etching is added on the back of the wafer, so that the silicon nitride film layer which cannot be completely removed by the first wet etching is removed again, the effect that the silicon nitride film layer on the back of the wafer is completely removed is achieved, after the silicon nitride film layer is removed, Poly is completely exposed, and the silicon nitride film layer can be uniformly etched by cleaning liquid in the cleaning step before the back-end process enters a photoetching machine, so that the thickness-controllable Ploy is obtained.
In the embodiment of the invention, the specific operation of the wafer back single-wafer wet etching process is as follows: the wafer after the first wet etching is placed in a Single wafer cleaning machine (Single Clean machine), and only the back of the wafer is cleaned with hydrofluoric acid as a cleaning agent for 120s, and fig. 6a and 7a show the cleaning effect. The second wet etching of the invention selects hydrofluoric acid as cleaning fluid with the best etching effect, and if the hydrofluoric acid is not selected, the etching effect is not good; the etching time is set to be 120s, the etching effect is optimal, if the etching time is less than 120s, the silicon nitride film layer is not completely removed, and if the etching time is more than 120s, the Poly layer is affected.
Preferably, the thickness of the polysilicon gate thin film layer is
Preferably, Poly has a thickness of
The subsequent process is more effective.
In summary, according to the invention, a cleaning process for the back surface of the wafer is added after the acid tank cleaning process, so that the silicon nitride thin film layer on the back surface of the wafer which is not completely removed in the acid tank process can be completely removed, and after the silicon nitride thin film layer is removed, the etching effect of the cleaning solution on the Poly cannot be influenced due to the residual silicon nitride thin film layer in the cleaning step before the wafer enters the photoetching machine in the back-stage process, so that the thickness of the Poly is uniform, the flatness of the back surface of the wafer is improved, the Defocus defect is reduced or eliminated, and the yield is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for improving the flatness of the backside of a wafer, the method comprising the steps of:
step A, providing a wafer with a prepared second side wall, wherein a silicon nitride film layer grows on the outer side of a polycrystalline silicon grid electrode film layer on the back of the wafer;
step B, growing a stress memory silicon nitride film layer on the front surface of the wafer provided in the step A;
step C, performing first wet etching on the wafer processed in the step B to remove the stress memory silicon nitride film layer and the silicon nitride film layer;
and D, performing second wet etching on the back of the wafer processed in the step C to remove the residual silicon nitride film layer.
2. The method according to claim 1, wherein the second sidewall in step a comprises a sidewall silicon nitride layer, the sidewall silicon nitride layer being grown by a furnace tube process;
the silicon nitride film layer is grown in the process of the furnace tube.
3. The method of claim 2, wherein the sidewall silicon nitride layer has a thickness of
The thickness of the silicon nitride film layer is
4. The method of claim 1, wherein the stress-memory silicon nitride film is formed by a chemical vapor deposition process.
5. The method of claim 4, wherein the stress-memory silicon nitride film has a thickness of
6. The method of claim 1, wherein the first wet etching is performed by an acid bath wet etching process.
7. The method for improving the flatness of the back surface of a wafer according to claim 6, wherein the etching liquid adopted by the acid bath wet etching process is a phosphoric acid solution, and the etching time is 300 s.
8. The method of claim 1, wherein the second wet etching is a single wafer back wet etching process.
9. The method according to claim 8, wherein the etching liquid used in the wafer back single-wafer wet etching process is hydrofluoric acid, and the etching time is 120 s.
10. The method of claim 1, wherein the polysilicon gate thin film layer has a thickness of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110685158.7A CN113506720B (en) | 2021-06-21 | Method for improving flatness of back surface of wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110685158.7A CN113506720B (en) | 2021-06-21 | Method for improving flatness of back surface of wafer |
Publications (2)
| Publication Number | Publication Date |
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| CN113506720A true CN113506720A (en) | 2021-10-15 |
| CN113506720B CN113506720B (en) | 2024-04-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113658854A (en) * | 2021-10-21 | 2021-11-16 | 绍兴中芯集成电路制造股份有限公司 | Photolithography method and method for manufacturing semiconductor device |
| CN113838746A (en) * | 2021-11-29 | 2021-12-24 | 西安奕斯伟材料科技有限公司 | Method for improving flatness of epitaxial wafer and epitaxial wafer |
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