KR0167252B1 - Method for forming isolation on a semiconductor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for isolating a device in a semiconductor integrated circuit. and; Isotropically etching the exposed substrate; Depositing a second silicon nitride film; Anisotropically etching the second silicon nitride film; Comprising the process of thermally oxidizing the isolation film to complete the device manufacturing, 1) the strength of the nitride film can be improved without sufficiently increasing the thickness of the silicon nitride film to suppress the growth of the long direction buzz beak of the narrow active pattern 2) the silicon substrate is etched by a lith plasma type chemical dry etching method to recess the isolation layer, thereby maintaining an isotropic, smooth recess profile and low damage silicon substrate. It is possible to improve the process reliability by reducing the possibility of improvement and the occurrence of crystal defects, and 3) the natural oxide film formed on the silicon substrate by depositing the second silicon nitride film in a thin thickness in the load-lock chamber. Not only minimize the growth of the nitride film but also completely oxidize the nitride film during the oxidation process. It is possible to minimize the stress of the substrate due to the second silicon nitride film and to suppress the growth of the buzz beak and improve the profile of the isolation film, thereby improving the electrical characteristics of the active device (e.g., junction leakage, threshold voltage characteristics). do.

Description

Device isolation method of semiconductor integrated circuit

1 is a plan view showing a buzz beak shape according to the oxidization phenomenon and pattern position in the diagonal active of the semiconductor device according to the prior art.

FIG. 2 is a cross-sectional view showing a buzz beak shape overgrown in the longitudinal direction of FIG.

3 (a) to 3 (c) are process flowcharts showing a method for isolating a nitride-clad-LOCOS (NCL) device of a semiconductor device according to the prior art.

4 (a) to 4 (c) are process flowcharts showing a poly-buffer-recessed locus device isolation method of a semiconductor device according to the prior art.

5 (a) to 5 (e) are process flowcharts showing the device isolation method of the semiconductor device according to the present invention.

6 is a graph showing changes in the oxidation thickness of a nitride film with temperature during wet oxidation in an H ₂ / O ₂ atmosphere.

* Explanation of symbols for main parts of the drawings

10 semiconductor substrate 12 pad oxide film

14 polysilicon 16 first silicon nitride film

18 photosensitive film pattern 20 second silicon nitride film

22: separator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for a semiconductor integrated circuit, and more particularly to a device isolation method for a semiconductor integrated circuit designed to be applicable to highly integrated semiconductor devices.

As the development of the electronics industry demands semiconductor chips for high-quality, multi-function, and high-capacity information processing, not only can they satisfy all the requirements at the same time, but also contribute to the improvement of chip productivity. Integration technology is widely used.

The most important technology that enables high integration in a general semiconductor metal-oxide-semiconductor (hereinafter referred to as MOS) device is a device isolation technology that electrically isolates a device from a device. This is the Locus method.

A typical technique of the LOCOS method is a simple stacked form of a pad oxide film that will act as a buffer for stress during oxidation on an active region defined in a silicon substrate, and a silicon nitride film for preventing oxidation of the active region, for example, Si. After forming a thin film of ₃ N ₄ / SiO ₂ structure and heat treatment to isolate the device.

The above technique has been used without any difficulty as a device isolation technology of a semiconductor having a minimum line width (minimum distance between an active pattern and an active pattern) of 1.0 μm (1 mega DRAM device), but has a minimum line width of less than 0.8 μm (4 mega DRAM device). The development of LOCOS methodology began with the development of devices with).

Therefore, more advanced LOCOS technology is being actively developed to improve the existing LOCOS method, which is expected to be used as a mass production technology of 256M DRAM level in the future.

However, device isolation mass production technology for semiconductor devices of 64M DRAM level or more has not yet been established.

This is because device isolation technology must satisfy the optimization requirements in terms of complex integration of the device, rather than simply minimizing the active and active spacing.

In other words, as the integration of the device, not only the distance between the active and the active is reduced, but also the feature size of the active itself is greatly reduced. Therefore, in all directions (width and length directions) of the active pattern Reduction of critical bird's beak and advantageous control of the buzz beak profile at the active edge are required.

Particularly, when the pattern width is 0.5 μm or less (64M DRAM-class active pattern) in the long direction active (active length direction), the oxidation is two-dimensional (2) as shown in the plan view shown in FIG. and the silicon nitride film e, which acts as an oxide mask, is activated by buzz beak growth activated by a in the long direction and b in the width direction with respect to the active pattern. When the thickness is thin, as can be seen in the cross-sectional view shown in FIG. 4, the mechanical strength of the nitride film is weakened due to the stress (c) between the nitride film and the substrate due to the expansion of the volume of the oxide film (d). As the lift-off occurs, the mask layer of the long pattern edge portion is excited, which causes the phenomenon of active buzz beak growth. Care should be sufficient.

In addition, when the distance between the active pattern and the active pattern is less than 0.5 μm, the geometric channel length of the parasitic field transistor that uses this spacer as a channel of the transistor is reduced, which causes a threshold voltage. Serious problems arise, such as a drop in voltage and punch through voltage.

Therefore, in order to improve the threshold voltage and the punch-through voltage of the field transistor, the thickness of the isolation layer must be increased to a predetermined thickness or more, but in this case, the opposite benefits, that is, the increase in the buzz beak length and the high surface topology after LOCOS ( Difficulty in applying photolithography in the pattern formation process according to the topology) is expected. Therefore, the development of device isolation technology should be conducted in the following directions to optimize the aforementioned problems.

That is, to reduce the buzz beak in all directions of the active pattern, increase the channel length of the geometric parasitic field transistor to satisfy the threshold voltage and the punch-through voltage of the field transistor, and improve the topology of the substrate surface after the device isolation process. Technology development should proceed.

Conventional techniques for reducing buzz bees include a polysilicon buffered LOCOS technique, which places a polysilicon layer between the pad oxide layer and the niche chemistry on the substrate, and a sidewall having the silicon nitride spacer on the silicon nitride pattern sidewalls on the pad oxide layer of the active substrate. Side wall spacer (LOCOS) technology, and the like to increase the channel length of the field transistor and to improve the surface topology of the substrate includes a field oxide recessed (LOCOS) technology.

However, these technologies still require a lot of improvement in terms of density.

Representative techniques recently introduced include a NCL (nitride-clad-LOCOS) device isolation process shown in FIG. 3, which is first used as a substrate (s) as shown in FIG. After the active pattern is formed on the pad oxide film 1 between the first silicon nitride film 5 and the substrate s, the silicon oxide film is undercut by dipping into the HF to form an undercut. After the cladding the pattern with the second silicon nitride film 5 ', as shown in FIG. 3, the nitride film of the portion where the isolation region 7 is to be formed, as shown in FIG. 5 ') is etched and wet oxidized at 1000 DEG C to form an isolation film 7 with a thickness of 5000 mV to complete device fabrication.

In other words, the process is performed by blocking the diffusion path of oxygen through the pad oxide film 1, or by increasing the mechanical strength of the nitride film 5 on the active pattern, the buzz beak due to the nitride film lift-off at the long edge of the active pattern. The device was manufactured in such a way as to inhibit the acceleration of growth.

On the other hand, another technique is the poly-buffer-recessed (PBR) LOCOS isolation process shown in FIG. 4, which increases the channel length of the field transistor and improves the surface topology of the separator. After etching the substrate in the field region and oxidizing the isolation layer to be recessed, the second nitride layer is coated on the sidewall of the etched substrate in order to solve the problem of the growth of the buzz beak caused by the substrate recess. In detail, it is as follows.

First, as shown in FIG. 4 (a), the pad oxide film 1 is grown on the substrate S in order to reduce the stress of the substrate, and then Si ₃ N ₄ (5) is used as the polysilicon 3 and the first nitride film. ) Is sequentially chemical vapor deposition (CVD), the nitride film (5), the polysilicon (3) and the pad oxide film (1) of the region where the isolation region will be formed are etched, and then the substrate (s) is 25-200 nm. Etch to the depth of.

Subsequently, the pad oxide layer 1 'is grown on both sidewalls of the active region and the isolation region of the substrate, and a second nitride layer 5' having a thickness of 250 Å is deposited, and the second nitride layer remains on the sidewall of the etched substrate. To form a pattern as shown in FIG. 4 (b). When the separator 7 is grown by heat treatment in this state, a pattern as shown in FIG. 4 (c) is obtained.

However, the device manufactured through the above process, which attempts to optimize the integration, also has the following problems.

In the case of the device fabricated through the NCL process, first, the nitride film thickness of the active region (for example, 1400 μs) is too thin to obtain the high mechanical strength of the nitride film at the long edge portion of the active pattern. -Off phenomenon is likely to occur, and secondly, since the oxide film f having a thickness of 55 밑에 is present under the second silicon nitride film, the diffusion through the oxide film cannot be blocked, so that the growth of the buzz beak cannot be effectively suppressed, and third, the substrate is recessed. It is difficult to obtain a high punch-through voltage because it is difficult to secure sufficient channel length of the field transistor mentioned above. Fourth, it is difficult to apply a photolithography process to form a pattern in a subsequent process because the topology of the substrate surface is poor after LOCOS. This is followed.

In addition, in the case of a device manufactured through the PBR LOCOS process, first, the etching of the substrate is vertical, and stress is concentrated on the corners during the oxidation process, so that crystal defects are likely to occur. Second, the pad oxide film under the second silicon nitride film ( It is difficult to control oxygen diffusion through the aforementioned oxide film because it is difficult to control the buzz beak. Third, since the thickness of the second silicon nitride film is along the thick and vertical side with 250 Å, the nitride film is oxidized after the oxidation process. It has the shape raised above, which makes the profile of the isolation film bad, which lowers the threshold voltage characteristics of the transistor. Fourth, when the oxide film is partially removed during the HF cleaning process after LOCOS due to the failure of the isolation film end face. The edge region of is likely to be exposed, reducing the reliability of the device.

Accordingly, the present invention has been made to solve the above problems, so as to optimize the process integration of semiconductor devices requiring 64M DRAM or more, that is, active width less than 0.4㎛ and active and active space below 0.5㎛ An object of the present invention is to provide a device isolation method for a semiconductor integrated circuit.

The device isolation method of the semiconductor integrated circuit according to the present invention for achieving the above object, the active pattern of the pad oxide film / polysilicon / first silicon nitride film structure in the active region of the semiconductor substrate so that the substrate surface of the device isolation region is exposed Forming a; Isotropically etching the exposed substrate; Depositing a second silicon nitride film; Anisotropically etching the second silicon nitride film; And thermally oxidizing the separator to grow the separator.

As a result of this process, the reliability of the semiconductor element can be improved.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The present invention relates to a severe bird's beak problem of the separator due to the two-dimensional oxidation of the long edge portion of the active pattern according to the narrow active width, and the field due to the decrease in the channel length caused by the narrow space between the active and the active. Degradation of threshold voltage and punch-through voltage of transistor, critical dimension variation of photoetching process after device isolation according to isolation topology and profile, threshold voltage change of active transistor, source / drain A locus-based device isolation method optimized to comprehensively improve a junction leakage problem and the like, and looks at some of the features introduced in the present invention.

First, in the present invention, 1) the oxidation masking layer (active mask) on the active layer instead of the conventional nitride film / oxide film (Si ₃ N ₄ / SiO ₂ ) structure of the nitride film / polysilicon / coral film (Si ₃ N ₄ / poly- The Si / SiO ₂ ) structure allows the mechanical strength to be increased without increasing the thickness of the silicon nitride film, and 2) the polysilicon of the sidewall of the mask layer having high mechanical strength to solve the weak buzz enchroachment in the narrow active long direction. The silicon was lateral recessed and then clamped with a thin silicon nitride film. 3) The substrate was smoothed by isotropic etching to improve the recess and profile of the field oxide. A very thin nitride film was used as sidewall passivation so that the silicon nitride film could be sufficiently oxidized during the thermal oxidation process. 4) Device isolation process due to introduction of polysilicon layer on the active substrate, isotropic etching of the substrate using chemical dry etching by the lime plasma method, and the adoption of a thin second silicon nitride film for protecting the sidewalls during the thermal oxidation process In addition to minimizing the stress generated during the process, the probability of occurrence of substrate crystal defects caused by stress is minimized.

A device isolation method of a semiconductor device having such a feature will be described in detail with reference to the process steps shown in FIGS. 5 (a) to 5 (e).

First, the general according to the semiconductor manufacturing process and form a well (well) on the silicon substrate 10, was on the surface grown by dry oxidation (dry O ₂₎ how the pad oxide film 12 of a 150Å thick at 900 ℃ fifth (a) forms a pattern as shown in FIG.

Subsequently, as shown in FIG. 5 (b), the polysilicon 14 having a thickness of 300 kPa and the 1400 kPa by low pressure chemical vapor deposition (hereinafter referred to as LPCVD) method on the pad oxide film 12 are described. A first silicon nitride film 16 having a thickness is deposited sequentially.

Next, as shown in FIG. 5 (c), a photoresist pattern 18 is formed on the first silicon nitride layer 16 to distinguish an active region and a device isolation region by using a photolithography process. Using the pattern 18 as a mask, the first silicon nitride film 16, the polysilicon 14, and the pad oxide film 12 are sequentially removed, and as shown in FIG. 5 (d), the silicon substrate in the device isolation region. To be exposed.

In this case, the first silicon nitride layer 16 is etched by reactive ion etching (hereinafter referred to as RIE) using a CHF ₃ / CF ₄ chemistry, and the polysilicon 14 is and it etched by RIE method using a HBr / Cl _2, the pad oxide film 12 is etched back by RIE using the CHr ₃ / CF ₄ chemistry solution.

Subsequently, as shown in FIG. 5 (e), the photoresist pattern 18 is immersed in an aqueous solution of H ₂ O ₂ / H ₂ SO ₄ , and then removed, and chemical dry etching is performed using a remove plasma method. The silicon substrate 10 exposed by the method or the wet etching method is isotropically etched to a thickness of 300-500 Å.

At this time, the exposed sidewalls of the polysilicon 14 between the first silicon nitride layer 16 and the thermal oxide layer 12 may be isotropically etched in the horizontal direction simultaneously with the substrate, but the etching may be performed by a lith plasma chemical dry etching method. In this case, the silicon substrate 10 is not subjected to any physical or chemical damage.

Subsequently, using the LPCVD apparatus (DJ-815V, KoKuSai CO.) Having a load-lock chamber as shown in FIG. , 80 GHz) thin second silicon nitride film 20 is deposited.

The deposition of the second silicon nitride film using the LPCVD apparatus having such a load-lock chamber is to minimize the growth of the native oxide film on the silicon substrate before the silicon nitride film deposition step.

Next, as shown in FIG. 5 (g), the second silicon nitride film is anisotropically etched by RIE using a CHF ₃ / CF ₂ chemical solution.

Thereafter, implantation of channel stop ions may be performed just before the thermal oxidation process by dividing the n well and p well regions, or may be performed after the isolation membrane has been completely grown. .

Next, as shown in FIG. 5 (h), a thermal oxidation process is performed at a temperature of 950 ° C. or higher for 35 minutes in an H ₂ / O ₂ atmosphere to grow a 4000 μm thick field oxide 22.

At this time, the second silicon nitride film 20 is oxidized very slowly at the sidewalls of the substrate and lowers the oxide growth rate to the sidewalls, and is completely oxidized while the isolation film having a thickness of 4000 Å is grown.

Therefore, when the thermal oxidation temperature is thick considering the thickness of the second silicon nitride film 20, the process should be performed at a relatively high temperature.

This is because the second silicon nitride film 20 should be sufficiently oxidized during thermal oxidation as can be seen in the graph shown in FIG.

Finally, as shown in FIG. 5 (e), the first silicon nitride film 16 is immersed in hot phosphoric acid (H ₃ PO ₄ ) and then removed, followed by the polysilicon 14 and the second silicon nitride film 20. This process is completed by removing the thermal oxide film 20 'formed by oxidation of. Subsequent processes proceed according to the general semiconductor manufacturing process.

As described above, according to the present invention, 1) the strength of the nitride film can be improved without sufficiently increasing the thickness of the silicon nitride film, so that the growth of the long direction buzz beak of the active pattern having a narrow width can be suppressed; The silicon substrate is etched by the dry plasma chemical dry etching method to recess to maintain an isotropic and smooth recess profile and a low damage silicon substrate, thereby improving the profile of the isolation layer and the possibility of crystal defects. 3) by depositing the second silicon nitride film in a thin thickness in the load-lock chamber, it is possible to minimize the growth of the natural oxide film on the silicon substrate and also during the oxidation process, The nitride film can be completely oxidized, and thus the substrate of the second silicon nitride film While minimizing the less it is possible to realize such improvement of the growth profile, suppressed and separation films of buzz beak is possible to improve the electrical characteristics of the active elements (for example, junction leakage, the threshold voltage characteristics).

Claims (11)

Forming an active pattern of a pad oxide film / polysilicon / first silicon nitride film structure in an active region of the semiconductor substrate so that the substrate surface of the device isolation region is exposed; Isotropically etching the exposed substrate; Depositing a second silicon nitride film; Anisotropically etching the second silicon nitride film; And thermally oxidizing the separator to grow the isolation layer. The method of claim 1, wherein the exposed substrate is etched by a chemical dry etching method or a wet etching method. 3. The method of claim 1 or 2, wherein the exposed substrate is etched to a depth of 300-500 microns. 2. The method of claim 1, wherein the active pattern is formed of a pad oxide film / amorphous silicon / first silicon nitride film structure. 2. The method of claim 1, wherein the second silicon nitride film is deposited using chemical vapor deposition equipment having a load-lock chamber. 2. The method of claim 1, wherein the second silicon nitride film is deposited to a thickness that can be 100% oxidized at the point where the growth of the separator of the desired thickness is completed. 7. The method of claim 1 or 6, wherein the second silicon nitride film is formed to a thickness of about 100 GPa or less. The device isolation method of claim 1, wherein the thermal oxidation process for forming a separator is performed at a temperature of 950 ° C. or higher. The method of claim 1, wherein the poly and silicon are isotropically etched together in an isotropic etching process of the exposed substrate. 2. The method of claim 1, wherein the second silicon nitride film is formed of a thermal oxide film during thermal oxidation. The method of claim 1, wherein the device isolation method of the semiconductor integrated circuit further comprises removing the first silicon nitride film, the polysilicon, and the thermal oxide film after the isolation layer is grown. Device isolation method.