CN113496949A - Method for improving electric leakage phenomenon after metal silicification layer is formed on surface of grid structure - Google Patents
Method for improving electric leakage phenomenon after metal silicification layer is formed on surface of grid structure Download PDFInfo
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- CN113496949A CN113496949A CN202010193262.XA CN202010193262A CN113496949A CN 113496949 A CN113496949 A CN 113496949A CN 202010193262 A CN202010193262 A CN 202010193262A CN 113496949 A CN113496949 A CN 113496949A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Abstract
The invention relates to a method for improving the electric leakage phenomenon after a metal silicification layer is formed on the surface of a grid structure, which comprises the steps of providing a first device area and a second device area; performing side wall etching on the first device region and the second device region; and forming a metal silicide layer on the surface of the first device region after the side wall is etched, and not forming the metal silicide layer on the surface of the second device region. The method of the invention cancels the SAB process, prevents the grooves caused by different etching rates in the SAB process, and avoids the existence of the grooves, so that no metal is remained in the grooves when the metal layer is formed at the later stage, thereby overcoming the problem of electric leakage of the device.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing processes, and particularly relates to a method for improving a current leakage phenomenon after a metal silicification layer is formed on the surface of a gate structure.
Background
In a semiconductor process in the prior art, as shown in fig. 1, after sidewall etching is performed on a first device region and a second device region, an SAB (self-aligned silicide block) is used for growing the first device region and the second device region, and then the SAB of the first device region is etched by using a photomask, and the SAB of the second device region is remained. A metal layer is then formed on the surfaces of the first device region and the second device region. Since the SAB of the first device region is etched, overetching is adopted to ensure that no silicon dioxide remains in an active (active) region. Due to the different etching rates of the thin dielectric (silicon dioxide) of the substrate and the silicon nitride sidewall, a groove is formed below the silicon nitride sidewall. When the metal layer grows, metal grows in the groove, and metal in the groove cannot be completely removed in the subsequent process, so that metal residues are caused, and electric leakage between devices is further caused.
Therefore, for the problem of metal residue, there is still a need for a method for improving the leakage phenomenon after forming a metal silicide layer on the surface of the gate structure.
Disclosure of Invention
In view of the above, it is necessary to provide a method for improving the leakage phenomenon after forming a metal silicide layer on the surface of a gate structure, the method comprising:
providing a first device region and a second device region;
performing side wall etching on the first device region and the second device region;
and forming a metal silicide layer on the surface of the first device region after the side wall is etched, and not forming the metal silicide layer on the surface of the second device region.
Further, the first device region and the second device region have the following structures before and after the side wall etching: forming a thin-layer dielectric on the substrate, the first device region and the second device region being formed on the thin-layer dielectric; the first device region includes a first stacked structure; the second device region includes a second stack structure.
Further, "forming a metal silicide layer on the surface of the first device region after the sidewall etching and not forming a metal silicide layer on the surface of the second device region" includes:
after the side wall is etched, forming metal layers on the surfaces of the first device area and the second device area;
etching the metal layer on the surface of the second device area by using the photomask; the pattern of the photomask is at least partially opened of the second stacking structure of the second device area.
Further, after etching the metal layer on the surface of the second device region using the mask, the method includes:
carrying out a thermal process on the metal layer to form a metal silicide layer;
and removing the metal layer without the metal silicide layer.
Further, in the "forming a metal silicide layer by performing a thermal process on the metal layer", a region where the metal silicide layer is formed is a first stacked structure surface of the first device region.
Further, the method used for "removing the metal layer where the metal silicide layer is not formed" is a wet etching method.
Further, the wet etching method uses an acid solution for etching.
Further, the first stacked structure and the second stacked structure are a gate structure.
Further, the metal of the metal layer is selected from any one of cobalt, tungsten, titanium, nickel and platinum, or an alloy formed by two or more of the cobalt, the tungsten, the titanium, the nickel and the platinum.
Further, "after forming a metal silicide layer on the surface of the first device region and not forming a metal silicide layer on the surface of the second device region after etching the sidewall", the method includes:
and forming a thin silicon nitride layer on the surfaces of the first device region and the second device region.
Further, the first device region and the second device region are formed on the same substrate, and a thin-layer dielectric is formed on the substrate; forming a first stacked structure on the thin-layer dielectric in the first device region; forming a second stack structure on the thin-layer dielectric in the second device region; forming an oxide layer (silicon dioxide layer) on at least part of the surfaces of the first stacked structure and the second stacked structure; forming silicon nitride side walls on the side walls of the first stacking structure and the second stacking structure outside the oxide layer; and forming a second silicon dioxide side wall on the outer side of the silicon nitride side wall.
Further, the thin dielectric layer is silicon dioxide.
Further, in the step of performing a thermal process on the metal layer to form the metal silicide layer, the thermal process is a rapid thermal process.
The invention has the following beneficial technical effects:
the method of the invention cancels the SAB process, prevents the grooves caused by different etching rates in the SAB process, and avoids the existence of the grooves, so that no metal is remained in the grooves when the metal layer is formed at the later stage, thereby overcoming the problem of electric leakage of the device.
The method of the invention cancels SAB process, reduces process steps and saves the time of the whole semiconductor process.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating a leakage phenomenon due to metal residues after a metal silicide layer is formed on a surface of a gate structure in the prior art; wherein, fig. 1(a) is a schematic diagram of the device after side wall etching; FIG. 1(b) is a schematic diagram of a device after SAB processing; FIG. 1(c) is a schematic diagram of the device after forming a cobalt metal layer and performing a thermal process; FIG. 1(d) is a schematic diagram after removing the cobalt metal layer.
FIG. 2 is a schematic structural diagram of a device in the prior art after side wall etching;
FIG. 3 is a process flow diagram of FIG. 1;
fig. 4 is a process flow diagram of a method for improving a leakage phenomenon after a metal silicide layer is formed on a surface of a gate structure according to an embodiment of the invention.
[ description of reference ]
1: a first device region; 11: a first stacked structure;
2: a second device region; 21: a second stacked structure;
3: a thin-layer dielectric;
112a, 112b oxide layers;
113a, 113 b: silicon nitride side walls;
114a, 114 b: a second silicon dioxide sidewall;
115a, 115 b: a gate electrode;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
As shown in fig. 2, the first device region 1 and the second device region 2 are formed on the same substrate, and a thin dielectric 3 is formed on the substrate, wherein the thin dielectric 3 is silicon dioxide; forming a first stacked structure 11 on the thin dielectric 3 in the first device region 1; forming a second stacked structure 21 on the thin-layer dielectric 3 in the second device region 2; forming oxide layers 112a, 112b (silicon dioxide layers) on at least a portion of the surfaces of the first stacked structure 11 and the second stacked structure 21; forming silicon nitride side walls 113a and 113b on the side walls of the first stacked structure 11 and the second stacked structure 21 outside the oxide layers 112a and 112 b; second silicon dioxide sidewalls 114a, 114b are formed on the outer sides of the silicon nitride sidewalls 113a, 113 b. The position defined by the dotted circle in fig. 2 is a position where a groove will be dug out below the silicon nitride sidewall during the etching process of the SAB. On top of the first stack 11 and the second stack 21 are gates 115a, 115b (polysilicon). The illustrated first stacked structure 11 includes, in order from top to bottom, a gate electrode 115a, an inter-gate dielectric layer, and a gate electrode; the second stacked structure 21 is shown as a gate 115b and a gate dielectric layer from top to bottom, and it should be noted that the illustration is only an example.
As shown in fig. 3 in the prior art, in step S101, sidewall etching is performed on a first device region 1 and a second device region 2 (an etched electron microscope image is shown in fig. 1 (a)); in step S102, a first device region 1 and a second device region 2 are grown using SAB (salicide block) so that the first device region 1 and the second device region 2 are both protected by the SAB; in step S103, etching the SAB of the first device region 1 by using a mask, and remaining the SAB of the second device region 2 (as shown in fig. 1 (b)); in step S104, a metal layer (Co layer) is then formed on the surfaces of the first device region 1 and the second device region 2; in step S105, after the metal layer is processed by the thermal process, a metal silicide layer is formed on the stack structure of the first device region 1 by the cobalt and the polysilicon (as shown in fig. 1 (c)); in step S106, the metal layer without the metal silicide layer is dissolved in an acid solution (typically sulfuric acid) (as shown in fig. 1 (d)); in step S107, a thin layer of silicon nitride is formed on the surfaces of the first device region 1 and the second device region 2.
Since the SAB of the first device region 1 is etched, an over-etch is used to ensure that no silicon dioxide remains in the active (active) region. Due to the different etching rates of the substrate thin-layer dielectric 3 (silicon dioxide) and the silicon nitride spacers 113a, a recess is formed under the silicon nitride spacers 113a (as shown by the dashed square in fig. 1(b) and the dashed circle in fig. 2). When the metal layer grows, metal grows in the groove (such as Co (cobalt) residue shown by a dotted line box in fig. 1 (c)), and the metal in the groove cannot be completely removed in the subsequent acid etching process, so that the metal residue (such as Co (cobalt) residue shown by an arrow in fig. 1 (d)) is caused, and electric leakage between devices is further caused.
The following examples of the present invention improve upon the above-described prior art process flow. The invention is also based on the device and the device region as shown in fig. 2.
The method for improving the leakage phenomenon after the metal silicide layer is formed on the surface of the gate structure as shown in fig. 4 comprises the following steps:
firstly, providing a first device region 1 and a second device region 2;
in step S201, performing sidewall etching on the first device region 1 and the second device region 2;
in step S202, after the sidewall etching, metal layers are formed on the surfaces of the first device region 1 and the second device region 2; and forming a metal layer by sputtering the metal layer on the surface of the device in an in-situ deposition mode.
In step S203, etching the metal layer on the surface of the second device region 2 by using the mask; the pattern of the mask is at least partially opened for the second stacked structure 21 of the second device region 2. The photomask is suitable for a lithography machine and comprises a substrate and a photomask pattern arranged on the substrate, wherein the photomask pattern is a light-transmitting area or a partial light-transmitting area on the substrate. The region outside the mask pattern is an opaque region on the substrate. The mask pattern has a profile that at least a portion of the second stack structure 21 of the second device region 2 is opened, and the mask pattern has a profile that at most a portion of the second device region 2 is entirely opened.
In step S204, performing a thermal process on the metal layer to form a metal silicide layer; preferably, the thermal process used is a rapid thermal process. Forming a metal silicide layer on the stacking structure of the first device region 1 by using the metal cobalt and the polysilicon; in the stacked structure in the second device region 2, since the metal cobalt layer has been etched away, the polysilicon of the second stacked structure 21 cannot form a metal silicide layer; therefore, after the sidewall etching, a metal silicide layer is formed on the surface of the first device region 1, and no metal silicide layer is formed on the surface of the second device region 2.
In step S205, the metal layer without the metal silicide layer is removed. Preferably, the metal layer is wet etched using sulfuric acid. Wherein, the wet etching method comprises the following steps of: 4: 20 NH4OH、H2O2And soaking in deionized water for 180 seconds and H in a volume ratio of 4:12SO4And H2O2Soaking for 600 seconds.
In step S205, a thin layer of silicon nitride is formed on the surfaces of the first device region 1 and the second device region 2.
In other embodiments, the metal of the metal layer is selected from any one of tungsten, titanium, nickel, platinum, or an alloy of two or more thereof.
Preferably, in step S202, the metal layer formed on the surface of the first device region 1 and the second device region 2 has a thickness of 120 angstroms.
The method for improving the leakage phenomenon after the metal silicide layer is formed on the surface of the grid structure is suitable for the common semiconductor manufacturing process. We provide different devices in the e-Flash area, but are not limited to e-Flash. For example, the entire device may be an embedded flash (e-flash); the first device region 1 may be a memory (memory) of a center region; the second device region 2 may be a logic element C logic of a surrounding region); the second stack structure 21 may be a gate structure of a logic element; the first stacked structure 11 may be a gate structure of a memory. The above are all examples, but are not intended to limit the present invention.
Compared with 7 steps in the prior art, the method omits the SAB growth and the etching process, so that the groove generated by over-etching the SAB does not exist, and the phenomenon of electric leakage caused by metal remaining in the groove does not exist.
Typically, the sidewall etch referred to above is typically a dry etch (plasma etch) commonly used in the art.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. Although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for improving the leakage phenomenon after forming a metal silicide layer on the surface of a gate structure is disclosed,
providing a first device region and a second device region;
performing side wall etching on the first device region and the second device region;
and forming a metal silicide layer on the surface of the first device region after the side wall is etched, and not forming the metal silicide layer on the surface of the second device region.
2. The method of claim 1, wherein a thin dielectric layer is formed on the substrate, and the first device region and the second device region are formed on the thin dielectric layer; the first device region includes a first stacked structure; the second device region includes a second stack structure.
3. The method according to claim 2, wherein the step of forming a metal silicide layer on the surface of the first device region and not forming a metal silicide layer on the surface of the second device region after the step of etching the sidewall comprises:
after the side wall is etched, forming metal layers on the surfaces of the first device area and the second device area;
etching the metal layer on the surface of the second device area by using the photomask; the pattern of the photomask is at least partially opened of the second stacking structure of the second device area.
4. The method of claim 3, wherein after the etching the metal layer on the surface of the second device region with the mask, the method comprises:
carrying out a thermal process on the metal layer to form a metal silicide layer;
and removing the metal layer without the metal silicide layer.
5. The method as claimed in claim 4, wherein in the step of forming the metal silicide layer by performing the thermal process on the metal layer, the region where the metal silicide layer is formed is a first stacked structure surface of the first device region.
6. The method as claimed in claim 4, wherein the step of removing the metal layer without forming the silicide layer is a wet etching process.
7. The method as claimed in claim 4, wherein the wet etching process is performed by using an acid solution.
8. The method as claimed in claim 2, wherein the first stacked structure and the second stacked structure are a gate structure.
9. The method as claimed in claim 4, wherein the metal of the metal layer is selected from any one of Co, W, Ti, Ni, and Pt, or an alloy of two or more thereof.
10. The method according to claim 1, wherein after the step of forming the metal silicide layer on the surface of the gate structure and the step of forming the metal silicide layer on the surface of the first device region after the step of etching the sidewall spacer and the step of not forming the metal silicide layer on the surface of the second device region, the method comprises:
and forming a thin silicon nitride layer on the surfaces of the first device region and the second device region.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115602542A (en) * | 2022-01-29 | 2023-01-13 | 和舰芯片制造（苏州）股份有限公司（Cn） | Manufacturing method of semiconductor SAB capable of preventing electric leakage and semiconductor device |
| CN116314234A (en) * | 2023-05-19 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and CMOS image sensor |
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| US20040099916A1 (en) * | 2002-11-21 | 2004-05-27 | Rotondaro Antonio L. P. | Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound |
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