KR100317491B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and to solve a problem due to a low coupling ratio between a floating gate and a control gate, a spacer polysilicon layer on inner and outer sidewalls of a polysilicon for floating gate. The method of manufacturing a flash memory device capable of maximizing the contact area between the floating gate and the control gate, thereby increasing the coupling ratio, and stably operating even at a low power supply voltage can be achieved.

Description

Method of manufacturing a flash memory device

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device for increasing a coupling ratio between a floating gate and a control gate.

In general, in the 0.25 탆 technology stack gate type flash memory device, the coupling ratio between the floating gate and the control gate during the cell formation process has a great effect on the bias of the control gate and the transistor implementation formed in the peripheral circuit region. give. Next, a method of manufacturing a conventional flash memory device will be described with reference to FIGS. 1 and 2.

1A and 1B are layout views illustrating a method of manufacturing a conventional flash memory device, and FIGS. 2A through 2C are diagrams A-A 'and BB' of FIG. 1 illustrating a method of manufacturing a conventional flash memory device. And CC 'section.

FIG. 2A is a cross-sectional view of the AA ′ portion of FIG. 1A, and forms a field oxide film 10 for inter-element insulation using an ISO mask M1 on a semiconductor substrate 11 having P-wells and N-wells formed thereon. . Thereafter, the tunnel oxide film 12 is formed on the entire structure, the first polysilicon layer 13 is formed, and then the first polysilicon layer 13 on the field oxide film 10 is formed using the poly1 mask M2. Remove

FIG. 2B is a cross-sectional view of the portion BB ′ of FIG. 1B, wherein the dielectric film 14, the second polysilicon layer 15, and the tungsten silicide layer 16 are formed on the entire structure in which the first polysilicon layer 12 pattern is formed. And the anti-reflection film 17 is sequentially formed. Then, the anti-reflection film 17, the tungsten silicide layer 16, the second polysilicon layer 15, the dielectric film 14, and the like are formed using the gate mask M3. The first polysilicon layer 13 is patterned. In this state, a cross-sectional view of the portion C-C 'of FIG.

The flash memory device manufactured in this manner cannot operate at low voltage because the area of the first polysilicon layer is small and has a small coupling ratio. In addition, the first polysilicon layer is not etched equally over the entire wafer, and there is a problem in that the uniformity of the cells is reduced due to the presence of a cell patterned with a narrow width.

Accordingly, the present invention provides a method of manufacturing a flash memory device capable of operating stably at low voltage by increasing the contact area of the floating gate polysilicon layer and the control gate polysilicon layer to have a large coupling ratio. There is this.

In the method of manufacturing a flash memory cell according to the present invention for achieving the above object, after forming a field oxide film on a semiconductor substrate on which a substructure is formed, a tunnel oxide film, a first polysilicon layer, and an oxide film are sequentially formed on the entire structure. Doing; Controlling the first polysilicon layer to remain on the field oxide film to form a stacked pattern of the first polysilicon layer and the oxide film; Removing the oxide film after forming a first spacer polysilicon layer on an outer wall of the stacked pattern of the first polysilicon layer and the oxide film; Forming a second spacer polysilicon layer on the inner sidewall of the stacked pattern of the first polysilicon layer and the oxide film, thereby forming a floating gate including the first polysilicon layer, the first and second spacer polysilicon; Forming a stacked pattern of a control gate and an anti-reflection film including a dielectric film, a second polysilicon layer, and a tungsten silicide layer on the floating gate; And forming a source and a drain region after performing the self-aligned source etching process.

1A and 1B are layout views illustrating a method of manufacturing a conventional flash memory device.

2A through 2C are cross-sectional views taken along the lines A-A ', B-B', and C-C 'of FIG. 1 to illustrate a method of manufacturing a conventional flash memory device.

3A and 3B are layout views illustrating a method of manufacturing a flash memory device according to the present invention.

4A through 4D are cross-sectional views taken along line D-D 'and E-E' of FIG. 3, illustrating a method of manufacturing a flash memory device according to the present invention.

5A and 5B are cross-sectional views taken along line F-F 'of FIG. 3B for explaining a method of manufacturing a flash memory device according to the present invention;

<Description of the symbols for the main parts of the drawings>

40: field oxide film 41: semiconductor substrate

42 tunnel oxide film 43a first polysilicon layer

43b: first spacer polysilicon layer 43c: second spacer polysilicon layer

43: floating gate 44: oxide film

45 dielectric film 46a polysilicon layer

46b: tungsten silicide layer 46: control gate

47: antireflection film M10: ISO mask

M20: Floating Gate Mask M30: Dielectric Film Mask

M40: Gate Mask M50: SAS Mask

The present invention forms a spacer polysilicon layer on both sides of the polysilicon pattern for floating gate to maximize the area in contact with the control gate, thereby increasing the coupling ratio.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3A and 3B are layout views illustrating a method of manufacturing a flash memory device according to the present invention, and FIGS. 4A to 4D are views illustrating a manufacturing method of a flash memory device according to the present invention. And FIG. 5A and FIG. 5B are cross-sectional views of the FF 'portion of FIG. 3B for explaining a method of manufacturing a flash memory device according to the present invention.

FIG. 4A is a cross-sectional view of the portion DD ′ of FIG. 3A. Referring to FIG. 3A, a field for inter-element insulation using an ISO mask M10 on a semiconductor substrate 41 on which P-wells and N-wells are formed is shown. An oxide film 40 is formed. Thereafter, the tunnel oxide film 42 is formed on the entire structure, and the first polysilicon layer 43a and the oxide film 44 are formed. Thereafter, the oxide film 44 and the first polysilicon layer 43a of the exposed portion are removed using the floating gate mask M20. Here, the first polysilicon layer 43a is formed to have a sheet resistance of 600 kPa and is formed to a thickness of 800 kPa, and is formed to have a thickness of 700 kPa of the oxide film 44. After the etching process using the floating gate mask M20, the first polysilicon layer 43a having 150 Å is left on the field oxide film 40. The first polysilicon layer 43a remaining on the field oxide film 40 serves to protect the field oxide film 40 during a subsequent process of removing the oxide film 44. Thereafter, a high concentration ion implantation process using As or the like is performed so that the sheet resistance of the exposed first polysilicon layer 43a on the field oxide film 40 is about 100 kPa. As the first polysilicon layer 43a on the field oxide layer 40 has a low sheet resistance, the first polysilicon layer 43a may be rapidly etched in a subsequent etching process.

Referring to FIG. 4B, after depositing polysilicon on the entire structure, a spacer etching process is performed, and the oxide layer 44 on the first polysilicon layer 43a is removed to form an outer wall of the first polysilicon layer 43a. The first spacer polysilicon layer 43b is formed on the substrate. Here, the polysilicon layer for forming the first spacer polysilicon layer is formed to have a thickness of 1000 GPa with a sheet resistance of 300 GPa.

Referring to FIG. 4C, after the polysilicon is deposited on the entire structure, a spacer etching process is performed to form the second spacer polysilicon layer 43c on the inner wall of the first polysilicon layer 43a. During the spacer etching process, the low-resistance first polysilicon layer 43a remaining on the field oxide film 40 is removed. The polysilicon layer for forming the second spacer polysilicon layer 43c is formed to have a thickness of 1000 GPa with a resistance of 300 GPa. Here, the sheet resistance of the first polysilicon layer 43a is about 600 kPa, which is larger than the sheet resistance of 300 kPa of the first and second spacer polysilicon layers 43b and 43c, which is later used as a secondary polysilicon layer for floating gate. This is to remove easily with a fast etching rate by using the resistance difference.

FIG. 4D is a cross-sectional view of the EE ′ portion of FIG. 3B and described with reference to FIG. 3B. The first polysilicon layer 43a, the first spacer polysilicon layer 43b, and the second spacer polysilicon layer 43c are illustrated in FIG. The dielectric film 45 is formed on the floating gate 43 formed. Thereafter, the dielectric film formed in the peripheral circuit region is removed by an etching process using the dielectric film mask M30. At this time, the thick floating gate polysilicon layer 31 (the upper ends of the first and second spacer polysilicon layers) in the cell region is simultaneously removed. Subsequently, the control gate polysilicon layer 46a, the tungsten silicide layer 46b, and the antireflection film 47 are sequentially formed on the entire structure, and the antireflection film 47 is formed by an etching process using the gate mask M40. The tungsten silicide layer 46b, the control silicon polysilicon layer 46a, the dielectric film 45 and the floating gate 43 are sequentially etched. As a result, a stack gate in which the floating gate and the control gate (polysilicon layer / tungsten silicide layer) 46 are stacked is formed. In the etching process using the gate mask M40, the region in which the dielectric film 45 is removed is a portion 31 in which the floating gate 43 is etched more than half, and a portion in which the floating gate 43 is etched (active region). And field oxide film regions. The floating silicon polysilicon layer in the portion where the other dielectric film 45 is not removed is not removed. Then, the remaining polysilicon layer for floating gate is removed by using a self-aligned etching (SAE) mask in which all cell regions are open. At this time, a slight loss occurs in the semiconductor substrate 41 of the portion where the floating gate polysilicon layer is removed, but since the junction is formed, the channel region of the cell is not affected. In this state, a cross-sectional view of the portion F-F 'of FIG. 3B is illustrated in FIG. 5A.

Referring to FIG. 5B, a self-aligned source etching process is performed using a self-aligned source mask M50. At this time, the floating silicon polysilicon layer 32 which is not completely removed during the self-aligned etching (SAE) process is completely removed.

As such, the present invention can maximize the contact area between the floating gate and the control gate by forming a spacer polysilicon layer on the inner and outer sidewalls of the polysilicon for floating gate.

As described above, the present invention can increase the coupling ratio of the cell by maximizing the contact area between the floating gate and the control gate, so that it can operate stably even at low voltage and advantageously implement transistors in the peripheral circuit area. . Accordingly, the area and the process steps of the peripheral circuit transistor can be reduced. In addition, the uniformity of the cell can be increased, thereby increasing the design window.

Claims (9)

Forming a field oxide film on the semiconductor substrate on which the substructure is formed, and sequentially forming a tunnel oxide film, a first polysilicon layer, and an oxide film on the entire structure; Controlling the first polysilicon layer to remain on the field oxide film to form a stacked pattern of the first polysilicon layer and the oxide film; Removing the oxide film after forming a first spacer polysilicon layer on an outer wall of the stacked pattern of the first polysilicon layer and the oxide film; Forming a second spacer polysilicon layer on the inner sidewall of the stacked pattern of the first polysilicon layer and the oxide film, thereby forming a floating gate including the first polysilicon layer, the first and second spacer polysilicon; Forming a stacked pattern of a control gate and an anti-reflection film including a dielectric film, a second polysilicon layer, and a tungsten silicide layer on the floating gate; And And forming a source and a drain region after performing a self-aligned source etching process. The method of claim 1, And the first polysilicon layer has a sheet resistance of 600 kW, and is formed to a thickness of 800 kW. The method of claim 1, And the oxide film is formed to a thickness of 700 kHz. The method of claim 1, And a first polysilicon layer remaining on the field oxide layer serves as an etch barrier layer of the field oxide layer during a subsequent oxide removal process. The method of claim 1, A high concentration ion implantation process is performed so that the sheet resistance of the polysilicon layer remaining on said field oxide film is about 100 kPa. The method of claim 1. The polysilicon layer for forming the first spacer polysilicon layer is formed to have a sheet resistance of 300 Ω with a thickness of 1000 Å, the manufacturing method of the flash memory device. The method of claim 1, The first polysilicon layer remaining on the field oxide layer is removed during the spacer etching process for forming the second spacer polysilicon layer. The method of claim 1, The polysilicon layer for forming the second spacer polysilicon layer is formed to a thickness of 1000 하여 to have a resistance of 300 kHz, the manufacturing method of the flash memory device. The method of claim 1, And completely removing the remaining polysilicon layers of the first and second spacer polysilicon layers when etching the dielectric film formed in the peripheral circuit area.