US20060220075A1 - Methods of fabricating self-aligned source of flash memory device - Google Patents
Methods of fabricating self-aligned source of flash memory device Download PDFInfo
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- US20060220075A1 US20060220075A1 US11/446,064 US44606406A US2006220075A1 US 20060220075 A1 US20060220075 A1 US 20060220075A1 US 44606406 A US44606406 A US 44606406A US 2006220075 A1 US2006220075 A1 US 2006220075A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present disclosure relates to semiconductor devices and, more particularly, to methods of fabricating semiconductor devices.
- a flash memory device includes a source connection layer that connects the sources of unit cells to form a source line.
- a metal contact method includes forming a contact in the sources of unit cell(s) and connecting the contacts.
- this method is inappropriate for highly integrated devices because a contact margin needs to be provided.
- a source line of an impurity diffusion layer has been employed.
- the source line of an impurity diffusion layer is formed by means of a self-aligned source (SAS) process.
- SAS self-aligned source
- Korean Publication Patent No. 2003-49450 discloses a method for smoothly applying a cell source ion implantation process by compensating damage of a photoresist pattern for the formation of a source line using a SAS etching process.
- Korean Publication Patent No. 2001-104910 provides a method for preventing the substrate silicon of active regions from being damaged by etching a field oxide layer after the formation of a polysilicon layer for a floating gate.
- U.S. Pat. No. 5,955,759 to Ismail et al. discloses a method for making a field effect transistor.
- the method by the Ismail et al. patent comprises forming raised source/drain contacts self-aligned to preexisting junction regions and then forming the gate dielectric and a self-aligned metal or metal/polysilicon gate which may be T-shaped in order to reduce the parasitic gate resistance.
- U.S. Pat. No. 5,552,331 to Hsu et al. discloses a method for forming spacers with different width along with a gate to protect gate-edges and adjacent source regions during an etching process for the formation of a self-aligned source.
- FIGS. 1 a through 1 c illustrate, in cross-sectional views, the process of forming a source line of a flash memory device according to a conventional method.
- a device isolation layer (not shown) is formed on a semiconductor substrate 11 .
- the device isolation layer defines a field region and an active region.
- a tunnel oxide layer 12 is formed in the active region of the substrate 11 .
- a stack gate structure is formed on the tunnel oxide layer 12 .
- the stack gate structure comprises a floating gate 13 , a dielectric layer 14 , and a control gate 15 .
- the control gate 15 generally has a multi-layer structure comprising a polysilicon and a metal material selected from a group consisting of WSix, W, CoSix, TiSix, etc.
- a photoresist pattern 16 is formed over the stack gate structure.
- the photoresist pattern is formed by means of a SAS mask process and defines a source line region.
- a device isolation layer (not shown) in the source line region is removed by means of a SAS etching process. As a result, the semiconductor substrate 11 in the source line region is completely exposed. After the completion of the SAS etching process, a baking process is performed. Through the SAS etching and the baking processes, the photoresist pattern 16 becomes thin and hardened.
- a cell source ion implantation process is performed using the thin and hardened photoresist pattern 17 as a mask.
- a source line 18 in which impurity ions are implanted is formed in the source line region of the semiconductor substrate 11 .
- FIGS. 1 a through 1 c illustrate, in cross-sectional views, the process of forming a source line of a flash memory device according to a conventional method
- FIGS. 2 a through 2 d illustrate, in cross-sectional views, the results of an example disclosed semiconductor fabricating process.
- an oxide layer 22 is formed on a substrate including a device isolation layer 21 .
- a first conducting layer 23 for a floating gate, a dielectric layer 24 , and a second conducting layer 25 for a control gate are formed in sequence over the oxide layer 22 . Some part of the first conducting layer 23 , the dielectric layer 24 , and the second conducting layer 25 are removed to form the floating and control gates.
- the oxide layer 22 has an appropriate thickness to ensure the characteristics of a transistor required for a cell array region or a peripheral circuit region.
- the thickness of the oxide layer 22 may vary depending on whether the peripheral region is a high-voltage region or a low-voltage region.
- the first conducting layer 23 for the floating gate may be formed of polysilicon.
- the polysilicon may be undoped or doped polysilicon.
- the doped polysilicon may be formed by the process of depositing a polysilicon layer and, then, implanting ions such as As or P or doping P through a POCl 3 process.
- the dielectric layer 24 is an insulating layer with a high dielectric constant and a high breakdown voltage.
- the dielectric layer 24 may be an oxide-nitride-oxide (ONO) layer.
- the second conducting layer 25 may be a doped polysilicon layer.
- a metal material may be deposited on the second conducting layer 25 for the control gate to form a suicide layer on the control gate. This is to reduce word line resistance according to the high-integration of a device.
- a mask pattern 26 for the formation of a self-aligned source (SAS) is formed over the substrate including the gates.
- an SAS etching process is performed to remove the device isolation layer exposed in a source line region between the gates. As a result, the surface of the substrate 11 in the source line region is completely exposed.
- the device isolation layer is preferably removed by means of a dry etching process employing a top power between 800 W and 1500 W and a bottom power between 800 W and 1300 W under a pressure between 100 mTorr and 130 mTorr.
- the used etching gases are C 4 F 8 between 3 standard cubic centimeter per minute (sccm) and 5 sccm, CHF3 between 2 sccm and 6 sccm, O2 between 1 sccm and 5 sccm, and Ar between 100 sccm and 300 sccm.
- an ion implantation process 28 is performed using the mask pattern 26 as an etching mask. As a result, a source line in which ions are implanted is formed in the semiconductor substrate.
- the dry etching employs plasma and, therefore, both sides of the gate may be damaged by ions in the plasma.
- both sides of the gate may be damaged by ions.
- a chemical dry etching process is performed after the ion implantation process.
- the chemical dry etching prevents ions from entering into a reaction chamber and allows reaction only by radicals.
- the damaged parts formed during the etching of the substrate can be removed and, therefore, the characteristics of an insulating layer in the following process can be enhanced.
- the chemical dry etching may be an isotropic etching.
- the chemical dry etching is performed by applying microwave power between 300W and 500W under a pressure between 200 mTorr and 250 mTorr.
- the used etching gases are CF 4 between 200 sccm and 280 sccm and O 2 between 40 sccm and 80 sccm.
- the chemical dry etching is performed by applying microwave power of 400 w under a pressure of 225 mTorr.
- CF 4 of 240 sccm and O 2 of 60 sccm are used as etching gases.
- the chemical dry etching can reduce damage and defects of silicon by eliminating damage by ions, thereby preventing the unordinary growth of an insulating layer in the following process and improving the electrical characteristics of a device.
- the insulating layer is preferably BPSG (boron phosphorus silicate glass) layer.
- the disclosed process removes the damage in silicon lattices due to the etching and the ion implantation processes and enhances the characteristics of an insulating layer by means of the chemical dry etching. Therefore, during the operation of a flash memory device, the loss of electrons can be prevented and the electrical characteristics of a device can be improved.
- example methods of fabricating a semiconductor device ensure the uniform thickness of an oxide layer and improve electrical characteristics of a device by employing a damage removal etching process to eliminate damage due to an etching and an ion implantation.
- One example disclosed method may include depositing an oxide layer, a first conducting layer for floating gate, a dielectric layer, and a second conducting layer for control gate in sequence on a semiconductor substrate including a device isolation layer; forming gates by removing some part of the oxide layer, the first conducting layer, the dielectric layer, and the second conducting layer; and forming a mask pattern for a self-aligned source over the substrate including the gates.
- the example method may also include removing the device isolation layer exposed between the gates; performing an ion implantation process; and eliminating damage generated during the ion implantation process or the removal process of the device isolation layer.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Example methods of fabricating semiconductor devices are disclosed. One example method may include depositing an oxide layer, a first conducting layer for a floating gate, a dielectric layer, and a second conducting layer for a control gate in sequence on a semiconductor substrate including a device isolation layer; forming gates by removing some parts of the oxide layer, the first conducting layer, the dielectric layer, and the second conducting layer; forming a mask pattern for a self-aligned source over the substrate including the gates; removing the device isolation layer exposed between the gates; performing an ion implantation process; and eliminating damage generated during the ion implantation process or the removal of the device isolation layer.
Description
- The present disclosure relates to semiconductor devices and, more particularly, to methods of fabricating semiconductor devices.
- Generally, a flash memory device includes a source connection layer that connects the sources of unit cells to form a source line. As a conventional method for forming the source connection layer, a metal contact method includes forming a contact in the sources of unit cell(s) and connecting the contacts. However, this method is inappropriate for highly integrated devices because a contact margin needs to be provided. To implement the high-integration of a device, recently, a source line of an impurity diffusion layer has been employed. The source line of an impurity diffusion layer is formed by means of a self-aligned source (SAS) process.
- For example, Korean Publication Patent No. 2003-49450 discloses a method for smoothly applying a cell source ion implantation process by compensating damage of a photoresist pattern for the formation of a source line using a SAS etching process. Korean Publication Patent No. 2001-104910 provides a method for preventing the substrate silicon of active regions from being damaged by etching a field oxide layer after the formation of a polysilicon layer for a floating gate.
- As other examples, U.S. Pat. No. 5,955,759 to Ismail et al. discloses a method for making a field effect transistor. The method by the Ismail et al. patent comprises forming raised source/drain contacts self-aligned to preexisting junction regions and then forming the gate dielectric and a self-aligned metal or metal/polysilicon gate which may be T-shaped in order to reduce the parasitic gate resistance. U.S. Pat. No. 5,552,331 to Hsu et al. discloses a method for forming spacers with different width along with a gate to protect gate-edges and adjacent source regions during an etching process for the formation of a self-aligned source.
-
FIGS. 1 a through 1 c illustrate, in cross-sectional views, the process of forming a source line of a flash memory device according to a conventional method. - Referring to
FIG. 1 a, a device isolation layer (not shown) is formed on asemiconductor substrate 11. The device isolation layer defines a field region and an active region. Atunnel oxide layer 12 is formed in the active region of thesubstrate 11. A stack gate structure is formed on thetunnel oxide layer 12. The stack gate structure comprises afloating gate 13, adielectric layer 14, and acontrol gate 15. To reduce word line resistance according to high-integration of device, thecontrol gate 15 generally has a multi-layer structure comprising a polysilicon and a metal material selected from a group consisting of WSix, W, CoSix, TiSix, etc. Next, aphotoresist pattern 16 is formed over the stack gate structure. The photoresist pattern is formed by means of a SAS mask process and defines a source line region. - Referring to
FIG. 1 b, a device isolation layer (not shown) in the source line region is removed by means of a SAS etching process. As a result, thesemiconductor substrate 11 in the source line region is completely exposed. After the completion of the SAS etching process, a baking process is performed. Through the SAS etching and the baking processes, thephotoresist pattern 16 becomes thin and hardened. - Referring to
FIG. 1 c, a cell source ion implantation process is performed using the thin and hardenedphotoresist pattern 17 as a mask. As a result, asource line 18 in which impurity ions are implanted is formed in the source line region of thesemiconductor substrate 11. - However, such conventional technology may cause defects in silicon lattices due to the etching and the ion implantation for the formation of source and drain and, therefore, the thickness of the oxide layer on either side of the gate may not become uniform.
-
FIGS. 1 a through 1 c illustrate, in cross-sectional views, the process of forming a source line of a flash memory device according to a conventional method; and -
FIGS. 2 a through 2 d illustrate, in cross-sectional views, the results of an example disclosed semiconductor fabricating process. - Referring to
FIG. 2 a, anoxide layer 22 is formed on a substrate including adevice isolation layer 21. A first conductinglayer 23 for a floating gate, adielectric layer 24, and a second conductinglayer 25 for a control gate are formed in sequence over theoxide layer 22. Some part of the first conductinglayer 23, thedielectric layer 24, and the second conductinglayer 25 are removed to form the floating and control gates. - Here, the
oxide layer 22 has an appropriate thickness to ensure the characteristics of a transistor required for a cell array region or a peripheral circuit region. The thickness of theoxide layer 22 may vary depending on whether the peripheral region is a high-voltage region or a low-voltage region. The first conductinglayer 23 for the floating gate may be formed of polysilicon. The polysilicon may be undoped or doped polysilicon. The doped polysilicon may be formed by the process of depositing a polysilicon layer and, then, implanting ions such as As or P or doping P through a POCl3 process. Thedielectric layer 24 is an insulating layer with a high dielectric constant and a high breakdown voltage. Thedielectric layer 24 may be an oxide-nitride-oxide (ONO) layer. The second conductinglayer 25 may be a doped polysilicon layer. - In another example, a metal material may be deposited on the second conducting
layer 25 for the control gate to form a suicide layer on the control gate. This is to reduce word line resistance according to the high-integration of a device. - Referring to
FIG. 2 b, amask pattern 26 for the formation of a self-aligned source (SAS) is formed over the substrate including the gates. - Referring to
FIG. 2 c, after the formation of themask pattern 26, an SAS etching process is performed to remove the device isolation layer exposed in a source line region between the gates. As a result, the surface of thesubstrate 11 in the source line region is completely exposed. The device isolation layer is preferably removed by means of a dry etching process employing a top power between 800 W and 1500 W and a bottom power between 800 W and 1300 W under a pressure between 100 mTorr and 130 mTorr. Here, the used etching gases are C4F8 between 3 standard cubic centimeter per minute (sccm) and 5 sccm, CHF3 between 2 sccm and 6 sccm, O2 between 1 sccm and 5 sccm, and Ar between 100 sccm and 300 sccm. - Referring to
FIG. 2 d, after the SAS etching process, anion implantation process 28 is performed using themask pattern 26 as an etching mask. As a result, a source line in which ions are implanted is formed in the semiconductor substrate. - However, during the removal process of the device isolation layer, the dry etching employs plasma and, therefore, both sides of the gate may be damaged by ions in the plasma. In addition, during the ion implantation, both sides of the gate may be damaged by ions. To remove such damaged parts, a chemical dry etching process is performed after the ion implantation process. By employing remote plasma, the chemical dry etching prevents ions from entering into a reaction chamber and allows reaction only by radicals. Through the chemical dry etching, the damaged parts formed during the etching of the substrate can be removed and, therefore, the characteristics of an insulating layer in the following process can be enhanced.
- The chemical dry etching may be an isotropic etching. According to one example, the chemical dry etching is performed by applying microwave power between 300W and 500W under a pressure between 200 mTorr and 250 mTorr. Here, the used etching gases are CF4 between 200 sccm and 280 sccm and O2 between 40 sccm and 80 sccm. In one example, the chemical dry etching is performed by applying microwave power of 400 w under a pressure of 225 mTorr. Here, CF4 of 240 sccm and O2 of 60 sccm are used as etching gases.
- The chemical dry etching can reduce damage and defects of silicon by eliminating damage by ions, thereby preventing the unordinary growth of an insulating layer in the following process and improving the electrical characteristics of a device.
- After the chemical dry etching, a cleaning process is performed to wash the etched substrate and, then, an insulating layer is deposited over the resulting
substrate 11. The insulating layer is preferably BPSG (boron phosphorus silicate glass) layer. - The disclosed process removes the damage in silicon lattices due to the etching and the ion implantation processes and enhances the characteristics of an insulating layer by means of the chemical dry etching. Therefore, during the operation of a flash memory device, the loss of electrons can be prevented and the electrical characteristics of a device can be improved.
- As disclosed herein, example methods of fabricating a semiconductor device ensure the uniform thickness of an oxide layer and improve electrical characteristics of a device by employing a damage removal etching process to eliminate damage due to an etching and an ion implantation.
- One example disclosed method may include depositing an oxide layer, a first conducting layer for floating gate, a dielectric layer, and a second conducting layer for control gate in sequence on a semiconductor substrate including a device isolation layer; forming gates by removing some part of the oxide layer, the first conducting layer, the dielectric layer, and the second conducting layer; and forming a mask pattern for a self-aligned source over the substrate including the gates. The example method may also include removing the device isolation layer exposed between the gates; performing an ion implantation process; and eliminating damage generated during the ion implantation process or the removal process of the device isolation layer.
- Although certain methods have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
Claims (13)
1. A semiconductor device, comprising:
a semiconductor substrate comprising a trench formed by removing at least a portion of a device isolation layer;
a plurality of gates each comprising an oxide layer, a first conducting layer for a floating gate, a dielectric layer, and a second conducting layer for a control gate, wherein the trench is formed in the semiconductor substrate between the plurality of gates;
a self-aligned source formed by an impurity ion implantation process in the trench and a selective chemical dry etch for eliminating damage resulting from the ion implantation or the removing of at least a portion of a device isolation layer; and
an insulating layer formed over the resulting substrate .
2. The semiconductor device as defined by claim 1 , wherein the first conducting layer and the dielectric layer are formed of polysilicon.
3. The semiconductor device as defined by claim 1 , wherein the dielectric layer is an oxide-nitride-oxide (ONO) layer.
4. The semiconductor device as defined by claim 1 , wherein the first conducting layer is a doped polysilicon formed by depositing a polysilicon layer and implanting ions As or P in the polysilicon layer.
5. The semiconductor device as defined by claim 1 , further comprising a silicide layer on the second conducting layer.
6. The semiconductor device as defined by claim 1 , wherein the insulating layer is a BPSG (boron phosphorus silicate glass) layer.
7. The semiconductor device as defined by claim 1 , wherein the trench is formed by dry etching the device isolation layer.
8. The semiconductor device as defined by claim 7 , wherein the dry etching is performed by applying a top power between 800 W and 1500 W under a pressure between 100 mTorr and 300 mTorr.
9. The semiconductor device as defined by claim 7 , wherein the dry etching is performed using C4F8 between 3 sccm and 5 sccm, CHF3 between 2 sccm and 6 sccm, O2 between 1 sccm and 5 sccm, and Ar between 100 sccm and 300 sccm.
10. The semiconductor device as defined by claim 1 , wherein the selective chemical dry etch process employs remote plasma in order to prevent ions from entering into a reaction chamber and to allow reaction only by radicals.
11. The semiconductor device as defined by claim 1 , wherein the selective chemical dry etch is an isotropic etching.
12. The semiconductor device as defined by claim 1 , wherein the selective chemical dry etch is performed by applying microwave power between 300 W and 500 W under a pressure between 200 mTorr and 250 mTorr.
13. The semiconductor device as defined by claim 1 , wherein the selective chemical dry etch is performed using CF4 between 200 sccm and 280 sccm and O2 between 40 sccm and 80 sccm.
Priority Applications (1)
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US11/446,064 US20060220075A1 (en) | 2003-09-25 | 2006-06-01 | Methods of fabricating self-aligned source of flash memory device |
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KR1020030066582A KR100561970B1 (en) | 2003-09-25 | 2003-09-25 | Method for fabricating semiconductor device |
KR10-2003-0066582 | 2003-09-25 | ||
US10/758,188 US7074679B2 (en) | 2003-09-25 | 2004-01-15 | Methods of fabricating self-aligned source of flash memory device |
US11/446,064 US20060220075A1 (en) | 2003-09-25 | 2006-06-01 | Methods of fabricating self-aligned source of flash memory device |
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US10/758,188 Continuation US7074679B2 (en) | 2003-09-25 | 2004-01-15 | Methods of fabricating self-aligned source of flash memory device |
PCT/FR2006/002360 A-371-Of-International WO2008046971A1 (en) | 2006-10-20 | 2006-10-20 | Gamma-camera using the depth of interaction in a detector |
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US13/177,423 Division US8143585B2 (en) | 2006-10-20 | 2011-07-06 | Gamma-camera utilizing the interaction depth in a detector |
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US11/446,064 Abandoned US20060220075A1 (en) | 2003-09-25 | 2006-06-01 | Methods of fabricating self-aligned source of flash memory device |
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Cited By (1)
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US20080286922A1 (en) * | 2007-05-18 | 2008-11-20 | Dongbu Hitek Co., Ltd. | Method of fabricating semiconductor device |
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KR100639460B1 (en) * | 2004-12-30 | 2006-10-26 | 동부일렉트로닉스 주식회사 | Method for forming gate of flash memory device |
CN108987401A (en) * | 2018-07-20 | 2018-12-11 | 上海华力微电子有限公司 | A kind of technology integrating method improving flash cell erasing state uniformity |
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2006
- 2006-06-01 US US11/446,064 patent/US20060220075A1/en not_active Abandoned
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US6784061B1 (en) * | 2002-06-25 | 2004-08-31 | Advanced Micro Devices, Inc. | Process to improve the Vss line formation for high density flash memory and related structure associated therewith |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080286922A1 (en) * | 2007-05-18 | 2008-11-20 | Dongbu Hitek Co., Ltd. | Method of fabricating semiconductor device |
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US20050070067A1 (en) | 2005-03-31 |
KR100561970B1 (en) | 2006-03-22 |
KR20050030651A (en) | 2005-03-31 |
US7074679B2 (en) | 2006-07-11 |
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