KR100338090B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to restrain leakage current due to the damage of a silicon substrate and losses of a junction region by selectively forming an amorphous silicon layer on the junction region. CONSTITUTION: Isolated gate electrodes(4) are formed on a silicon substrate(1). An oxide layer(7A) is formed on the gate electrodes, and an oxide spacer(7B) is formed at both sidewalls of the gate electrodes. A source/drain region(6) is formed in the silicon substrate. After cleaning the resultant structure, an amorphous silicon layer(8) is formed on the silicon substrate of the source/drain region(6). Then, an insulating layer is formed on the entire surface of the resultant structure.

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an amorphous silicon layer is selectively formed on source and drain regions.

In general, in the semiconductor device manufacturing process, an etching process is performed to form contact holes. However, the silicon substrate may be damaged due to excessive etching during the etching process. For this reason, device leakage current characteristics and refresh characteristics are degraded during device operation.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing damage to a silicon substrate due to excessive etching in forming a contact hole.

Another object of the present invention is a method of manufacturing a semiconductor device capable of improving the characteristics of the device.

A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of forming a plurality of gate electrodes separated by openings on a silicon substrate, forming the gate oxide spacer, on the silicon substrate Forming a source and drain region in the source, selectively forming an amorphous silicon layer on the silicon substrate of the source and drain region, forming an insulating film on the entire structure, and forming a bit line and a charge storage electrode Characterized in that the step of performing a contact process.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device according to the present invention.

In connection with the first A diagram, the gate oxide film 3 and the polysilicon are sequentially deposited on the silicon substrate 1 on which the field oxide film 2 is formed. The polysilicon and the gate oxide layer 3 are sequentially patterned by a photolithography and an etching process using a mask for a gate electrode. A plurality of gate electrodes 4 separated by openings 14 are formed on the silicon substrate 1, and N ⁻ impurity ions are implanted into the silicon substrate 1 to form a primary junction region 5A. Is formed.

In relation to the first diagram, an oxide film 7A is deposited on the entire structure, an oxide spacer etching process is performed on the oxide film 7A, and a slight oxide film is left on the gate electrode, and the side wall of the gate electrode 4 is formed. An oxide film spacer 7B is formed in the film. N ⁺ impurity ions are implanted into the silicon substrate 1 to form a second junction region 5B having a lightly doped drain (LDD) structure. The primary and secondary junction regions 5A and 5B become source and drain regions 6.

Regarding the 1C diagram, after performing a washing process using CF4 gas over the entire structure, the amorphous silicon layer 8 is selectively formed on the source and drain regions 6 formed on the silicon substrate 1. At this time, an amorphous silicon layer 8 having a thickness of 100 to 500 kPa is formed at a temperature of 450 to 510 ° C using Si ₂ H ₆ gas. The F group is contained in the oxide films 7A and 7B deposited on the gate electrode 4 during the cleaning process using the CF4 gas. Since the F group prevents deposition of amorphous silicon, it is not deposited on the oxide films 7A and 7B deposited on the gate electrode 4, thereby forming an amorphous silicon film.

In relation to the 1D diagram, the primary interlayer insulating film 9A and the primary BPSG film 9B are sequentially formed on the entire upper surface, and an etching process using a contact mask is performed. The first interlayer insulating film 9A and the first BPSG film 9B are patterned, and a first contact hole 11A is formed on the source and drain regions 6.

In relation to the first E diagram, polysilicon is deposited on the entire upper surface including the first contact hole 11A, and the polysilicon is patterned by an etching process to form a bit line 12. Secondary interlayer insulating film 10A and secondary BPSG film 10B are sequentially formed on the entire upper surface, and an etching process using a contact mask is performed. The second interlayer insulating film 10A and the second BPSG film 10B are patterned, and a second contact hole 11B is formed on the source and drain regions 6.

In relation to the first F diagram, polysilicon is deposited on the entire upper surface including the second contact hole 11B, and the polysilicon is patterned by an etching process to form a charge storage electrode 13.

As described above, according to the present invention, an amorphous silicon layer is selectively formed on the source and drain regions to which the bit line and the charge storage electrode are connected, thereby acting as a protective film during an etching process for forming a contact hole. There is an excellent effect to prevent excessive leakage current due to loss of junction area and to improve device characteristics.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Explanation of symbols on the main parts of the drawings

1 silicon substrate 2: field oxide film

3: gate oxide film 4: gate electrode

5A: primary junction region 5B: secondary junction region

6: source and drain region 7A: oxide film

7B: oxide film spacer 8: amorphous silicon layer

9A: primary interlayer insulating film 9B: primary BPSG film

10A: secondary interlayer insulating film 10B: secondary BPSG film

11A: first contact hole 11B: second contact hole

12 bit line 13 charge storage electrode

14: opening

Claims (4)

In the semiconductor device manufacturing method, Forming a plurality of gate electrodes separated on a silicon substrate, Depositing an oxide film over the entire structure, forming an oxide spacer on sidewalls of the gate electrode, and etching the thin oxide film to remain on the gate electrode; Performing impurity ion implantation on the silicon substrate to form source and drain regions; Performing a cleaning process, Selectively forming an amorphous silicon layer on a silicon substrate in the source and drain regions; And forming an insulating film on the entire structure. The method of claim 1, wherein the cleaning process is performed using CF ₄ gas. The method of claim 1, wherein the amorphous silicon layer is formed at a temperature of 450 to 510 ° C. and an atmosphere of 0.1 to 5.0 Torr using Si ₂ H ₆ gas. The method of claim 1, wherein the amorphous silicon layer is formed to a thickness of about 100 to 500 microns.