KR940003595B1 - Method of fabricating a semiconductor device - Google Patents

Method of fabricating a semiconductor device Download PDF

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KR940003595B1
KR940003595B1 KR1019910014811A KR910014811A KR940003595B1 KR 940003595 B1 KR940003595 B1 KR 940003595B1 KR 1019910014811 A KR1019910014811 A KR 1019910014811A KR 910014811 A KR910014811 A KR 910014811A KR 940003595 B1 KR940003595 B1 KR 940003595B1
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forming
high temperature
temperature oxide
oxide film
semiconductor device
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KR930005215A (en
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박영우
최영제
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The method includes the steps of; forming device isolation region and active region on a first conductive semiconductor substrate and gate electrode; forming source/drain region by ion injecting second conductive impurity; forming a nitride layer; forming a first high temperature oxide layer; blocking cell portion using photoresist and anisotropically etching said first high temperature oxide layer to form spacer; forming LDD structure by forming source/drain region by injecting second conductive impurity; removing said first high temperature oxide layer by wet etching; forming capacitor; and forming planarizing layer, contact hole and bit line, thereby improving step coverage and preventing over-etching of contact hole.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

제1a도 내지 제1f도는 종래 DRAM의 제조방법을 공정순서에 따라 나타낸 도면.1A to 1F are diagrams showing a conventional method for manufacturing a DRAM in a process sequence.

제2a도 내지 제2f도는 본 발명에 따른 DRAM의 제조방법을 공정순서에 따라 나타낸 도면.2A to 2F are diagrams showing a method of manufacturing a DRAM according to the present invention in a process sequence.

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 DRAM의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a DRAM.

종래의 16M DRAM의 셀트랜지스터는 리프레쉬 특성의 개선을 위해 스페이서(Spacer)가 없는 n-(소오스-드레인) 어레이의 구조로 되어 있는데 이는 셀트랜지스터에 스페이서를 형성할 경우 스페이서 식각시의 손상으로 인하여 리프레쉬 특성이 나빠지는 것에 대한 대책이었다.A cell transistor of a conventional 16M DRAM is n do not have a spacer (Spacer), to improve the refresh characteristics - there is a - (source drain) structure in the array which the refreshing due to damage during the spacer etch the case of forming the spacer in the cell transistor It was a measure against the deterioration of characteristics.

제1a도 내지 제1f도에 상기 종래의 스페이서가 없는 n-(소오스/트레인) 어레이 구조로 된 셀부분과 LDD(Lightly Doped Drain) 주변부로 이루어진 DRAM의 제조공정을 나타내었다.1A to 1F illustrate a DRAM manufacturing process including a cell portion having an n − (source / train) array structure without the conventional spacer and a lightly doped drain (LDD) peripheral portion.

반도체기판(1)상에 소자분리영역과 액티브영역을 형성한 후 게이트전극(4)을 형성하고 n형 불순물을 가볍게(lightly) 이온주입하여 n-의 소오스/드레인(5) 영역을 형성한다(제1a도). 여기에서 미설명부호 2와 3은 각각 필드산화막의 게이트산화막을 나타낸다.After forming the isolation region and the active region on the semiconductor substrate 1, the gate electrode 4 is formed, and lightly ion implanted with n - type impurities to form the n-source / drain 5 region ( 1a). Reference numerals 2 and 3 here denote gate oxide films of the field oxide films, respectively.

이어서 주변부의 트랜지스터의 스페이스 형성을 위해 고온산화막(High Temperature Oxide)(6)을 형성한 후(제1b도), 셀부분은 포토레지스트마스크(7)를 이용하여 블로킹(Blocking)하여 주변부만 스페이서 식각을 실시하여 스페이서(6')를 형성한 후 n형 불순물을 무겁게(heavily) 이온주입하여 n+의 소오스/드레인 영역(8)을 형성하여 LDD 구조를 만든다(제1c도).Subsequently, a high temperature oxide film 6 is formed to form a space of the transistor in the peripheral portion (FIG. 1b), and then the cell portion is blocked using the photoresist mask 7 so that only the peripheral portion is etched. After the spacer 6 'is formed, n-type impurities are heavily ion implanted to form an n + source / drain region 8 to form an LDD structure (FIG. 1C).

이어서 셀부분을 블로킹하고 있는 포토레지스트마스크를 제거한 다음 매몰콘택(Buried Contact) 형성을 위해 고온산화막(9)을 형성한 후 콘택홀을 만들고(제1d도), 스토리지전극(10), 절연충(11), 플레이트전극(12)을 차례로 형성하여 셀부분에 커패시터를 형성한다(제1e도).Subsequently, the photoresist mask blocking the cell portion is removed, and then a high temperature oxide film 9 is formed to form a buried contact, and then a contact hole is formed (FIG. 1d), the storage electrode 10, and the insulating worm ( 11), plate electrodes 12 are sequentially formed to form capacitors in the cell portion (FIG. 1E).

이어서 평탄화충(13)을 형성하고 비트선접속을 위한 콘택홀을 만든 다음 상기 콘택홀이 형성된 반도체기판 전면에 비트선(14)을 형성함으로써 DRAM을 완성한다(제1f도).Subsequently, the planarizing worms 13 are formed, a contact hole for bit line connection is made, and a bit line 14 is formed on the entire surface of the semiconductor substrate on which the contact hole is formed, thereby completing the DRAM (FIG. 1f).

상기와 같은 종래의 방법에서는 주변부의 LDD 구조의 트랜지스터를 형성하기 위하여 스페이서를 만들기 위한 고온산화막(6)을 침적한 후 셀부는 마스크로 블로킹하고 주변부만 스페이서식각을 실시함에 따라 스페이서가 형성되지 않는 셀부와 스페이서가 형성되는 주변부와는 스페이서를 만들기 위해 침적하는 고온산화막(6)의 두께만큼 단차가 생기게 되며 이 셀부와 주변부의 단차는 셀부에 커패시터를 형성한 후 더욱 커지게 되어 스텝커버리지(Step coverage)가 나빠지므로 후속공정인 비트선접속을 위한 콘택홀형성공정 및 비트선형성공정이 어려워지는 문제가 있다.In the conventional method as described above, after depositing the high temperature oxide film 6 for forming the spacer to form the transistor of the LDD structure of the peripheral portion, the cell portion is blocked with a mask and only the peripheral portion is subjected to spacer etching. The gap between the cell and the peripheral portion is formed by the thickness of the high temperature oxide film 6 deposited to form the spacer, and the gap between the cell portion and the peripheral portion becomes larger after forming a capacitor in the cell portion. As a result, the contact hole forming process and the bit linear forming process for the bit line connection, which are subsequent processes, become difficult.

본 발명의 목적은 DRAM의 셀어레이 부분과 주변부와의 단차를 줄일 수 있는 반도체장치의 제조방법을 제공하는데 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the step difference between the cell array portion and the peripheral portion of the DRAM.

상기 목적을 달성하기 위해 본 발명의 방법은 소오스/드레인영역이 제2도전형으로 가볍게 도우프된 셀부와 소오스/드레인영역이 LDD 구조로 된 주변부로 이루어진 반도체장치의 제조방법에 있어서, 제1도전형의 반도체기판상에 소자분리영역과 액티브영역을 형성한 후 게이트전극을 형성하고 제2도전형의 불순물을 가볍게 이온주입하여 소오스/드레인영역을 형성하는 공정과, 상기 반도체기판 전면에 질화막을 형성하는 공정, 상기 질화막상에 제1고온산화막을 형성하는 공정, 상기 반도체기관상의 셀부는 포토레지스트로 블로킹하고 주변부에 형성된 제1고온산화막만을 이방성식각하여 스페이서를 형성한 후 제2도전형의 불순물을 무겁게 주입하여 소오스/드레인영역을 형성하여 LDD 구조를 만드는 공정, 상기 셀부 및 주변부의 제1고온산화막을 습식식각에 의해 모두 제거하는 공정, 상기 노출된 질화막상에 제2고온산화막을 침적한 후 반도체기판의 소정영역에 커패시터를 형성하는 공정, 및 상기 커패시터가 형성된 반도체기판 전면에 평탄화층을 형성하고 비트선접속을 위한 콘택홀을 형성한 후 비트선을 형성하는 공정이 구비되어 있는 것을 특징으로 한다.In order to achieve the above object, the method of the present invention provides a method of manufacturing a semiconductor device comprising a cell portion lightly doped with a source / drain region as a second conductivity type and a peripheral portion with a source / drain region having an LDD structure. Forming a device isolation region and an active region on the semiconductor semiconductor substrate, forming a gate electrode, and implanting impurities of the second conductive type to form a source / drain region, and forming a nitride film on the entire surface of the semiconductor substrate. Forming a first high temperature oxide film on the nitride film, blocking the cell portion on the semiconductor engine with photoresist, and anisotropically etching only the first high temperature oxide film formed on the periphery to form a spacer, and then Heavily implanted to form a source / drain region to form an LDD structure; wet the first high temperature oxide film of the cell and peripheral portions Removing all by an angle, depositing a second high temperature oxide film on the exposed nitride film, forming a capacitor in a predetermined region of the semiconductor substrate, and forming a planarization layer on the entire surface of the semiconductor substrate on which the capacitor is formed, and forming a bit line. And forming a bit line after forming a contact hole for connection.

이하, 본 발명의 실시예를 도면을 참조하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

제2a도 내지 제2f도에 본 발명에 의한 DRAM의 제조공정순서를 나타내었는 바, 이를 설명하면 다음과 같다.2A to 2F show the manufacturing process steps of the DRAM according to the present invention.

반도체기판(21)상에 소자분리영역과 액티브영역을 형성한 후 게이트전극(24)을 형성하고 n형 불순물을 가볍게(lightly) 이온주입하여 n-의 소오스/드레인(25)영역을 형성한다(제2a도). 여기에서 미설명부호 22와 23은 각각 필드산화막과 게이트산화막을 나타낸다.After the isolation region and the active region are formed on the semiconductor substrate 21, the gate electrode 24 is formed and the ion-implanted n-type impurities are lightly implanted to form an n − source / drain 25 region ( 2a). Reference numerals 22 and 23 denote the field oxide film and the gate oxide film, respectively.

이어서 100Å∼1,OOOÅ 두께의 얇은 질화막(26)을 침적하고 주변부의 트랜지스터의 스페이서 형성을 위한 고온산화막(27)을 침적한다(제2b도).Subsequently, a thin nitride film 26 having a thickness of 100 GPa to 1, OOO is deposited and a high temperature oxide film 27 for spacer formation of the transistor in the peripheral portion is deposited (FIG. 2B).

그리고 난 후 셀부는 포토레지스트마스크(29)로 블로킹하고 주변부만 스페이서식각을 실시하여 스페이서(27')를 형성한 후 n형 불순물을 무겁게(heavily) 주입하여 n+의 소오스/드레인영역을 형성하여 LDD 구조로 만든다(제2c도). 이렇게 함으로써 스페이서가 없는 n-(소오스/드레인) 어레이의 셀트랜지스터 및 n+LDD 구조의 주변부 트랜지스터가 완성된다.After that, the cell portion is blocked by the photoresist mask 29, and only the peripheral portion is subjected to spacer etching to form the spacer 27 ', and then heavily implanted n-type impurities to form a source / drain region of n + . Create an LDD structure (Figure 2c). This completes the cell transistor of the n − (source / drain) array without a spacer and the peripheral transistor of the n + LDD structure.

이어서 상기 포토레지스트마스크를 제거한 후, BOE(Bufferde Oxied Etchant)를 이용한 습식식각에 의하여 셀부 및 주변부의 고온산화막을 모두 제거한다(제2d도). 이에 따라 셀부와 주변부의 단차는 생기지 않으면서 스페이서 형성을 위한 고온산화막을 침적하기 전에 침적된 질화막(26)에 의해 액티브영역과 필드 영역이 충분히 보호된다.Subsequently, after the photoresist mask is removed, all of the high temperature oxide layers of the cell portion and the peripheral portion are removed by wet etching using BOE (Bufferde Oxied Etchant) (FIG. 2D). Accordingly, the active region and the field region are sufficiently protected by the deposited nitride film 26 before the high temperature oxide film for spacer formation is deposited without generating a step between the cell portion and the peripheral portion.

이어서 매몰콘택형성을 위해 고온산화막(30)을 500Å-3,OOOÅ 침적한 후 매몰콘택을 만들고 나서 스토리 지전극(31), 절연층(32), 플레이트전극(33)을 차례로 형성하여 셀부분에 커패시터를 형성한다(제2e도).Subsequently, 500 Å-3, OOO Å of the high temperature oxide film 30 is deposited to form a buried contact, and then a buried contact is formed, and then the storage electrode 31, the insulating layer 32, and the plate electrode 33 are sequentially formed in the cell portion. A capacitor is formed (Fig. 2e).

이어서 평탄화층(34)을 형성하고 비트선접속을 위한 콘택홀을 만든 다음 상기 평탄화층(34)상 및 콘택홀에 비트선(35)을 형성함으로써 DRAM을 완성한다(제2f도).Subsequently, the planarization layer 34 is formed, a contact hole for bit line connection is made, and a bit line 35 is formed on the planarization layer 34 and in the contact hole to complete the DRAM (FIG. 2f).

이상 상술한 바와 같이 본 발명에 의하면, DRAM의 셀부분은 스페이서가 없는 n-(소오스/드레인) 어레이로 형성하고 주변부는 LDD 구조로 종래와 같이 형성하면서 셀부와 주변부의 단차를 줄일 수 있음에 따라 셀부와 주변부에 동시에 형성되는 후속의 모든 공정을 용이하게 할 수 있으며, 특히 셀부의 비트선의 스텝커버리지를 개선할 수 있고 주변부의 비트선접속을 위한 콘택홀의 과다식각을 방지할 수 있다.According to that formed from a (source / drain) of the array and the peripheral portion is, forming as in the prior art as a LDD structure reduces the difference in level of the cell part and the peripheral part - according to at least to the present invention, as described above, the cell portion of the DRAM is the spacer is n-free All subsequent processes simultaneously formed at the cell portion and the peripheral portion can be facilitated, and in particular, the step coverage of the bit line of the cell portion can be improved, and over-etching of the contact hole for bit line connection at the peripheral portion can be prevented.

Claims (6)

소오스/드레인영역이 제2도전형으로 가볍게 도우프된 셀부와 소오스/드레인영역이 LDD 구조로 된 주변부로 이루어진 반도체장치의 제조방법에 있어서, 제1도전형의 반도체기판상에 소자분리영역과 액티브 영역을 형성한 후 게이트전극을 형성하고 제2도전형의 불순물을 가볍게 이온주입하여 소오스/드레인영역을 형성하는 공정과, 상기 반도체기판 전면에 질화막을 형성하는 공정, 상기 질화막상에 제1고온산화막을 형성하는 공정, 상기 반도체기판상의 셀부는 포토레지스트로 블로킹하고 주변부에 형성된 제1고온산화막만을 이방성식각하여 스페이서를 형성한 후 제2도전형의 불순물을 무겁게 주입하여 소오스/드레인영역을 형성하여 LDD 구조를 만드는 공정, 상기 셀부 및 주변부의 제1고온산화막을 습식식각에 의해 모두 제거하는 공정, 상기 노출된 질화막상에 제2고온산화막을 침적한 후 반도체기판의 소정영역에 커패시터를 형성하는 공정, 및 상기 커패시터가 형성된 반도체기판 전면에 평탄화층을 형성하고 비트선접속을 위한 콘택홀을 형성한 후 비트선을 형성하는 공정이 구비되어 있는 것을 특징으로 하는 반도체장치의 제조방법.A method of manufacturing a semiconductor device comprising a cell portion lightly doped with a source / drain region as a second conductive type and a peripheral portion with a source / drain area having an LDD structure, wherein the device isolation region and the active region are formed on a semiconductor substrate of the first conductive type. Forming a gate electrode after forming a region, and lightly ion implanting impurities of a second conductivity type to form a source / drain region; forming a nitride film over the entire surface of the semiconductor substrate; and forming a first high temperature oxide film on the nitride film. Forming a spacer by blocking the cell portion on the semiconductor substrate with photoresist and anisotropically etching only the first high temperature oxide film formed on the periphery, and heavily injecting impurities of the second conductivity type to form a source / drain region A process of making a structure, removing all of the first high temperature oxide film of the cell portion and the peripheral portion by wet etching; Depositing a second high temperature oxide film on the nitride film and forming a capacitor in a predetermined region of the semiconductor substrate; and forming a planarization layer on the entire surface of the semiconductor substrate on which the capacitor is formed, and forming a contact hole for bit line connection. And a step of forming a semiconductor device. 제1항에 있어서, 상기 제1도전형은 p형인 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the first conductivity type is p-type. 제1항에 있어서, 상기 제2도전형은 n형인 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said second conductivity type is n-type. 제1항에 있어서, 상기 질화막은 100Å-1,000Å의 두께로 얇게 형성되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film is formed thin in a thickness of 100 kPa-1,000 kPa. 제1항에 있어서, 상기 제1고온산화막을 제거하기 위한 습식식각은 BOE에 의해 행해지는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the wet etching for removing the first high temperature oxide film is performed by BOE. 제1항에 있어서, 상기 제2고온산화막은 500Å-3,000Å의 두께로 형성되는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the second high temperature oxide film is formed to a thickness of 500 kPa-3,000 kPa.
KR1019910014811A 1991-08-26 1991-08-26 Method of fabricating a semiconductor device KR940003595B1 (en)

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