KR930005215A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR930005215A
KR930005215A KR1019910014811A KR910014811A KR930005215A KR 930005215 A KR930005215 A KR 930005215A KR 1019910014811 A KR1019910014811 A KR 1019910014811A KR 910014811 A KR910014811 A KR 910014811A KR 930005215 A KR930005215 A KR 930005215A
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KR
South Korea
Prior art keywords
forming
oxide film
semiconductor device
temperature oxide
high temperature
Prior art date
Application number
KR1019910014811A
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Korean (ko)
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KR940003595B1 (en
Inventor
박영우
최영제
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910014811A priority Critical patent/KR940003595B1/en
Publication of KR930005215A publication Critical patent/KR930005215A/en
Application granted granted Critical
Publication of KR940003595B1 publication Critical patent/KR940003595B1/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음.No content.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2F도는 본 발명에 따른 DRAM의 제조방법을 공정순서에 따라 나타낸 도면.2A to 2F are diagrams showing a manufacturing method of a DRAM according to the present invention in a process sequence.

Claims (6)

소오스/드레인영역이 제2도전형으로 가볍게 도우프된 셀부와 소오스/드레인영역이 LDD구조로 된 주변부로 이루어진 반도체장치의 제조방법에 있어서, 제1도전형의 반도체기판상에 소자분리령역과 액티브영역을 형성한 후 게이트전극을 형성하고 제2도전형의 불순물을 가볍게 이온주입하여 소오스/드레인영역을 형성하는 공정과, 상기 반도체기판 전면에 질화막을 형성하는 공정, 상기 질화막상에서 제1고온산화막을 형성하는 공정, 상기 반도체기판상의 셀부는 포토레지스트로 블로킹하고 주변부에 형성된 제1고온산화막만을 이방성 식각하여 스페이서를 형성한후 제2도전형의 불순물을 무겁게 주입하여 소오스/드레인 영역을 형성하여 LDD구조를 만드는 공정, 상기 셀부 및 주변부의 제1고온산화막을 습식식각에 의해 모두 제거하는 공정, 상기 노출된 질화막상에 제2고온산화막을 침적한후 반도체기판의 소정영역에 커패시터를 형성하는 공정, 및 상기 커패시터가 형성된 반도체기판 전면에 평탄화층을 형성하고 비트선접속을 위한 콘택홀을 형성한 후 비트선을 형성하는 공정이 구비되어 있는 것을 특징으로 튀는 반도체장치의 제조방법.A method of fabricating a semiconductor device comprising a cell portion lightly doped with a source / drain region as a second conductive type and a peripheral portion with a source / drain area having an LDD structure, wherein the element isolation region and active region are formed on a semiconductor substrate of the first conductive type. Forming a gate electrode after forming the region, and lightly ion implanting impurities of the second conductivity type to form a source / drain region; forming a nitride film over the entire semiconductor substrate; and forming a first high temperature oxide film on the nitride film. In the forming step, the cell portion on the semiconductor substrate is blocked by photoresist and anisotropically etched only the first high temperature oxide film formed on the periphery to form a spacer, followed by heavily injecting impurities of the second conductivity type to form a source / drain region to form an LDD structure. Process of making, removing all of the first high-temperature oxide film of the cell portion and the peripheral portion by wet etching, the exposure Depositing a second high temperature oxide film on the nitride film, and then forming a capacitor in a predetermined region of the semiconductor substrate, and forming a planarization layer on the entire surface of the semiconductor substrate on which the capacitor is formed, and forming a contact hole for bit line connection. A method of manufacturing a splashing semiconductor device, characterized by comprising a step of forming a. 제1항에 있어서, 상기 제1도전형은 p형인 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the first conductivity type is p-type. 제1항에 있어서, 상기 제1도전형은 n형인 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the first conductivity type is n-type. 제1항에 있어서, 상기 질화막은 100Å∼1,000Å의 두께로 얇게 형성되는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film is formed thin in a thickness of 100 kPa to 1,000 kPa. 제1항에 있어서, 상기 제1고온산화막을 제거하기 위한 습식식각은 BOE에 의해 행해지는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the wet etching for removing the first high temperature oxide film is performed by BOE. 제1항에 있어서, 상기 제1고온산화막 500Å∼3,000Å의 두께로 형성되는 것을 특징으로 하는 반도체장치의 제조방법.2. The method of manufacturing a semiconductor device according to claim 1, wherein the first high temperature oxide film is formed to a thickness of 500 to 3000 mW. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910014811A 1991-08-26 1991-08-26 Method of fabricating a semiconductor device KR940003595B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910014811A KR940003595B1 (en) 1991-08-26 1991-08-26 Method of fabricating a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910014811A KR940003595B1 (en) 1991-08-26 1991-08-26 Method of fabricating a semiconductor device

Publications (2)

Publication Number Publication Date
KR930005215A true KR930005215A (en) 1993-03-23
KR940003595B1 KR940003595B1 (en) 1994-04-25

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Application Number Title Priority Date Filing Date
KR1019910014811A KR940003595B1 (en) 1991-08-26 1991-08-26 Method of fabricating a semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419749B1 (en) * 1996-10-22 2004-06-04 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419749B1 (en) * 1996-10-22 2004-06-04 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Also Published As

Publication number Publication date
KR940003595B1 (en) 1994-04-25

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