KR20000039157A - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR20000039157A KR20000039157A KR1019980054403A KR19980054403A KR20000039157A KR 20000039157 A KR20000039157 A KR 20000039157A KR 1019980054403 A KR1019980054403 A KR 1019980054403A KR 19980054403 A KR19980054403 A KR 19980054403A KR 20000039157 A KR20000039157 A KR 20000039157A
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- Prior art keywords
- active region
- silicide
- drain
- source
- region
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 53
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 24
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 230000003064 anti-oxidating effect Effects 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- -1 nitrogen ions Chemical class 0.000 claims 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052731 fluorine Inorganic materials 0.000 abstract description 2
- 239000011737 fluorine Substances 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 abstract 2
- 230000002265 prevention Effects 0.000 description 11
- 239000002184 metal Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 실리사이드가 형성되지 않는 소자를 효과적으로 보호하여 실리사이드가 형성되는 소자의 특성저하를 방지하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, which is suitable for effectively preventing a device in which silicide is not formed to prevent deterioration of characteristics of the device in which silicide is formed.
종래 반도체소자의 제조방법을 도1a 내지 도1f에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described in detail with reference to the procedure cross-sectional view shown in FIGS. 1A to 1F.
먼저, 도1a에 도시한 바와같이 소자격리영역(2)을 통해 실리사이드가 형성되는 제1액티브영역과 형성되지 않는 제2액티브영역이 구분된 반도체기판(1)의 제1,제2액티브영역 상에 게이트산화막(3)과 게이트전극(4)이 적층된 게이트를 형성한다. 이때, 도면에 도시하지는 않았지만 불순물 이온주입을 통해 반도체기판(1)의 노출된 제1,제2액티브영역 내에 소스/드레인이 형성된다.First, as shown in FIG. 1A, the first and second active regions of the semiconductor substrate 1 in which the first active region in which silicide is formed and the second active region in which silicide is formed through the device isolation region 2 are separated. A gate in which the gate oxide film 3 and the gate electrode 4 are stacked is formed on the gate. At this time, although not shown in the drawing, source / drain is formed in the exposed first and second active regions of the semiconductor substrate 1 through the implantation of impurity ions.
그리고, 도1b에 도시한 바와같이 상기 게이트가 형성된 구조물의 상부전면에 절연막을 형성한 후, 선택적으로 식각하여 상기 게이트에 사이드월(side wall,5)을 형성한다.As shown in FIG. 1B, an insulating film is formed on the upper surface of the structure on which the gate is formed, and then selectively etched to form sidewalls 5 in the gate.
그리고, 도1c에 도시한 바와같이 상기 게이트에 사이드월(5)이 형성된 구조물의 상부전면에 실리사이드형성 방지막(6)을 증착한 후, 감광막을 도포, 노광 및 현상하여 제2액티브영역의 실리사이드형성 방지막(6) 상부에 감광막 패턴(PR1)을 형성한다.As shown in FIG. 1C, after the silicide formation prevention film 6 is deposited on the upper surface of the structure in which the sidewall 5 is formed on the gate, a photosensitive film is applied, exposed, and developed to form silicide of the second active region. The photoresist pattern PR1 is formed on the protection layer 6.
그리고, 도1d에 도시한 바와같이 상기 감광막 패턴(PR1)을 적용하여 노출된 실리사이드형성 방지막(6)을 식각한다. 이때, 실리사이드형성 방지막(6)은 플라즈마 식각을 통해 식각되는데, 소자격리영역(2)은 과도식각되어 손실(loss)이 발생하며, 플라즈마 식각에서 발생되는 전하(charge)가 상기 제1액티브영역의 게이트전극(4)에 인가됨에 따라 게이트산화막(3)에 손상(damage)을 주게 된다.As shown in FIG. 1D, the exposed silicide formation prevention layer 6 is etched by applying the photoresist pattern PR1. In this case, the silicide formation prevention layer 6 is etched through plasma etching, and the device isolation region 2 is excessively etched to generate a loss, and a charge generated in the plasma etch may be generated in the first active region. As it is applied to the gate electrode 4, the gate oxide film 3 is damaged.
그리고, 도1e에 도시한 바와같이 상기 감광막 패턴(PR1)을 제거하고 세정한다.Then, the photosensitive film pattern PR1 is removed and cleaned as shown in FIG. 1E.
그리고, 도1f에 도시한 바와같이 상기 세정된 구조물의 상부전면에 금속층을 증착한 후, 열처리하는 살리사이드(SALICIDE) 공정을 적용하여 제1액티브영역의 게이트전극(4) 및 소스/드레인 표면에 실리사이드층(7)을 형성한다.In addition, as shown in FIG. 1F, a metal layer is deposited on the upper surface of the cleaned structure, and then a heat treatment is applied to the gate electrode 4 and the source / drain surface of the first active region by applying a salicide process. The silicide layer 7 is formed.
여기서, 살리사이드 공정이란 열처리에 의해 금속과 실리콘은 반응하여 실리사이드층(7)으로 형성되지만, 금속과 사이드월(5), 소자격리영역(2) 및 실리사이드형성 방지막(6)은 반응하지 않는 성질을 이용하여 제1액티브영역의 게이트전극(4) 및 소스/드레인 표면에만 선택적으로 실리사이드층(7)을 형성하고, 반응하지 않은 금속층을 제거하는 일련의 공정을 지칭하며, 이와같은 실리사이드층(7)은 저항값을 크게 감소시켜 반도체소자의 특성향상에 기여한다.Here, in the salicide process, the metal and silicon react with each other by heat treatment to form the silicide layer 7, but the metal and the sidewall 5, the device isolation region 2, and the silicide formation prevention film 6 do not react. A method of forming a silicide layer 7 selectively on only the gate electrode 4 and the source / drain surface of the first active region by using Equation 2 and removing a non-reacted metal layer, the silicide layer 7 ) Greatly reduces the resistance value and contributes to the improvement of the characteristics of the semiconductor device.
상술한 바와같이 종래 반도체소자의 제조방법은 실리사이드형성 방지막을 실리사이드가 형성되는 소자의 상부에도 형성한 후, 플라즈마 식각함에 따라 소자격리영역에 손실이 발생하여 접합누설전류가 증가되며, 아울러 게이트전극에 인가되는 플라즈마 전하(charge)로 인해 게이트산화막이 손상되어 반도체소자의 신뢰성이 저하되는 문제점이 있었다.As described above, in the conventional method of manufacturing a semiconductor device, after forming the silicide formation prevention layer on the upper surface of the device on which the silicide is formed, a loss occurs in the device isolation region due to plasma etching, thereby increasing the junction leakage current and increasing the gate electrode. There is a problem that the gate oxide film is damaged by the plasma charge applied, thereby reducing the reliability of the semiconductor device.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 실리사이드가 형성되지 않는 소자를 효과적으로 보호하여 실리사이드가 형성되는 소자의 게이트산화막 손상 및 소자격리영역 손실을 최소화할 수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to effectively protect devices that do not form silicide, thereby minimizing gate oxide damage and device isolation region loss of the silicide-formed devices. To provide a method for manufacturing a semiconductor device that can be.
도1은 종래 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12:소자격리영역11: semiconductor substrate 12: device isolation region
13:게이트산화막 14:게이트전극13: gate oxide film 14: gate electrode
15:측벽 16:실리사이드형성 방지산화막15: side wall 16: silicide formation prevention oxide film
17:실리사이드층 PR11:감광막 패턴17: silicide layer PR11: photosensitive film pattern
F:불소이온F: fluorine ion
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자 제조방법의 바람직한 일 실시예는 실리사이드가 형성되는 제1액티브영역과 형성되지 않는 제2액티브영역이 소자격리영역을 통해 구분된 반도체기판의 제1,제2액티브영역 상에 측벽을 갖는 게이트 및 소스/드레인을 형성하는 공정과; 상기 제1액티브영역의 상부에 감광막 패턴을 형성하는 공정과; 상기 감광막 패턴을 마스크로 하여 제2액티브영역에 산화공정에 따른 산화막의 형성을 촉진하는 불순물이온을 주입하는 공정과; 상기 감광막 패턴을 제거하고, 산화공정을 수행하여 제1,제2액티브영역의 게이트전극 및 소스/드레인 상에 서로다른 두께를 갖는 실리사이드형성 방지산화막을 형성하는 공정과; 상기 실리사이드형성 방지산화막이 형성된 구조물에 세정공정을 수행하여 제2액티브영역의 게이트전극 및 소스/드레인 상에만 실리사이드형성 방지산화막을 잔류시키는 공정과; 상기 제1,제2액티브영역 상에 살리사이드 공정을 수행하여 제1액티브영역의 게이트전극 및 소스/드레인 상에만 실리사이드층을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.One preferred embodiment of the semiconductor device manufacturing method for achieving the object of the present invention as described above is the first substrate of the semiconductor substrate in which the first active region in which the silicide is formed and the second active region not formed through the device isolation region Forming a gate and a source / drain having sidewalls on the first and second active regions; Forming a photoresist pattern on the first active region; Implanting impurity ions which promote the formation of an oxide film according to an oxidation process in a second active region using the photosensitive film pattern as a mask; Removing the photoresist pattern and performing an oxidation process to form silicide formation preventing oxide films having different thicknesses on the gate electrodes and the source / drain of the first and second active regions; Performing a cleaning process on the structure on which the silicide forming anti-oxidation film is formed to leave the silicide forming anti-oxidation film only on the gate electrode and the source / drain of the second active region; And forming a silicide layer only on the gate electrode and the source / drain of the first active region by performing a salicide process on the first and second active regions.
상기한 바와같은 본 발명에 의한 반도체소자 제조방법의 바람직한 실시예를 도2a 내지 도2f의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the semiconductor device manufacturing method according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2F.
먼저, 도2a에 도시한 바와같이 실리사이드가 형성되는 제1액티브영역과 형성되지 않는 제2액티브영역이 소자격리영역(12)을 통해 구분된 반도체기판(11)의 제1,제2액티브영역 상에 측벽(15)을 갖는 게이트(13,14) 및 소스/드레인(미도시)을 형성한다. 이때, 게이트(13,14)는 종래와 동일하게 게이트산화막(13) 및 게이트전극(14)이 적층되어 형성되며, 소스/드레인은 도면에 도시하지는 않았지만 게이트(13,14) 및 측벽(15)에 의해 노출되는 반도체기판(11)의 제1,제2액티브영역 내에 불순물 이온주입을 통해 형성되며, 채널길이가 짧아짐에 따른 영향을 최소화하기 위하여 엘디디(lightly doped drain : LDD) 구조가 채택된다.First, as shown in FIG. 2A, the first and second active regions of the semiconductor substrate 11 in which the first active region in which silicide is formed and the second active region in which no silicide is formed are separated through the device isolation region 12 are formed. Gates 13 and 14 having sidewalls 15 and source / drain (not shown) are formed. In this case, the gates 13 and 14 are formed by stacking the gate oxide layer 13 and the gate electrode 14 in the same manner as in the prior art. It is formed through the implantation of impurity ions into the first and second active regions of the semiconductor substrate 11 exposed by the light emitting structure, and an lightly doped drain (LDD) structure is adopted to minimize the effect of shortening of the channel length. .
그리고, 도2b에 도시한 바와같이 상기 제1,제2액티브영역의 상부에 전면에 감광막을 도포, 노광 및 현상하여 제1액티브영역 상부에 감광막 패턴(PR11)을 형성한다.As shown in FIG. 2B, a photoresist film is coated, exposed and developed on the entire surface of the first and second active regions to form a photoresist pattern PR11 on the first active region.
그리고, 도2c에 도시한 바와같이 상기 감광막 패턴(PR11)을 마스크로 하여 제2액티브영역에 산화공정에 따른 산화막의 형성을 촉진하는 불순물이온으로 예를들면, 플루오르(F)를 주입한다.As shown in Fig. 2C, for example, fluorine (F) is implanted into the second active region with impurity ions that promote the formation of an oxide film according to the oxidation process, using the photosensitive film pattern PR11 as a mask.
그리고, 도2d에 도시한 바와같이 상기 감광막 패턴(PR11)을 제거하고, 산화공정을 수행하여 제1,제2액티브영역의 게이트전극(14) 및 소스/드레인(미도시) 상에 서로다른 두께를 갖는 실리사이드형성 방지산화막(16)을 형성한다.As shown in FIG. 2D, the photoresist pattern PR11 is removed and an oxidation process is performed to different thicknesses on the gate electrode 14 and the source / drain (not shown) of the first and second active regions. A silicide formation prevention oxide film 16 having a structure is formed.
그리고, 도2e에 도시한 바와같이 상기 실리사이드형성 방지산화막(16)이 형성된 구조물에 세정공정을 수행하여 제2액티브영역의 게이트전극(14) 및 소스/드레인 상에만 실리사이드형성 방지산화막(16)을 잔류시킨다. 이때, 제1액티브영역에 형성된 실리사이드형성 방지산화막(16)은 세정공정에 의해 완전히 제거되지만, 상대적으로 두꺼운 제2액티브영역에 형성된 실리사이드형성 방지산화막(16)은 잔류하게 된다.As shown in FIG. 2E, the silicide formation prevention oxide layer 16 is formed only on the gate electrode 14 and the source / drain of the second active region by performing a cleaning process on the structure on which the silicide formation prevention oxide layer 16 is formed. Remain. At this time, the silicide formation prevention oxide film 16 formed in the first active region is completely removed by the cleaning process, but the silicide formation prevention oxide film 16 formed in the relatively thick second active region remains.
그리고, 도2f에 도시한 바와같이 상기 제1,제2액티브영역 상에 살리사이드 공정을 수행하여 제1액티브영역의 게이트전극(14) 및 소스/드레인 상에만 실리사이드층(17)을 형성한다. 이때, 제2액티브영역의 게이트전극(14) 및 소스/드레인 상에는 잔류하는 실리사이드형성 방지산화막(16)으로 인해 실리사이드층(17)이 형성되지 않는다.As shown in FIG. 2F, the salicide process is performed on the first and second active regions to form the silicide layer 17 only on the gate electrode 14 and the source / drain of the first active region. At this time, the silicide layer 17 is not formed on the gate electrode 14 and the source / drain of the second active region due to the remaining silicide formation oxide layer 16.
한편, 상기 본 발명의 일 실시예에서는 실리사이드가 형성되지 않는 상기 제2액티브영역에 산화공정시 산화막의 형성을 촉진하는 불순물을 이온주입하였으나, 본 발명의 다른 실시예로는 상기 감광막 패턴(PR11)을 제2액티브영역 상에 형성하고, 제1액티브영역에 산화공정시 산화막의 형성을 억제하는 불순물을 이온주입하여도 동일한 결과를 얻을 수 있다.Meanwhile, in one embodiment of the present invention, an ion is implanted into the second active region in which no silicide is formed, to promote the formation of an oxide film during an oxidation process. In another embodiment of the present invention, the photosensitive film pattern PR11 is implanted. Is formed on the second active region, and the same result can be obtained by ion implantation of impurities in the first active region which inhibit the formation of the oxide film during the oxidation process.
상기 산화공정시 산화막의 형성을 억제하는 불순물로는 질소(N)를 사용하는 것이 고려된다.It is considered to use nitrogen (N) as an impurity that suppresses the formation of an oxide film during the oxidation process.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 실리사이드가 형성되는 제1액티브영역과 형성되지 않는 제2액티브영역 상에 불순물 이온주입을 통해 서로다른 두께를 갖는 산화막을 형성하고, 세정을 통해 제1액티브영역의 산화막만을 제거한 후, 살리사이드 공정을 수행하여 제1액티브영역에만 실리사이드를 형성함에 따라 소자격리영역의 손실에 따른 접합누설전류를 최소화할 수 있으며, 게이트산화막의 손상을 효과적으로 방지하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention as described above, an oxide film having a different thickness is formed on the first active region in which silicide is formed and the second active region in which no silicide is formed through impurity ion implantation, and then washed. By removing only the oxide layer of the first active region, and then performing a salicide process to form silicide only in the first active region, it is possible to minimize the junction leakage current due to the loss of the device isolation region, and effectively prevent damage to the gate oxide layer. There is an effect that can improve the reliability of the semiconductor device.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100368310B1 (en) * | 2000-12-29 | 2003-01-24 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100676198B1 (en) * | 2000-10-04 | 2007-01-30 | 삼성전자주식회사 | Semiconductor device fabricating method for reducing recess of isolation field in salicide layer |
| KR100831259B1 (en) * | 2006-12-29 | 2008-05-22 | 동부일렉트로닉스 주식회사 | Method of fabricating cmos device |
| KR100955921B1 (en) * | 2003-01-21 | 2010-05-03 | 매그나칩 반도체 유한회사 | Method for forming salicide of semiconductor device |
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| KR100927787B1 (en) | 2003-01-24 | 2009-11-20 | 매그나칩 반도체 유한회사 | Semiconductor device manufacturing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100676198B1 (en) * | 2000-10-04 | 2007-01-30 | 삼성전자주식회사 | Semiconductor device fabricating method for reducing recess of isolation field in salicide layer |
| KR100368310B1 (en) * | 2000-12-29 | 2003-01-24 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100955921B1 (en) * | 2003-01-21 | 2010-05-03 | 매그나칩 반도체 유한회사 | Method for forming salicide of semiconductor device |
| KR100831259B1 (en) * | 2006-12-29 | 2008-05-22 | 동부일렉트로닉스 주식회사 | Method of fabricating cmos device |
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