KR100399446B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR100399446B1 KR100399446B1 KR10-1999-0060934A KR19990060934A KR100399446B1 KR 100399446 B1 KR100399446 B1 KR 100399446B1 KR 19990060934 A KR19990060934 A KR 19990060934A KR 100399446 B1 KR100399446 B1 KR 100399446B1
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- Prior art keywords
- insulating film
- film
- forming
- organic low
- spacer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- -1 LDD ion Chemical class 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000037452 priming Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 고유전 게이트절연막-금속게이트전극을 사용하여 게이트전극이 층간절연막에 매립되는 다마신 방법의 MOSFET에서 유기저유전막 패턴의 측벽에 절연막 스페이서를 형성하고, 층간절연막으로 다른 부분을 채운후에 절연막 스페이서 내부에 고유전 게이트절연막-금속게이트전극을 형성한 후, 게이트전극의 상부에 캡층을 형성하였으므로, 후속의 자기정렬 콘택 공정을 안정적으로 진행할 수 있어 소자의 고집적화에 유리하다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, an insulating film spacer is formed on a sidewall of an organic low dielectric film pattern in a MOSFET of a damascene method in which a gate electrode is embedded in an interlayer insulating film using a high dielectric gate insulating film-metal gate electrode. After filling the other portion with the interlayer insulating film, the high-k gate insulating film-metal gate electrode was formed inside the insulating film spacer, and then a cap layer was formed on the gate electrode, so that the subsequent self-aligned contact process can be stably performed. It is advantageous for high integration.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOS FET라 칭함)의 게이트전극을 절연막에 매립시키는 다마신(damascene) 공정에서 유기 저유전(organic low-k)막을 사용하여 게이트전극을 용이하게 형성하고 게이트전극의 상부에 캡층을 구비하여 자기정렬 콘택을 안정적으로 실시할 수 있어 소자의 고집적화에 유리한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an organic low dielectric (Damascene) process in which a gate electrode of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET) is embedded in an insulating film. The present invention relates to a method of fabricating a semiconductor device, which is advantageous in forming a gate electrode by using an organic low-k) film and having a cap layer on the gate electrode to stably perform self-aligned contacts, which is advantageous for high integration of the device.
반도체소자가 고집적화되어 감에 따라 소자의 크기를 감소시키기 위하여 MOSFET의 게이트전극이나 소오스/드레인영역 및 이들과의 콘택등 공정 전반의 디자인 룰이 감소되고 있으나, 채널폭의 감소는 문턱전압 감소와 트랜지스터 펀치를 유발하게 된다.As semiconductor devices become more integrated, the overall design rules such as gate electrodes, source / drain regions, and contacts with MOSFETs are reduced to reduce the size of the devices. Will cause a punch.
또한 p 또는 n형 반도체기판에 n 또는 p형 불순물로 형성되는 pn 접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다. 따라서 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면 확산에 의한 짧은채널효과(short channel effect)를 방지하기 위하여 채널이온주입과 소오스/드레인영역 이온주입시 에너지를 감소시켜 측면 확산을 방지하는데, 이때 접합깊이가 얕게 형성되어 소자의 동작 특성을 저하시킨다.In addition, a pn junction formed of n or p type impurity on a p or n type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in semiconductor devices with reduced channel width, energy is reduced during channel ion implantation and source / drain region ion implantation in order to prevent short channel effects caused by side diffusion from the diffusion region. At this time, the junction depth is formed to be shallow to reduce the operating characteristics of the device.
짧은 채널효과가 발생되면 게이트전극의 폭 변화에 대하여 문턱전압이 심하게 변화되어 문턱전압 조절이 어렵게되어 공정마진이 적어지는 문제점이 있다.When the short channel effect occurs, the threshold voltage is severely changed with respect to the width change of the gate electrode, which makes it difficult to control the threshold voltage, thereby reducing the process margin.
더욱이 DRAM의 디자인룰이 0.13㎛ 이하로 감소함에 따라 고유전 게이트절연막-금속게이트전극을 사용하는 구조가 연구되고 있으며, 상기의 고유전 게이트절연막-금속게이트전극 구조의 MOSFET를 형성하는 공정에서는 고온 공정시에 고유전 게이트절연막과 금속게이트전극가 영향을 받아 열화되는 문제점이 있어, 게이트전극을 절연막에 매립시키는 다마신(damascene) 공정을 사용하는 금속재배치 게이트 공정(metal replacement gate process; 이하 MRG 공정이라 칭함)이 개발되고 있다.Furthermore, as DRAM design rules are reduced to 0.13 µm or less, structures using high-k gate insulating film-metal gate electrodes have been studied. In the process of forming MOSFETs of the high-k gate insulating film-metal gate electrode structures, a high temperature process is used. The high dielectric gate insulating film and the metal gate electrode are deteriorated due to influences at the time. Thus, a metal replacement gate process using a damascene process in which the gate electrode is embedded in the insulating film is referred to as an MRG process. ) Is being developed.
도 1은 종래 기술에 따른 반도체소즈의 단면도로서, MRG 공정의 예이다.1 is a cross-sectional view of a semiconductor source according to the prior art, which is an example of an MRG process.
먼저, 반도체기판(10)에서 MOSFET의 채널로 예정되어있는 부분을 사이에 두고, 질화막 재질의 절연막 스페이서(12)들이 형성되어있으며, 상기 채널로 예정된 부분을 노출시키는 층간절연막(14)이 전면에 형성되어있고, 상기 반도체기판(10)의 노출된 채널영역에 알루미늄 산화막(Al2O3) 재질의 고유전 게이트절연막(16)과 WN/W 적층 구조의 금속게이트전극(18)이 형성되어있으며, 상기 절연막 스페이서(12) 양측의 반도체기판(10)에 소오스/드레인영역(도시되지 않음)이 형성되어 있다.First, the insulating film spacers 12 made of nitride film are formed with a portion of the semiconductor substrate 10 arranged as a channel of the MOSFET, and the interlayer insulating film 14 exposing the portion scheduled to the channel is disposed on the front surface of the semiconductor substrate 10. In the exposed channel region of the semiconductor substrate 10, a high-k gate insulating film 16 made of aluminum oxide (Al 2 O 3 ) material and a metal gate electrode 18 having a WN / W stacked structure are formed. Source / drain regions (not shown) are formed in the semiconductor substrate 10 on both sides of the insulating film spacer 12.
여기서 다마신 공정에 의해 금속게이트전극(18)의 대부분이 층간절연막(14)에 묻히게 되나, 소자의 디자인룰에 따라 공정을 진행하게 되면, 금속게이트전극(18)이 층간절연막(14)의 상부로 노출되게 되며, 이 경우 게이트전극의 상부에 식각장벽층인 캡층이 별로도 존재하지 않아 자기정렬 콘택 공정시에 게이트전극이 다른 배선과 단락되는 문제점이 있다.Here, most of the metal gate electrode 18 is buried in the interlayer insulating film 14 by the damascene process. However, when the process is performed according to a design rule of the device, the metal gate electrode 18 is formed on the upper portion of the interlayer insulating film 14. In this case, since the cap layer, which is an etch barrier layer, is not present on the gate electrode, there is a problem in that the gate electrode is shorted with other wiring during the self-aligned contact process.
상기의 문제점을 해결하기 위해서는 소자의 면적을 증가시켜야하나 이는 소자의 고집적화를 방해하게 된다.In order to solve the above problem, the area of the device must be increased, but this hinders the high integration of the device.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 유기저유전막으로 게이트 패턴을 형성하고, 그 양측에 절연막 스페이서를 형성한후 화학기계적연마(chemical-mechaniscal polishing ; 이하 CMP라 칭함)과 다마신 공정에 의해 고유전 게이트절연막-금속게이트전극 구조의 MOSFET를 형성하여 소자의 고집적화에 유리한 안정적인 동작 특성을 가지는 반도체소자의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a gate pattern with an organic low-k dielectric film, and to form insulating film spacers on both sides thereof, followed by chemical-mechaniscal polishing (hereinafter referred to as CMP). And a damascene process to form a MOSFET having a high-k gate insulating film-metal gate electrode structure, thereby providing a method of manufacturing a semiconductor device having stable operation characteristics for high integration of the device.
도 1은 종래 기술에 따른 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 제조공정도.2A to 2F are manufacturing process diagrams of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 반도체기판 12 : 절연 스페이서10 semiconductor substrate 12 insulating spacer
14 : 층간절연막 16 : 고유전 게이트절연막14 interlayer insulating film 16 high-k gate insulating film
18 : 금속게이트전극 20 : 제1산화막18 metal gate electrode 20 first oxide film
22 : 유기저유전막 24 : 제2산화막22: organic low dielectric film 24: second oxide film
26 : 감광막 패턴 28 : 금속층26 photosensitive film pattern 28 metal layer
30 : 캡층30: cap layer
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은,Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
반도체기판상에 게이트패턴 마스크로 유기저유전막 패턴을 형성하는 공정과,Forming an organic low dielectric film pattern on the semiconductor substrate using a gate pattern mask;
상기 유기저유전막 패턴의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the organic low dielectric film pattern;
상기 절연막 스페이서 바깥쪽에 층간절연막을 형성하고, 유기저유전막을 제거하여 반도체기판의 채널 부분으로 예정되어있는 부분을 노출시키는 공정과,Forming an interlayer insulating film outside the insulating film spacer, removing the organic low-k dielectric film, and exposing a portion intended as a channel portion of the semiconductor substrate;
상기 구조의 전표면에 고유전 게이트절연막과 금속막을 순차적으로 형성하는 공정과,Sequentially forming a high-k gate insulating film and a metal film on the entire surface of the structure;
상기 금속막을 전면 식각하여 상기 절연막 스페이서 내부에 일정두께가 남도록하여 금속게이트전극을 형성하는 공정과,Forming a metal gate electrode by etching the entire surface of the metal film so that a predetermined thickness remains inside the insulating film spacer;
상기 금속게이트전극 상부에 절연막 패턴으로된 캡층을 형성하는 공정을 구비함에 있다.And forming a cap layer formed of an insulating layer pattern on the metal gate electrode.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본발명에 따른 반도체소자의 제조 공정도이다.2A to 2F are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 실리콘 웨이퍼 반도체기판(10)상에 제1산화막(20)과 유기저유전막(22) 및 제2산화막(24)을 순차적으로 형성한 후, 게이트 패턴닝 마스크를 사용하여 상기 제2산화막(24)상에 감광막 패턴(26)을 형성한다. 여기서 상기 제1 및제2산화막(20,24)은 유기저유전막(22)의 마스크층으로서 50∼200Å 정도로 비교적 얇게 형성되며, 상기 유기저유전막(22)은 코팅-베이킹-쿠어링 공정으로 형성된다. (도 2a 참조).First, the first oxide film 20, the organic low dielectric film 22, and the second oxide film 24 are sequentially formed on the silicon wafer semiconductor substrate 10, and then the second oxide film ( The photosensitive film pattern 26 is formed on 24. Here, the first and second oxide films 20 and 24 are formed relatively thin as a mask layer of the organic low dielectric film 22, about 50 to 200 microns, and the organic low dielectric film 22 is formed by a coating-baking-curing process. . (See FIG. 2A).
그다음 상기 감광막 패턴(26)을 마스크로 노출되어있는 제2산화막(24)과 유기저유전막(22)을 건식식각 방법으로 순차적으로 제거하여 제2산화막(24), 유기저유전막(22) 및 제1산화막(20) 패턴을 형성하되, 상기 유기저유전막(22) 식각공정시 감광막 패턴(26)도 함께 제거되며, 상기 제2산화막(24)이 유기저유전막(22) 식각시 식각장벽이 된다. (도 2b 참조).Next, the second oxide layer 24 and the organic low dielectric layer 22, which are exposed to the photoresist layer pattern 26 as a mask, are sequentially removed by a dry etching method, thereby forming the second oxide layer 24, the organic low dielectric layer 22, and the second oxide layer 22. The first oxide layer 20 is formed, and the photoresist layer pattern 26 is also removed during the organic low dielectric layer 22 etching process, and the second oxide layer 24 becomes an etch barrier when the organic low dielectric layer 22 is etched. . (See FIG. 2B).
그후, 상기 패턴들을 마스크로 소오스/드레인영역 형성을 위한 LDD 이온주임을 실시하고, 상기 패턴들의 측벽에 질화막이나 과실리콘 산화질화막 재질의 절연막 스페이서(12)를 형성하고, 고농도 이온주입으로 소오스/드레인영역(도시되지 않음)을 형성한다. 이때 상기 스페이서 식각 공정은 기판의 손상을 최소로 하기 위하여 C-H-F계 가스 플라즈마를 사용한다.Subsequently, LDD ion priming for forming a source / drain region is performed using the patterns as a mask, and an insulating film spacer 12 made of nitride or persilicon oxynitride is formed on the sidewalls of the patterns, and source / drain is formed by high concentration ion implantation. Form an area (not shown). At this time, the spacer etching process uses a C-H-F-based gas plasma to minimize damage to the substrate.
그다음 상기 구조의 전표면에 산화막 재질의 층간절연막(14)을 두껍게 형성하고, CMP 공정을 실시하여 절연막 스페이서(12) 상부의 층간절연막(14)을 제거하여 평탄화시켜, 제2산화막(24) 패턴이나 유기저유전막(22)을 노출시키고, 다시 제2산화막(24)과 유기저유전막(22) 및 제1산화막(20) 패턴을 순차적으로 제거하여 채널 부분을 노출시킨다. 이때 상기 유기저유전막(22) 패턴 제거 공정은 습식이나 건식 방법으로 제거하는데, 건식의 경우에는 통상의 감광막 제거 공정을 사용한다. (도 2c 참조).Then, an interlayer insulating film 14 made of an oxide film is thickly formed on the entire surface of the structure, and a CMP process is performed to remove and planarize the interlayer insulating film 14 on the insulating film spacer 12 to form a second oxide film 24 pattern. In addition, the organic low dielectric layer 22 is exposed, and the second oxide layer 24, the organic low dielectric layer 22, and the first oxide layer 20 are sequentially removed to expose the channel portion. At this time, the organic low-k dielectric layer 22 pattern removal process is removed by a wet or dry method, in the case of dry is used a conventional photosensitive film removal process. (See FIG. 2C).
그후, 상기 구조의 전표면에 알루미늄 산화막 재질의 고유전 게이트절연막(16)과 WN/W 구조의 금속층(28)을 순차적으로 형성한다. (도 2d 참조).Thereafter, the high dielectric gate insulating film 16 of aluminum oxide and the metal layer 28 of the WN / W structure are sequentially formed on the entire surface of the structure. (See FIG. 2D).
그다음 상기 금속층(28)을 전면 에치백하여 절연막 스페이서(12)의 내측에 일정 두께 만이 남도록하여 금속층(28) 패턴으로된 매립된 금속게이트전극(18)을 형성한다. 이때 상기 식각 공정시 금속층(28)과 고유전 게이트절연막(16)과의 식각선택비를 증가시키기 위하여 NF3나 SF6등의 플루오루 함유 가스를 Ar이나 He등의 불활성 가스를 플라즈마 안정화 가스로하여 혼합 가스 플라즈마로 실시한다. (도 2e 참조).Next, the metal layer 28 is etched back to form a buried metal gate electrode 18 having a metal layer 28 pattern so that only a predetermined thickness remains inside the insulating film spacer 12. At this time, in order to increase the etching selectivity between the metal layer 28 and the high-k gate insulating film 16 during the etching process, a fluorine-containing gas such as NF 3 or SF 6 is used as an inert gas such as Ar or He as a plasma stabilizing gas. It is carried out by a mixed gas plasma. (See FIG. 2E).
그후, 상기 금속게이트전극(18)의 상부에 캡층(30)을 형성한다. 상기 캡층(30)은 질화막이나 과실리콘 산화질화막을 전면 도포하고 전면식각하여 형성하고, 그다음 층간절연막(14)상의 고유전 게이트절연막(16)을 제거하여 MOSFET를 완성한다. (도 2f 참조).Thereafter, a cap layer 30 is formed on the metal gate electrode 18. The cap layer 30 is formed by coating the entire surface of the nitride film or the silicon nitride oxynitride film and etching the entire surface. Then, the high-k gate insulating film 16 on the interlayer insulating film 14 is removed to complete the MOSFET. (See FIG. 2F).
그다음 도시되어있지는 않으나, 상기 구조의 전표면에 평탄화층을 형성하고, 자기정렬 콘택을 형성하게 되는데, 콘택 식가공정시 캡층 및 스페이서와 평탄화층 및 층간절연막간의 식각선택비를 증가시키기 위하여 과탄소 C-F계 가스를 사용하거나 CH3F, CH2F2또는 C2HF5등의 C-H-F계 가스와 혼합한 가스를 안정화가스와 섞어 사용하여 안정적인 자기정렬 콘택을 얻을 수 있다.Then, although not shown, a planarization layer is formed on the entire surface of the structure and a self-aligned contact is formed. In order to increase the etching selectivity between the cap layer and the spacer, the planarization layer, and the interlayer insulating layer during the contact etching process, A stable self-aligned contact can be obtained by using a gas or by using a gas mixed with a CHF gas such as CH 3 F, CH 2 F 2 or C 2 HF 5 with a stabilizing gas.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은 다마신 공정에 의해 게이트가 층간절연막에 매립되는 구조의 MOSFET에서 유기저유전막 패턴과 CMP 방법을 이용하여 안정적으로 소자를 형성하여, 소자의 고집적화에 유리한 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a device is stably formed by using an organic low-k dielectric pattern and a CMP method in a MOSFET having a gate embedded in an interlayer insulating film by a damascene process. There is an advantage in terms of high integration.
Claims (11)
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| US9337293B2 (en) | 2013-02-22 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having electrode and manufacturing method thereof |
| US9941372B2 (en) | 2013-02-22 | 2018-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having electrode and manufacturing method thereof |
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