KR100831259B1 - Method of fabricating cmos device - Google Patents

Abstract

A method of manufacturing a CMOS device is provided to prevent contact resistance between a resistor of a gate pattern and a contact plug from being increased. A first conductive type active region(a) and a second conductive type active region(b) are defined in a semiconductor substrate(50). A first gate pattern(56a) and a second gate pattern(56b) are formed on the first and second conductive type active regions, respectively. The first conductive type active region is implanted with a second conductive type impurity using the first gate pattern, and a counterdoping layer(58) of a second conductive impurity is formed on the first gate pattern. The second conductive type active region is implanted with first conductive type impurity using the second gate pattern. The first gate pattern is implanted with the first conductive type impurity to remove the counterdoping layer.

Description

Method of manufacturing CMOS device {Method of Fabricating CMOS Device}

1 to 4 are process cross-sectional views for explaining a method for manufacturing a CMOS device according to the prior art.

5 to 7 are process cross-sectional views illustrating a method of manufacturing a CMOS device according to a first embodiment of the present invention.

8 to 10 are cross-sectional views illustrating a method of manufacturing a CMOS device according to a second embodiment of the present invention.

11 to 13 are cross-sectional views illustrating a method of manufacturing a CMOS device according to a third embodiment of the present invention.

The present invention relates to a method for manufacturing a CMOS device, and more particularly, to a method for manufacturing a CMOS device for preventing the anti-doping layer from being formed in a gate pattern.

In general, as the doping concentration of the semiconductor film increases, the contact surface between the metal and the semiconductor film forms a ohmic layer, thereby lowering the resistance value. Therefore, it is advantageous that the source region, the drain region, and the gate electrode to which the contact plug is in contact have a high doping concentration. In order to lower the resistance, it is possible to consider forming a silicide film in the gate electrode and the source / drain regions in the CMOS device. However, due to the increase in manufacturing cost and the increase in the junction leakage, the application to the CMOS device with low power consumption and low standby power is limited. have.

In addition, since the CMOS device includes NMOS transistors and PMOS transistors arranged on a semiconductor substrate, a doping concentration is lowered in a part of the gate electrode in the manufacturing process, and thus resistance is increased.

1 to 4 are process cross-sectional views for explaining a method of manufacturing a conventional CMOS device.

Referring to FIG. 1, a CMOS device is formed on a semiconductor substrate 10 in which a first conductive type active region a and a second conductive type active region b are defined. The first conductivity type active region a and the second conductivity type active region b are determined by a well region formed in the semiconductor substrate 10 and are isolated by the device isolation layer 12. The first conductivity type active region a may be an n-type active region in which a PMOS transistor is to be formed, and the second conductivity type active region b may be a p-type active region in which an NMOS transistor is to be formed.

The gate insulating layer 14 is formed on the substrate of the first conductive type active region a and the second conductive type active region b, and the first gate pattern 16a and the second gate pattern 14 are formed on the gate insulating layer 14. The gate pattern 16b is formed. The first gate pattern 16a and the second gate pattern 16b may be formed of a first conductivity type, that is, n-type polysilicon.

Referring to FIG. 2, the photoresist film 18 covering the active region b and the second gate pattern 16b of the second conductivity type is formed, and the first gate pattern 16a is used as an ion implantation mask. A source region and a drain region 22 of the second conductivity type are formed in the first conductivity type active region a. At this time, the impurity ions 20 of the second conductivity type are implanted in the upper portion of the first gate pattern 16a as well as the semiconductor substrate of the first active region a, thereby forming an anti-doping layer on the first gate pattern 16a. 24). The anti-doping layer 24 is a layer in which the second conductivity type impurities are injected onto the first gate pattern 16a doped with the first conductivity type impurity to lower the impurity concentration. The contact resistance with the contact plug to be high is also high.

Referring to FIG. 3, the photoresist film 18 is removed to form another photoresist film 26 covering the active region a of the first conductivity type and the first gate pattern 16a. The impurity ions 28 of the first conductivity type are implanted into the active region b of the second conductivity type using the second gate pattern 16b as an ion implantation mask. As a result, the source region and the drain region 30 of the first conductivity type are formed in the active region b of the second conductivity type. The impurity ions 28 of the first conductivity type may be implanted in the upper portion of the second gate pattern 16b, but rather, the impurity concentration of the first conductivity type is increased to increase the sheet resistance of the second gate pattern and the contact resistance with the contact plug. Can be lowered.

Referring to FIG. 4, the photoresist film 26 is removed, an interlayer insulating film 38 is formed on the entire surface of the substrate, and the first gate pattern 16a and the second gate pattern 16b are penetrated through the interlayer insulating film 38. The contact plug 40 and the wiring layer 42 respectively connected to) are formed.

As shown, an anti-doping layer 24 is formed on the first gate pattern 16b to increase the contact resistance Rs of the contact plug 40 and the anti-doping layer 24, thereby degrading the performance of the device. Can be.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a CMOS device capable of preventing the formation of an anti-doping layer on a gate pattern.

Another object of the present invention is to provide a method of manufacturing a CMOS device without an anti-doping layer on a gate pattern in contact with a contact plug.

In order to achieve the above technical problem, the present invention defines a first conductive type active region and a second conductive type active region in a semiconductor substrate, and includes a first conductive type active region and a first conductive type active region on a first conductive type active region and a second conductive type active region. Forming a first gate pattern and a second gate pattern of a conductivity type. Using the first gate pattern as an ion implantation mask, a second conductivity type impurity is implanted into the first conductivity type active region, and an anti-doping layer of the second conductivity type impurity is formed on the first gate pattern. Impurities of the first conductivity type are implanted into the second conductivity type active region using the second gate pattern as an ion implantation mask.

And optionally implanting impurities of a first conductivity type on top of the first gate pattern to remove the anti-doping layer. In the present invention, by removing the anti-doping layer generated during the formation of the source region and the drain region in a subsequent process, the excellent CMOS device in which the anti-doping layer does not exist in the upper part of the gate pattern in the structure of the final CMOS device is provided. Can be implemented.

In another embodiment of the present invention, the anti-doping layer may be prevented from being formed on the gate pattern. Specifically, a first conductive type active region and a second conductive type active region are defined in a semiconductor substrate, and a gate conductive film of a first conductive type is formed on the first and second conductive type active regions. An ion implantation mask film is formed on the first conductivity type gate conductive film. The ion implantation mask layer and the gate conductive layer are patterned to form a first gate pattern and a second gate pattern of the first conductivity type on the first and second conductivity type active regions, respectively. An impurity of a second conductivity type is selectively implanted into the first conductivity type active region using an ion implantation mask film. Impurities of the first conductivity type are implanted into the second conductivity type active region using the second gate pattern as an ion implantation mask. In the present invention, the ion implantation mask film may be used as an etch stop layer of the interlayer insulating film in subsequent contact plug formation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Example 1)

5 to 7 are process cross-sectional views illustrating a method of manufacturing a CMOS device according to a first embodiment of the present invention.

Referring to FIG. 5, the first conductive type active region a and the second conductive type active region b are defined in the semiconductor substrate 50. The first conductivity type active region a and the second conductivity type active region b are determined by a well region formed in the semiconductor substrate 50 and are isolated by the device isolation layer 52. The first conductivity type active region a may be an n-type active region in which a PMOS transistor is to be formed, and the second conductivity type active region b may be a p-type active region in which an NMOS transistor is to be formed.

A gate insulating film 54 is formed on the substrate of the first conductive type active region a and the second conductive type active region b, and the first gate pattern 56a and the second gate are formed on the gate insulating layer 54. The pattern 56b is formed. The first gate pattern 56a and the second gate pattern 56b may be formed of a first conductivity type, that is, n-type polysilicon.

As in the prior art, a second conductivity type source / drain region 60p is formed by implanting a second conductivity type impurity into the first conductivity type active region on both sides of the first gate pattern 56a, and the second gate. Impurities of the first conductivity type are implanted into the second conductivity type active regions on both sides of the pattern 56b to form the first conductivity source / drain regions 60n. In this case, an anti-doping layer 58 may be formed on the first gate pattern 56a in which the second conductivity type impurity is implanted.

A mask film 62 having excellent gap fill characteristics is formed on the entire surface of the resultant in which the anti-doping layer 58 is formed. The material used as the mask layer 62 may be a material having a narrow gap region between the gate patterns and a material having an etch selectivity with the lower structure so as to be easily removed later. As the most suitable material, a photoresist film may be used. The photoresist film is uniformly coated on the entire surface of the substrate, and thus has excellent gap fill characteristics and easy removal.

Referring to FIG. 6, the mask layer 62 is planarized to form the first conductive type active region a, the second conductive type active region b, and the first and second gate patterns 56a and 56b. A flatly covered mask film 62a is formed.

As shown, the mask layer 62 has a thickness above the first and second gate patterns 56a and 56b smaller than a thickness above the peripheral active region. Accordingly, the first conductive type impurity 64 is implanted through the mask layer 62, and the first and second gate patterns are implanted by implanting the impurity at a value smaller than the thickness of the mask layer over the active region. The first conductivity type impurity may be selectively injected only at the top of the. As a result, the anti-doping layer 58 may be doped with the first conductivity type impurity again to form a rather high concentration of the first conductivity type impurity layer 66a, and a higher concentration on the second gate pattern 56b. The first conductivity type impurity layer 66b may be formed.

Referring to FIG. 7, the mask layer 62 is removed to form an interlayer insulating layer 68 on the entire surface of the substrate. Contact plugs 70 connected to the first gate pattern 56a and the second gate pattern 56b are formed through the interlayer insulating film 68, and the wiring layer 72 connected to the contact plug 70 is formed. Integrated circuits can be implemented.

(Example 2)

8 to 10 are cross-sectional views illustrating a method of manufacturing a CMOS device according to a second embodiment of the present invention.

Referring to FIG. 8, the method for manufacturing the CMOS device according to the second embodiment may have a feature of preventing the anti-doping layer from being formed. An isolation layer 52 is formed on the semiconductor substrate 50, and a gate insulation layer 54 is formed on the active region surface defined by the isolation layer 52. A first conductive gate conductive film 56 is formed on the gate insulating film 54, and an ion implantation mask film 57 is formed on the first conductive gate conductive film 56. The ion implantation mask film 57 may be formed of an oxide film, and preferably, the gate conductive film 56 is oxidized by a high-speed heat treatment (RTA).

Referring to FIG. 9, the first gate pattern 56a is formed in the active region a of the first conductivity type by patterning the ion implantation mask layer 57 and the gate conductivity layer 56 of the first conductivity type. A second gate pattern 56b is formed in the active region b of the second conductivity type.

A photoresist film 62p is formed in order to form the source / drain regions 60p of the second conductivity type in the active region a of the first conductivity type. Even when the second conductivity type impurity 64 is implanted into the active region a of the first conductivity type, the second conductivity type impurity is implanted into the first gate pattern 56a by the ion implantation mask pattern 57a, thereby lifting the weight. The formation of the wooping layer can be prevented.

Referring to FIG. 10, the source / drain regions 60n of the first conductivity type are formed in the second active regions b on both sides of the second gate pattern 56b in the usual manner, and the interlayer insulating film 68 is formed. And forming the contact plug 70 and the wiring layer 72.

(Example 3)

11 to 13 are process cross-sectional views illustrating a third embodiment of the present invention.

Referring to FIG. 11, the capping film 80 is conformally formed on the entire surface of the substrate on which the anti-doping layer 58 is formed on the first gate pattern 56a. The capping film 80 may be formed of a silicon oxide film or a silicon nitride film, and preferably, about 500 to 1500 angstroms.

Referring to FIG. 12, an ion implantation mask 82 having an upper portion of the first gate pattern 56a opened is formed on the resultant product on which the capping layer 80 is formed. The first dopant layer 84 is implanted into the reverse doping layer 58 by using the ion implantation mask 82 to remove the reverse doping layer, and further, the first gate dopant layer having a high concentration of It can also be formed in the upper portion (56a). The ion implantation mask 82 may be formed of a photoresist film. At this time, the width of the open region 86 of the ion implantation mask 82 is greater than the width of the first gate pattern 56a so that the reverse doping layer 58 is covered with the ion implantation mask due to misalignment. It is desirable to prevent.

In the present invention, since the capping layer 80 is formed with both sides of the first gate pattern 56a with a predetermined thickness, the capping layer 80 may be formed even when the open region 86 of the ion implantation mask is misaligned with a predetermined width M. Infiltration of the impurity ions 84 into the conductive source / drain fill 60p can be suppressed in the capping film 80. That is, the open region 86 of the ion implantation mask 82 may be formed with a misalignment margin equal to the thickness of the capping film 80.

Referring to FIG. 13, an interlayer insulating film 68 is formed on the capping film 80, and the contact plug 70 and the wiring layer 72 connected to the first gate pattern 56a and the second gate pattern 56b, respectively. ).

In the forming of the contact plug 70, the interlayer insulating layer 68 and the capping layer 80 are etched to form contact holes (not shown) in which the first gate pattern 56a and the second gate pattern 56b are exposed. Form. In this case, when the capping layer 80 is formed of a material having an etching selectivity with respect to the interlayer insulating layer 68, the capping layer 80 becomes an etch stop layer while the thick interlayer insulating layer 68 is etched to overetch the underlying structure. It also has the effect of preventing.

As described above, according to the present invention, it is possible to prevent the anti-doping layer from being formed on the gate pattern, thereby preventing the resistance of the gate pattern and the contact resistance with the contact plug from increasing, and the CMOS having excellent operating characteristics. An apparatus may be provided.

In addition, even when the anti-doping layer is formed on the gate pattern, impurities are injected into the anti-doping layer in a subsequent process to remove the anti-doping layer or increase the impurity concentration to increase the sheet resistance of the gate pattern and the contact resistance with the contact plug. It can also be lowered.

Claims (14)

Defining a first conductivity type active region and a second conductivity type active region in the semiconductor substrate; Forming a first gate pattern and a second gate pattern of the first conductivity type on the first conductivity type active region and the second conductivity type active region, respectively Implanting a second conductivity type impurity into the first conductivity type active region by using the first gate pattern as an ion implantation mask, and forming an anti-doping layer of a second conductivity type impurity on the first gate pattern step; Implanting impurities of a first conductivity type into the second conductivity type active region using the second gate pattern as an ion implantation mask; And Selectively implanting impurities of a first conductivity type on top of the first gate pattern to remove the anti-doping layer. In claim 1, And the first gate pattern and the second gate pattern are formed of a conductive film doped with n-type impurities. In claim 1, Removing the anti-doping layer, Forming a mask layer on which the thickness of the first gate pattern and the second gate pattern is thinner than that of the active region of the first conductivity type and the active region of the second conductivity type; And And implanting impurities of a first conductivity type into the first gate pattern and the second gate pattern through the mask layer. In claim 3, Forming the mask film, Coating a photoresist film on the entire surface of the semiconductor substrate; And And planarizing the photoresist layer to form a mask layer covering the first and second conductive patterns and the first and second gate patterns. In claim 3, Injecting the impurity of the first conductivity type, And a projection depth of the first conductivity type impurity is smaller than a thickness of the mask film. In claim 1, Removing the anti-doping layer, Forming an ion implantation mask on which the first gate pattern is opened; And Selectively implanting first conductivity type impurities into the first gate pattern using the ion implantation mask. In claim 6, Before forming the ion implantation mask, And forming a capping film conformally covering the first and second active regions and the first and second gate patterns on the semiconductor substrate. In claim 7, The width of the open area of the ion implantation mask is larger than the width of the first gate pattern manufacturing method of the CMOS device. In claim 7, The boundary of the open region of the ion implantation mask is formed so as to have a misalignment margin as the thickness of the capping film. In claim 6, And the ion implantation mask is formed of a photoresist film. The method of claim 7, wherein And forming an interlayer dielectric layer on the capping layer, wherein the capping layer is formed of a material having an etch selectivity with respect to the interlayer dielectric layer. Defining a first conductivity type active region and a second conductivity type active region in the semiconductor substrate; Forming a gate conductive film of a first conductivity type on the first and second conductivity type active regions; Forming an ion implantation mask film on the first conductivity type gate conductive film; Patterning the ion implantation mask layer and the gate conductive layer to form a first gate pattern and a second gate pattern of a first conductivity type on the first and second conductivity type active regions, respectively Selectively implanting a second conductivity type impurity into the first conductivity type active region using the ion implantation mask film; And And implanting impurities of a first conductivity type into the second conductivity type active region using the second gate pattern as an ion implantation mask. In claim 12, The ion implantation mask film is a method for manufacturing a CMOS device, characterized in that the oxide film. In claim 12, Forming the ion implantation mask film, And oxidizing the gate conductive film by high-speed heat treatment (RTA).

Images