KR20000045466A - Method for fabricating dual gate electrode - Google Patents
Method for fabricating dual gate electrode Download PDFInfo
- Publication number
- KR20000045466A KR20000045466A KR1019980062024A KR19980062024A KR20000045466A KR 20000045466 A KR20000045466 A KR 20000045466A KR 1019980062024 A KR1019980062024 A KR 1019980062024A KR 19980062024 A KR19980062024 A KR 19980062024A KR 20000045466 A KR20000045466 A KR 20000045466A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- gate
- conductor
- forming
- gate oxide
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000009977 dual effect Effects 0.000 title abstract 3
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 10
- 239000011737 fluorine Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 9
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 230000006866 deterioration Effects 0.000 abstract description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 2
- 239000006117 anti-reflective coating Substances 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 이중 게이트전극 형성방법에 관한 것으로, 특히 높은 처리속도를 필요로 하는 차세대 고집적 소자에서 이용되는 이중 게이트전극, 보다 상세하게는 이중 게이트산화막을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a double gate electrode, and more particularly, to a method of manufacturing a double gate electrode, and more particularly, a double gate oxide film used in a next-generation highly integrated device requiring a high processing speed.
종래의 이중 게이트 산화막의 제조는 필드산화막이 형성된 실리콘 기판 상에 열산화방법으로 1차적으로 게이트산화막을 형성한 후, 감광막을 이용하여 제2게이트산화막이 형성될 부분의 산화막을 제거하고, 감광막을 제거한 다음, 제2게이트산화막을 상기 제1게이트산화막보다 두껍게 형성한다.In the conventional manufacturing of the double gate oxide film, the gate oxide film is first formed on the silicon substrate on which the field oxide film is formed by a thermal oxidation method, and then the oxide film of the portion where the second gate oxide film is to be formed is removed using the photosensitive film, and the photosensitive film is removed. After removal, the second gate oxide film is formed thicker than the first gate oxide film.
그러나, 이러한 방법으로는 제1게이트산화막과 제2게이트산화막의 상이한 두께 조절이 쉽지 않은 문제점이 있게 된다. 특히 제1게이트산화막의 두께를 조절하기가 힘들어지게 된다.However, this method has a problem that it is not easy to control the different thickness of the first gate oxide film and the second gate oxide film. In particular, it becomes difficult to control the thickness of the first gate oxide film.
또한, 제1게이트산화막은 감광막을 제거할 때 식각손상을 받게 되어 핀홀 ( pinhole ) 과 같은 결함이 포함될 때 낮은 전기장의 스트레스에서도 작동 불량을 일으키게 되는 로우 필드 브레이크다운 ( low field breakdown ) 이 일어나는 문제점이 있는데, 이것은 게이트산화막 이전의 세정 공정에 따른 거칠기, 오염 및 웨이퍼 자체 결함 등의 영향에 크게 의존한다.In addition, when the first gate oxide film is etched when the photoresist film is removed, a low field breakdown occurs due to a malfunction caused by low electric field stress when a defect such as a pinhole is included. This is largely dependent on the effects of roughness, contamination, and defects of the wafer itself due to the cleaning process before the gate oxide film.
도 1a 내지 도 1f 는 종래기술에 따른 반도체소자의 이중 게이트전극 형성방법을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a double gate electrode of a semiconductor device according to the related art.
먼저, 반도체기판(31)에 웰 및 소자분리막(33)을 형성한다. 이때, 상기 소자분리막(33)은 반도체기판의 활성영역을 정의한다. (도 1a)First, a well and an isolation layer 33 are formed on the semiconductor substrate 31. In this case, the device isolation layer 33 defines an active region of the semiconductor substrate. (FIG. 1A)
그 다음, 상기 반도체기판(31) 상부에 제1게이트산화막(35)을 형성한다. 그리고, 상기 제1게이트산화막(35) 상부에 감광막패턴(37)을 형성한다.Next, a first gate oxide layer 35 is formed on the semiconductor substrate 31. A photoresist pattern 37 is formed on the first gate oxide layer 35.
이때, 상기 감광막패턴(37)은 상대적으로 두꺼운 제2게이트산화막이 형성될 부분을 노출시킨다. (도 1b, 도 1c)In this case, the photoresist pattern 37 exposes a portion where a relatively thick second gate oxide film is to be formed. (FIG. 1B, FIG. 1C)
그 다음, 상기 감광막패턴(37)을 마스크로하여 상기 제1게이트산화막(35)을 식각하고 상기 감광막패턴(37)을 제거한다. (도 1d)Next, the first gate oxide layer 35 is etched using the photoresist pattern 37 as a mask to remove the photoresist pattern 37. (FIG. 1D)
그리고, 두꺼운 제2게이트산화막(39)을 형성하고 전체표면상부에 게이트전극용 도전체(41)를 형성한다. 이때, 상기 게이트전극용 도전체(41)은 다결정실리콘막으로 형성한다. (도 1e, 도 1f)Then, a thick second gate oxide film 39 is formed and a conductor 41 for a gate electrode is formed over the entire surface. In this case, the gate electrode conductor 41 is formed of a polysilicon film. (FIG. 1E, FIG. 1F)
후속 패터닝공정으로 제1게이트전극과 제2게이트전극을 형성한다.The first gate electrode and the second gate electrode are formed by a subsequent patterning process.
상기한 바와같이 종래기술에 따른 이중 게이트전극 형성방법은, 제1게이트산화막의 식각공정으로 반도체기판을 손상시킬 수 있으며, 식각공정후 남을 수 있는 감광막패턴의 잔유물로 인하여 트랜지스터의 특성이 저하되는 문제점이 있다.As described above, the method of forming the double gate electrode according to the related art may damage the semiconductor substrate by an etching process of the first gate oxide layer, and deteriorate the characteristics of the transistor due to residues of the photoresist pattern that may remain after the etching process. There is this.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여,The present invention to solve the above problems of the prior art,
불순물이 주입된 제2게이트전극용 도전체를 형성하고 후속 열공정으로 제2게이트절연막을 두껍게 형성할 수 있도록 하여 제1게이트절연막과 제2게이트절연막의 두께를 다르게 하는 이중 게이트전극 형성방법을 제공하는데 그 목적이 있다.Provided is a method of forming a double gate electrode in which a second gate electrode conductor in which impurities are implanted is formed and a second gate insulating film can be formed thick by a subsequent thermal process so that the thicknesses of the first gate insulating film and the second gate insulating film are different. Its purpose is to.
도 1a 내지 도 1f 는 종래기술의 실시예에 따른 이중 게이트전극 형성방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method of forming a double gate electrode according to an exemplary embodiment of the prior art.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 이중 게이트전극 형성방법을 도시한 단면도.2A through 2E are cross-sectional views illustrating a method of forming a double gate electrode according to an exemplary embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 소자분리막11,31: semiconductor substrate 13,33: device isolation film
15,35 : 제1게이트산화막 17,41 : 게이트전극용 도전체15,35: first gate oxide film 17,41: conductor for gate electrode
19,37 : 감광막패턴 21 : 불소 불순물19,37 photosensitive film pattern 21: fluorine impurities
23 : 반사방지막 25,39 : 제2게이트산화막23: antireflection film 25,39: second gate oxide film
100,300 : 얇은 게이트산화막이 형성되는 부분100,300: portion where a thin gate oxide film is formed
200,400 : 두꺼운 게이트산화막이 형성되는 부분200,400: portion where a thick gate oxide film is formed
이상의 목적을 달성하기 위해 본 발명에 따른 이중 게이트전극 형성방법은,In order to achieve the above object, a method of forming a double gate electrode according to the present invention,
반도체기판 상부에 웰과 소자분리막을 형성하는 공정과,Forming a well and an isolation layer on the semiconductor substrate;
상기 반도체기판 상부에 제1게이트절연막과 게이트전극용 도전체를 형성하는 공정과,Forming a first gate insulating film and a conductor for a gate electrode on the semiconductor substrate;
두꺼운 게이트절연막이 형성될 부분의 상기 게이트전극용 도전체에 불소 불순물을 임플란트 하는 공정과,Implanting a fluorine impurity into the gate electrode conductor in a portion where a thick gate insulating film is to be formed;
상기 게이트전극용 도전체 상부에 반사방지막을 형성하는 공정과,Forming an anti-reflection film on the gate electrode conductor;
상기 반사방지막, 게이트전극용 도전체 및 제1게이트절연막을 게이트전극 마스크를 이용한 식각공정으로 식각하여 게이트전극을 형성하는 공정과,Etching the anti-reflection film, the gate electrode conductor and the first gate insulating film by an etching process using a gate electrode mask to form a gate electrode;
상기 반도체기판을 열처리하여 상기 불소 불순물이 임플란트된 제1게이트절연막을 두껍게 형성함으로써 제2게이트절연막을 형성하는 공정을 포함하는 것과,Heat treating the semiconductor substrate to form a thick first gate insulating film implanted with the fluorine impurity, thereby forming a second gate insulating film;
상기 게이트전극용 도전체는 도프된 다결정실리콘으로 형성하는 것과,The gate electrode conductor may be formed of doped polycrystalline silicon,
상기 게이트전극용 도전체는 비정질 실리콘으로 형성하고 불순물을 도핑하여 형성하는 것과,The gate electrode conductor may be formed of amorphous silicon and doped with impurities.
상기 게이트전극은 게이트전극용 도전체 상부에 실리사이드가 적층된 구조로 형성되는 것을 특징으로한다.The gate electrode may be formed in a structure in which silicide is stacked on the conductor for the gate electrode.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명의 실시예에 따른 이중 게이트전극 형성방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming a double gate electrode according to an exemplary embodiment of the present invention.
먼저, 반도체기판(11)에 웰 및 소자분리막(13)을 형성한다. 이때, 상기 소자분리막(13)은 반도체기판의 활성영역을 정의한다. (도 2a)First, a well and an isolation layer 13 are formed on the semiconductor substrate 11. In this case, the device isolation layer 13 defines an active region of the semiconductor substrate. (FIG. 2A)
그 다음, 상기 반도체기판(11) 상부에 얇은 제1게이트산화막(15)을 형성한다. 그리고, 상기 제1게이트산화막(15) 상부에 게이트전극용 도전체(17)를 일정두께 형성한다.Next, a thin first gate oxide film 15 is formed on the semiconductor substrate 11. A gate electrode conductor 17 is formed on the first gate oxide layer 15 at a predetermined thickness.
이때, 상기 게이트전극용 도전체(17)은 도프된 다결정실리콘으로 형성하되, 비정질 실리콘으로 형성할 수도 있다. (도 2b)In this case, the gate electrode conductor 17 may be formed of doped polysilicon, but may be formed of amorphous silicon. (FIG. 2B)
그리고, 상기 게이트전극용 도전체(17) 상부에 감광막패턴(19)을 형성한다. 이때, 상기 감광막패턴(19)은 이중게이트전극을 형성할 수 있는 마스크를 이용한 노광 및 현상공정으로 형성한다.A photoresist pattern 19 is formed on the gate electrode conductor 17. In this case, the photoresist pattern 19 is formed by an exposure and development process using a mask capable of forming a double gate electrode.
그리고, 상기 감광막패턴(19)을 마스크로하여 상기 두꺼운 제2게이트산화막이 형성될 부분의 게이트전극용 도전체(17)에 불소를 임플란트한다.Then, fluorine is implanted into the gate electrode conductor 17 in the portion where the thick second gate oxide film is to be formed using the photoresist pattern 19 as a mask.
여기서, 상기 게이트전극용 도전체(17)로 비정질 실리콘을 사용하는 경우는 게이트전극용 도전체를 도핑한 다음, 불소를 임플란트할 수도 있다. (도 2c)In this case, when amorphous silicon is used as the gate electrode conductor 17, the gate electrode conductor may be doped and then fluorine may be implanted. (FIG. 2C)
그리고, 상기 감광막패턴(19)을 제거하고 상기 게이트전극용 도전체(17) 상부에 반사방지막(23)을 형성한다. 이때, 상기 반사방지막(23)은 산화질화막으로 형성한다.The photoresist layer pattern 19 is removed to form an anti-reflection film 23 on the gate electrode conductor 17. In this case, the anti-reflection film 23 is formed of an oxynitride film.
그리고, 게이트전극마스크(도시안됨)를 이용한 식각공정으로 반사방지막(23), 게이트전극용 도전체(17) 및 제1게이트산화막(15)을 식각하여 게이트전극을 형성한다. (도 2d)The anti-reflection film 23, the gate electrode conductor 17, and the first gate oxide film 15 are etched by an etching process using a gate electrode mask (not shown) to form a gate electrode. (FIG. 2D)
그 다음, 열처리공정을 실시하여 상기 불소가 이온주입된 부분의 제1게이트산화막(15)이 두껍게 열산화되어 제2게이트산화막(25)을 형성한다.Then, the first gate oxide film 15 in the portion where the fluorine is ion implanted is thermally thickened to form a second gate oxide film 25 by performing a heat treatment process.
이로인하여, 두께가 다른 게이트산화막(15,25)으로 인하여 특성이 다른 두개의 게이트전극을 형성한다. (도 2e)As a result, two gate electrodes having different characteristics are formed due to the gate oxide films 15 and 25 having different thicknesses. (FIG. 2E)
본 발명의 실시예에서 상기 게이트전극용 도전체는 실리콘과 실리사이드의 적층구조로 형성할 수도 있다.In an embodiment of the present invention, the gate electrode conductor may be formed of a stacked structure of silicon and silicide.
이상에서 설명한 바와같이 본 발명에 따른 이중 게이트전극 형성방법은, 제1게이트산화막의 식각공정이나 반도체기판과 감광막의 접촉을 방지하여 식각공정시 기판의 손상을 방지하는 동시에 감광막 잔유물로 인한 트랜지스터의 특성 열화를 방지함으로써 반도체소자의 특성 및 신뢰성을 향상시키는 효과가 있다.As described above, the method of forming the double gate electrode according to the present invention prevents damage of the substrate during the etching process by preventing the etching process of the first gate oxide film or the contact between the semiconductor substrate and the photosensitive film, and the characteristics of the transistor due to the photoresist residue. By preventing deterioration, there is an effect of improving the characteristics and reliability of the semiconductor device.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980062024A KR20000045466A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating dual gate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980062024A KR20000045466A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating dual gate electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000045466A true KR20000045466A (en) | 2000-07-15 |
Family
ID=19568720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980062024A KR20000045466A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating dual gate electrode |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000045466A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101147868B1 (en) * | 2005-02-22 | 2012-05-24 | 삼성전자주식회사 | method for fabricating semiconductor device having dual work function metal gate electrodes and semiconductor device fabricated therby |
-
1998
- 1998-12-30 KR KR1019980062024A patent/KR20000045466A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101147868B1 (en) * | 2005-02-22 | 2012-05-24 | 삼성전자주식회사 | method for fabricating semiconductor device having dual work function metal gate electrodes and semiconductor device fabricated therby |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4808555A (en) | Multiple step formation of conductive material layers | |
| JP3746907B2 (en) | Manufacturing method of semiconductor device | |
| KR19990087022A (en) | Method for manufacturing semiconductor device | |
| KR100280525B1 (en) | Manufacturing method of semiconductor device | |
| KR20000045466A (en) | Method for fabricating dual gate electrode | |
| KR100226733B1 (en) | Manufacture of semiconductor device | |
| US6667243B1 (en) | Etch damage repair with thermal annealing | |
| KR100334869B1 (en) | Forming method for gate electronic of semiconductor device | |
| KR100215871B1 (en) | Method for fabricating semiconductor device | |
| US6573192B1 (en) | Dual thickness gate oxide fabrication method using plasma surface treatment | |
| KR20080087282A (en) | Method for fabricating dual poly gate in semiconductor device | |
| KR19990070036A (en) | Manufacturing method of semiconductor device | |
| KR100247811B1 (en) | Method for manufacturing semiconductor device | |
| KR100280537B1 (en) | Semiconductor device manufacturing method | |
| KR100628218B1 (en) | method for manufacturing of semiconductor device | |
| KR0124637B1 (en) | Method of forming the isolation on semiconductor device | |
| KR100250686B1 (en) | Manufacturing method of a semiconductor device | |
| KR100567047B1 (en) | Menufacturing method for mos transistor | |
| KR100595861B1 (en) | Method for fabricating semiconductor device | |
| KR950021133A (en) | Semiconductor device manufacturing method | |
| KR20030056607A (en) | Method of manufacturing a semiconductor device | |
| KR19980055970A (en) | Transistor manufacturing method | |
| KR19980052419A (en) | Method for manufacturing field effect transistor of semiconductor device | |
| KR19990010370A (en) | Method for forming via contact hole in semiconductor device | |
| KR20030001764A (en) | method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |